Based on prior work by Andy Fleming <afleming@freescale.com>
Signed-off-by: Shruti Kanetkar <Shruti@freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
power-isa-version and power-isa-* are cpu node general properties defined
in ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of a property named power-isa-[CAT], where [CAT] is the
abbreviated category name with all uppercase letters converted to
lowercase, indicates that the category is supported by the implementation.
The patch update all the e500mc platforms.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.
Other changes include:
* Adding of MPIC timer blocks
* Dropping "fsl,p2041-IP..." from compatibles for standard blocks
* Removed mpic interrupt-parent from dcsr-epu node, just use top level
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
