Commit Graph

4526 Commits

Author SHA1 Message Date
Ulf Hansson
4d3d534e9f Merge branch 'fixes' into next 2019-02-28 12:19:51 +01:00
BOUGH CHEN
e30be063d6 mmc: sdhci-esdhc-imx: correct the fix of ERR004536
Commit 18094430d6 ("mmc: sdhci-esdhc-imx: add ADMA Length
Mismatch errata fix") involve the fix of ERR004536, but the
fix is incorrect. Double confirm with IC, need to clear the
bit 7 of register 0x6c rather than set this bit 7.
Here is the definition of bit 7 of 0x6c:
    0: enable the new IC fix for ERR004536
    1: do not use the IC fix, keep the same as before

Find this issue on i.MX845s-evk board when enable CMDQ, and
let system in heavy loading.

root@imx8mmevk:~# dd if=/dev/mmcblk2 of=/dev/null bs=1M &
root@imx8mmevk:~# memtester 1000M > /dev/zero &
root@imx8mmevk:~# [  139.897220] mmc2: cqhci: timeout for tag 16
[  139.901417] mmc2: cqhci: ============ CQHCI REGISTER DUMP ===========
[  139.907862] mmc2: cqhci: Caps:      0x0000310a | Version:  0x00000510
[  139.914311] mmc2: cqhci: Config:    0x00001001 | Control:  0x00000000
[  139.920753] mmc2: cqhci: Int stat:  0x00000000 | Int enab: 0x00000006
[  139.927193] mmc2: cqhci: Int sig:   0x00000006 | Int Coal: 0x00000000
[  139.933634] mmc2: cqhci: TDL base:  0x7809c000 | TDL up32: 0x00000000
[  139.940073] mmc2: cqhci: Doorbell:  0x00030000 | TCN:      0x00000000
[  139.946518] mmc2: cqhci: Dev queue: 0x00010000 | Dev Pend: 0x00010000
[  139.952967] mmc2: cqhci: Task clr:  0x00000000 | SSC1:     0x00011000
[  139.959411] mmc2: cqhci: SSC2:      0x00000001 | DCMD rsp: 0x00000000
[  139.965857] mmc2: cqhci: RED mask:  0xfdf9a080 | TERRI:    0x00000000
[  139.972308] mmc2: cqhci: Resp idx:  0x0000002e | Resp arg: 0x00000900
[  139.978761] mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
[  139.985214] mmc2: sdhci: Sys addr:  0xb2c19000 | Version:  0x00000002
[  139.991669] mmc2: sdhci: Blk size:  0x00000200 | Blk cnt:  0x00000400
[  139.998127] mmc2: sdhci: Argument:  0x40110400 | Trn mode: 0x00000033
[  140.004618] mmc2: sdhci: Present:   0x01088a8f | Host ctl: 0x00000030
[  140.011113] mmc2: sdhci: Power:     0x00000002 | Blk gap:  0x00000080
[  140.017583] mmc2: sdhci: Wake-up:   0x00000008 | Clock:    0x0000000f
[  140.024039] mmc2: sdhci: Timeout:   0x0000008f | Int stat: 0x00000000
[  140.030497] mmc2: sdhci: Int enab:  0x107f4000 | Sig enab: 0x107f4000
[  140.036972] mmc2: sdhci: AC12 err:  0x00000000 | Slot int: 0x00000502
[  140.043426] mmc2: sdhci: Caps:      0x07eb0000 | Caps_1:   0x8000b407
[  140.049867] mmc2: sdhci: Cmd:       0x00002c1a | Max curr: 0x00ffffff
[  140.056314] mmc2: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0xffffffff
[  140.062755] mmc2: sdhci: Resp[2]:   0x328f5903 | Resp[3]:  0x00d00f00
[  140.069195] mmc2: sdhci: Host ctl2: 0x00000008
[  140.073640] mmc2: sdhci: ADMA Err:  0x00000007 | ADMA Ptr: 0x7809c108
[  140.080079] mmc2: sdhci: ============================================
[  140.086662] mmc2: running CQE recovery

Fixes: 18094430d6 ("mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fix")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-28 12:18:31 +01:00
Ulf Hansson
82b6248705 Merge branch 'fixes' into next 2019-02-28 09:16:18 +01:00
BOUGH CHEN
85236d2be8 mmc: sdhci-esdhc-imx: clear the HALT bit when enable CQE
After system suspend, CQE is in cqhci_off state, which set the HALT bit, make
CQE in HALT state. If the SoC do not power down the USDHC module, then when
system resume back, this bit keep the same, still set. Though there is a
sdhci reset during sdhci_resume_host(), but this reset do not impact the
CQE part, so need to clear this bit when enable CQE, otherwise CQE will
stuck in the first CMDQ request after system resume back.

Find this issue on NXP i.MX845s-mek board

[  105.919862] mmc2: cqhci: timeout for tag 6
[  105.923965] mmc2: cqhci: ============ CQHCI REGISTER DUMP ===========
[  105.930407] mmc2: cqhci: Caps:      0x0000310a | Version:  0x00000510
[  105.936847] mmc2: cqhci: Config:    0x00001001 | Control:  0x00000001
[  105.943286] mmc2: cqhci: Int stat:  0x00000000 | Int enab: 0x00000006
[  105.949725] mmc2: cqhci: Int sig:   0x00000006 | Int Coal: 0x00000000
[  105.956164] mmc2: cqhci: TDL base:  0x7809b000 | TDL up32: 0x00000000
[  105.962604] mmc2: cqhci: Doorbell:  0x00000040 | TCN:      0x00000000
[  105.969043] mmc2: cqhci: Dev queue: 0x00000000 | Dev Pend: 0x00000000
[  105.975483] mmc2: cqhci: Task clr:  0x00000000 | SSC1:     0x00011000
[  105.981922] mmc2: cqhci: SSC2:      0x00000001 | DCMD rsp: 0x00000000
[  105.988362] mmc2: cqhci: RED mask:  0xfdf9a080 | TERRI:    0x00000000
[  105.994801] mmc2: cqhci: Resp idx:  0x00000000 | Resp arg: 0x00000000
[  106.001240] mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
[  106.007680] mmc2: sdhci: Sys addr:  0xb2b37800 | Version:  0x00000002
[  106.014120] mmc2: sdhci: Blk size:  0x00000200 | Blk cnt:  0x00000001
[  106.020560] mmc2: sdhci: Argument:  0x00010000 | Trn mode: 0x00000013
[  106.026999] mmc2: sdhci: Present:   0x01f88008 | Host ctl: 0x00000030
[  106.033439] mmc2: sdhci: Power:     0x00000002 | Blk gap:  0x00000080
[  106.039878] mmc2: sdhci: Wake-up:   0x00000008 | Clock:    0x0000000f
[  106.046318] mmc2: sdhci: Timeout:   0x0000008f | Int stat: 0x00000000
[  106.052757] mmc2: sdhci: Int enab:  0x107f4000 | Sig enab: 0x107f4000
[  106.059196] mmc2: sdhci: AC12 err:  0x00000000 | Slot int: 0x00000502
[  106.065635] mmc2: sdhci: Caps:      0x07eb0000 | Caps_1:   0x8000b407
[  106.072075] mmc2: sdhci: Cmd:       0x00000d1a | Max curr: 0x00ffffff
[  106.078514] mmc2: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0x31360181
[  106.084954] mmc2: sdhci: Resp[2]:   0x44473430 | Resp[3]:  0x00450100
[  106.091392] mmc2: sdhci: Host ctl2: 0x00000008
[  106.095836] mmc2: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x7804b208
[  106.102274] mmc2: sdhci: ============================================
[  106.108785] mmc2: running CQE recovery

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-28 09:16:12 +01:00
Alamy Liu
d07e9fadf3 mmc: cqhci: Fix a tiny potential memory leak on error condition
Free up the allocated memory in the case of error return

The value of mmc_host->cqe_enabled stays 'false'. Thus, cqhci_disable
(mmc_cqe_ops->cqe_disable) won't be called to free the memory.  Also,
cqhci_disable() seems to be designed to disable and free all resources, not
suitable to handle this corner case.

Fixes: a4080225f5 ("mmc: cqhci: support for command queue enabled host")
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-27 15:06:45 +01:00
Alamy Liu
27ec9dc17c mmc: cqhci: fix space allocated for transfer descriptor
There is not enough space being allocated when DCMD is disabled.

CQE_DCMD is not necessary to be enabled when CQE is enabled.
(Software could halt CQE to send command)

In the case that CQE_DCMD is not enabled, it still needs to allocate
space for data transfer. For instance:
  CQE_DCMD is enabled:  31 slots space (one slot used by DCMD)
  CQE_DCMD is disabled: 32 slots space

Fixes: a4080225f5 ("mmc: cqhci: support for command queue enabled host")
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-27 15:06:31 +01:00
Takeshi Saito
5603731a15 mmc: tmio: fix access width of Block Count Register
In R-Car Gen2 or later, the maximum number of transfer blocks are
changed from 0xFFFF to 0xFFFFFFFF. Therefore, Block Count Register
should use iowrite32().

If another system (U-boot, Hypervisor OS, etc) uses bit[31:16], this
value will not be cleared. So, SD/MMC card initialization fails.

So, check for the bigger register and use apropriate write. Also, mark
the register as extended on Gen2.

Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>
[wsa: use max_blk_count in if(), add Gen2, update commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: stable@kernel.org
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
[Ulf: Fixed build error]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-26 10:01:49 +01:00
Sergei Shtylyov
5c27ff5db1 mmc: tmio_mmc_core: don't claim spurious interrupts
I have encountered an interrupt storm during the eMMC chip probing (and
the chip finally didn't get detected).  It turned out that U-Boot left
the DMAC interrupts enabled while the Linux driver  didn't use those.
The SDHI driver's interrupt handler somehow assumes that, even if an
SDIO interrupt didn't happen, it should return IRQ_HANDLED.  I think
that if none of the enabled interrupts happened and got handled, we
should return IRQ_NONE -- that way the kernel IRQ code recoginizes
a spurious interrupt and masks it off pretty quickly...

Fixes: 7729c7a232 ("mmc: tmio: Provide separate interrupt handlers")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 17:25:13 +01:00
Jonathan Neuschäfer
c9bd505dbd mmc: spi: Fix card detection during probe
When using the mmc_spi driver with a card-detect pin, I noticed that the
card was not detected immediately after probe, but only after it was
unplugged and plugged back in (and the CD IRQ fired).

The call tree looks something like this:

mmc_spi_probe
  mmc_add_host
    mmc_start_host
      _mmc_detect_change
        mmc_schedule_delayed_work(&host->detect, 0)
          mmc_rescan
            host->bus_ops->detect(host)
              mmc_detect
                _mmc_detect_card_removed
                  host->ops->get_cd(host)
                    mmc_gpio_get_cd -> -ENOSYS (ctx->cd_gpio not set)
  mmc_gpiod_request_cd
    ctx->cd_gpio = desc

To fix this issue, call mmc_detect_change after the card-detect GPIO/IRQ
is registered.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 15:40:36 +01:00
Ulf Hansson
643108630e mmc: of_mmc_spi: Convert to mmc_of_parse_voltage()
Let's drop the open-coding of the parsing of the "voltage-ranges" DT
property and convert to use the common mmc_of_parse_voltage() API instead.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 15:20:58 +01:00
Takeshi Saito
f0c8234cb9 mmc: renesas_sdhi: Change HW adjustment register according to speed mode
SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF
according to the mode. If it is inappropriate, CRC error tends to occur.

This adds variable "tap_hs400" for HS400 mode and configures SCC_DT2FF
as needed.

Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>
[wsa: rebased to upstream and updated commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund@ragnatech.se>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 14:45:59 +01:00
Ulf Hansson
e9968c6fa8 mmc: mmci: Send a CMD12 to clear the DPSM at errors
The current approach with sending a CMD12 (STOP_TRANSMISSION) to complete a
data transfer request, either because of using the open-ended transmission
type or because of receiving an error during a pre-defined data transfer,
isn't sufficient for the STM32 sdmmc variant. More precisely, this variant
needs to clear the DPSM ("Data Path State Machine") by sending a CMD12, for
all failing ADTC commands.

Support this, by adding a struct mmc_command inside the struct mmci_host
and initialize it to a CMD12 during ->probe(). Let's also add checks for
the new conditions, to enable mmci_data_irq() and mmci_cmd_irq() to
postpone the calls to mmci_request_end(), but instead send the CMD12.

Cc: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Ludovic Barre <ludovic.barre@st.com>
2019-02-25 08:40:58 +01:00
Gustavo A. R. Silva
e9d6a371cf mmc: sdhci-xenon: Fixup already marked switch fall-through
In preparation to enabling -Wimplicit-fallthrough, mark switch cases
according to what the compiler looks for, where we are expecting to fall
through.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Thomas Petazzoni
e8391453e2 mmc: sdhci-tegra: drop ->get_ro() implementation
The SDHCI core is know properly checking for the state of a WP GPIO,
so there is no longer any need for the sdhci-tegra code to implement
->get_ro() using mmc_gpio_get_ro().

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Thomas Petazzoni
39ee32ce48 mmc: sdhci-omap: drop ->get_ro() implementation
The SDHCI core is now properly checking for the state of a WP GPIO,
so there is no longer any need for the sdhci-omap code to implement
->get_ro() using mmc_gpio_get_ro().

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Thomas Petazzoni
6d5cd068ee mmc: sdhci: use WP GPIO in sdhci_check_ro()
Even though SDHCI controllers may have a dedicated WP pin that can be
queried using the SDHCI_PRESENT_STATE register, some platforms may
chose to use a separate regular GPIO to route the WP signal. Such a
GPIO is typically represented using the wp-gpios property in the
Device Tree.

Unfortunately, the current sdhci_check_ro() function does not make use
of such GPIO when available: it either uses a host controller specific
->get_ro() operation, or uses the SDHCI_PRESENT_STATE. Several host
controller specific ->get_ro() functions are implemented just to check
a WP GPIO state.

Instead of pushing this to more controller-specific implementations,
let's handle this in the core SDHCI code, just like it is already done
for the CD GPIO in sdhci_get_cd().

The below patch simply changes sdhci_check_ro() to use the value of
the WP GPIO if available.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Linus Walleij
70bcc9e3a8 mmc: wmt-sdmmc: Drop unused include
The WMT SDMMC driver uses slot GPIO helpers and does not make
any use of <linux/gpio.h> so drop this surplus include.

Cc: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Linus Walleij
bed12fb0a3 mmc: sunxi-mmc: Drop unused includes
The Sunxi MMC driver uses slot GPIO helpers and does not make
any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these
surplus includes.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: cenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Linus Walleij
3557cba7e5 mmc: sdhci-pxav2: Drop unused include
The SDHCI PXAv2 driver uses slot GPIO helpers and does not make
any use of <linux/gpio.h> so drop this surplus include.

Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Linus Walleij
43ea6c9ad9 mmc: sdhci-bcm-kona: Drop unused includes
The SDHCI BCM Kona driver uses slot GPIO helpers and does not
make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these
surplus includes.

Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Linus Walleij
b7a7da5644 mmc: mxs-mmc: Drop unused includes
The MXS-MMC driver uses slot GPIO helpers and does not make
any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these
surplus includes.

Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Linus Walleij
05b3a5e5f8 mmc: mxcmmc: Drop unused includes
The MXCMMC driver uses slot GPIO helpers and does not make
any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these
surplus includes.

Cc: Jun Qian <hangdianqj@163.com>
Cc: Matteo Facchinetti <matteo.facchinetti@sirius-es.it>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Colin Ian King
c16e9b7656 mmc: cb710: fix indentation issue in if block
There is an if block that is not indented, fix this.  Also add a
break statement on the default case to clean up a cppcheck warning.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Linus Walleij
a2b760a601 mmc: slot-gpio: Remove override_active_level on WP
The argument "override_active_level" made it possible to
enforce a specific polarity on the write-protect
GPIO line. All callers in the kernel pass "false" to this
call after I have converted all drivers to use GPIO machine
descriptors, so remove the argument and clean out this.

This kind of polarity inversion should be handled by the
GPIO descriptor inside the GPIO library if needed.

This rids us of one instance of the kludgy calls into
the gpiod_get_raw_value() API.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Lukas Wunner
9cda3e7ceb mmc: bcm2835: Deduplicate reset of driver data on remove
The BCM2835 MMC host driver sets the device's driver data pointer to
NULL on ->remove() even though the driver core subsequently does the
same in __device_release_driver().  Drop the duplicate assignment.

Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Lukas Wunner
c58ccf2b6d mmc: bcm2835: Drop pointer to mmc_host from bcm2835_host
The BCM2835 MMC host driver uses a pointer to get from the private
bcm2835_host structure to the generic mmc_host structure.  However the
latter is always immediately preceding the former in memory, so compute
its address with a subtraction (which is cheaper than a dereference) and
drop the superfluous pointer.

No functional change intended.

Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Alexander Graf <agraf@suse.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Lukas Wunner
e5c1e63c93 mmc: bcm2835: Drop DMA channel error pointer check
bcm2835_add_host() invokes IS_ERR_OR_NULL() on a DMA channel pointer,
however dma_request_slave_channel() (which was used to populate the
pointer) never returns an error pointer.  So a NULL pointer check is
sufficient.

Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Aaro Koskinen
a6327b5e57 mmc: omap: fix the maximum timeout setting
When running OMAP1 kernel on QEMU, MMC access is annoyingly noisy:

	MMC: CTO of 0xff and 0xfe cannot be used!
	MMC: CTO of 0xff and 0xfe cannot be used!
	MMC: CTO of 0xff and 0xfe cannot be used!
	[ad inf.]

Emulator warnings appear to be valid. The TI document SPRU680 [1]
("OMAP5910 Dual-Core Processor MultiMedia Card/Secure Data Memory Card
(MMC/SD) Reference Guide") page 36 states that the maximum timeout is 253
cycles and "0xff and 0xfe cannot be used".

Fix by using 0xfd as the maximum timeout.

Tested using QEMU 2.5 (Siemens SX1 machine, OMAP310), and also checked on
real hardware using Palm TE (OMAP310), Nokia 770 (OMAP1710) and Nokia N810
(OMAP2420) that MMC works as before.

[1] http://www.ti.com/lit/ug/spru680/spru680.pdf

Fixes: 730c9b7e66 ("[MMC] Add OMAP MMC host driver")
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Sowjanya Komatineni
3c4019f979 mmc: tegra: HW Command Queue Support for Tegra SDMMC
This patch adds HW Command Queue for supported Tegra SDMMC
controllers.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Sowjanya Komatineni
4c4faff62b mmc: sdhci: Add ADMA3 DMA support for V4 enabled host
Below are the supported DMA types in Host Control1 Register
with Version 4 enable
b'00 - SDMA
b'01 - Not Used
b'10 - ADMA2
b'11 - ADMA2 or ADMA3

ADMA3 uses Command Descriptor to issue an SD command.
A multi-block data transfer is performed by using a pair of CMD
descriptor and ADMA2 descriptor.

ADMA3 performs multiple of multi-block data transfer by using
Integrated Descriptor which is more suitable for Command Queuing
to fetch both Command and Transfer descriptors.

Host Capabilities register indicates the supports of ADMA3 DMA.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Nicolas Ferre
b1d14045f1 mmc: atmel-mci: enable 8 bits buswidth support
This patch adds support for 8-bit buswidth.
Relevant SDCR value modified.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Takeshi Saito
d30ae056ad mmc: renesas_sdhi: Fix card initialization failure in high speed mode
This fixes card initialization failure in high speed mode.

If U-Boot uses SDR or HS200/400 mode before starting Linux and Linux
DT does not enable SDR/HS200/HS400 mode, card initialization fails in
high speed mode.

It is necessary to initialize SCC registers during card initialization
phase. HW reset function is registered only for a port with either of
SDR/HS200/HS400 properties in device tree. If SDR/HS200/HS400 properties
are not present in device tree, SCC registers will not be reset. In SoC
that support SCC registers, HW reset function should be registered
regardless of the configuration of device tree.

Reproduction procedure:
- Use U-Boot that support MMC HS200/400 mode.
- Delete HS200/HS400 properties in device tree.
  (Delete mmc-hs200-1_8v and mmc-hs400-1_8v)
- MMC port works high speed mode and all commands fail.

Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Cc: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Paul Cercueil
0539552745 mmc: jz4740: Remove platform data and use standard APIs
Drop the custom code to get the 'cd' and 'wp' GPIOs. The driver now
calls mmc_of_parse() which will init these from devicetree or
device properties.

Also drop the custom code to get the 'power' GPIO. The MMC core
provides us with the means to power the MMC card through an external
regulator.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Ernest Zhang(WH)
414126f9e5 mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller
O2 SD host controller only need set the quirk2 flag
SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD when
work on force 1.8v emmc mode but not normal mode

Signed-off-by: Ernest Zhang <ernest.zhang@bayhubtech.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Mathieu Malaterre
7f76e46841 mmc: jz4740: Annotate implicit fall through
There is a plan to build the kernel with -Wimplicit-fallthrough and
these places in the code produced warnings (W=1).

This commit removes the following warnings:

  drivers/mmc/host/jz4740_mmc.c:745:3: warning: this statement may fall through [-Wimplicit-fallthrough=]
  drivers/mmc/host/jz4740_mmc.c:779:3: warning: this statement may fall through [-Wimplicit-fallthrough=]

Signed-off-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Wei Yongjun
9a633f3bfb mmc: sdhci-esdhc-imx: fix return value check in sdhci_esdhc_imx_probe()
In case of error, the function devm_kzalloc() returns NULL pointer not
ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.

Fixes: fadac7488064 ("mmc: sdhci-esdhc-imx: add CMDQ support")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Sowjanya Komatineni
de25fa5a1a mmc: tegra: SDMMC pads auto-calibration
Program initial drive code offsets which will be used by auto
calibration process.

Program fixed drive strengths for SDMMC pads in pad control
register when auto cal timeouts.
Fixed settings are based on Pre-SI analysis of the pad design.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
BOUGH CHEN
bcdb530125 mmc: sdhci-esdhc-imx: add DCMD support for CMDQ
Currently, USDHC do not generate transfer complete interrupt
when send a non-data-command with R1b response. But if want
to support DCMD in CMDQ, need to change this, the DCMD IC
logic require the USDHC to enable this function, otherwise
DCMD will never get a CC(command complete) interrupt.

This patch set ESDHC_VEND_SPEC2_EN_BUSY_IRQ and add DCMD support.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
BOUGH CHEN
bb6e358169 mmc: sdhci-esdhc-imx: add CMDQ support
Add CMDQ support for imx8qm/imx8qxp.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
[Ulf: Rebased on top of latest changes]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
BOUGH CHEN
401059df9b mmc: sdhci: correct the maximum timeout when enable CMDQ
Change to use sdhci_set_timeout() to set the maximum timeout, so that
the host can use it's own set_timeout() callback to set the maximum
timeout if the host has.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
BOUGH CHEN
029e2476f9 mmc: sdhci-esdhc-imx: add HS400_ES support for i.MX8QXP
Add an new esdhc_soc_data for i.MX8QXP, and add HS400_ES mode
support.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
[Ulf: Rebased on top of latest changes]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
BOUGH CHEN
2b0efe8204 mmc: sdhci-esdhc-imx: remove the 100MHz limitation for Strobe DLL
For some eMMC, after switch to HS400ES mode, it need to config the strobe
dll target dealy even if the clock is 50MHZ or 25MHz, otherwise will meet
CMD index/crc error when send CMD13 to check the switch status.

[    2.473915] IRQ status 0x000a8001
[    2.473934] mmc2: mmc_select_hs400es failed, error -84
[    2.473938] mmc2: error -84 whilst initialising MMC card

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Niklas Söderlund
bb60023c63 mmc: tmio: undo PM autosuspend when removing the host
When removing the driver make sure to undo the PM autosuspend configured
when probing the host.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Niklas Söderlund
0c134535e8 mmc: tmio: fix typo in tmio_mmc_init_ocr()
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Ernest Zhang(WH)
69d91ed146 mmc: sdhci: Fix O2 Host PLL and card detect issue
1. O2 Host Controller PLL lock status is not in compliance with
CLOCK_CONTROL register bit 1
2. O2 Host Controller card detect function only work when PLL is
enabled and locked

Signed-off-by: Ernest Zhang <ernest.zhang@bayhubtech.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Ernest Zhang(WH)
328be8bed2 mmc: sdhci: Moving sdhci_o2 into sdhci-pci-o2micro.c
Moving sdhci_o2 into sdhci-pci-o2micro.c

Signed-off-by: Ernest Zhang <ernest.zhang@bayhubtech.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
Stefan Wahren
1e20186e70 mmc: sdhci-brcmstb: handle mmc_of_parse() errors during probe
We need to handle mmc_of_parse() errors during probe otherwise the
MMC driver could start without proper initialization (e.g. power sequence).

Fixes: 476bf3d62d ("mmc: sdhci-brcmstb: Add driver for Broadcom BRCMSTB SoCs")
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
BOUGH CHEN
2b06e1597a mmc: sdhci: add delay after the last tuning command
When host set the host->tuning_delay, even the last tuning
command need a delay, otherwise the first command after the
tuning will meet issue.

Take i.MX7D as an example, there will be the following log:
  mmc2: switch to high-speed from hs200 failed, err:-110
  mmc2: error -110 whilst initialising MMC card

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
BOUGH CHEN
d00ab1010c mmc: sdhci-esdhc-imx: add delay between tuning cycles
It's observed that i.MX uSDHC needed delay between tuning
cycles for HS200 successful tuning. This patch is to set 1ms
delay for that.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00
BOUGH CHEN
af6a50d457 mmc: sdhci-esdhc-imx: add SD clock limitation for imx6ull
i.MX6ULL has errata ERR010450, point out that due to SOC I/O
timing limitation, for eMMC HS200 and SD/SDIO 3.0 SDR104, the
clock rate can't exceed 150MHz. And for eMMC DDR52 and SD/SDIO
DDR50 mode, the clock rate can't exceed 45MHz.

This patch add this limit for imx6ull.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
[Ulf: Fixed comments and whitespace]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25 08:40:58 +01:00