AuxXxilium/linux_dsm_epyc7002
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2 Commits

Author SHA1 Message Date
Anson Huang
8efaf5ed4d clk: imx: increase AXI clock rate to 264MHz for i.MX6UL 
On i.MX6UL, AXI clock rate's design target is 264MHz, but by default
it is only set to 198MHz which is NOT good enough for performance,
this patch increases AXI clock rate from 198MHz to 264MHz to meet
the design target, this is done by switching its parent clock
"periph" from 396MHz PFD to 528MHz PLL.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
 2015-09-17 08:52:17 +08:00
Frank Li
787b4271a6 clk: imx: add imx6ul clk tree support 
Add imx6ul clock driver support.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Bai Ping <b51503@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
 2015-07-14 15:02:13 +08:00