Commit Graph

2857 Commits

Author SHA1 Message Date
Rajendra Nayak
52111672f7 clk: qcom: gdsc: Add GDSCs in msm8996 GCC
Add all data for the GDSCs which are part of msm8996 GCC block

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:26:19 -08:00
Rajendra Nayak
a823bb9fbe clk: qcom: gdsc: Add support for votable gdscs
Some gdscs might be controlled via voting registers and might not
really disable when the kernel intends to disable them (due to other
votes keeping them enabled)
Mark these gdscs with a flag for we do not check/wait on a disable
status for these gdscs within the kernel disable callback.

Also at boot, if these GDSCs are found to be ON, we make sure we
vote for them before we inform the genpd framework about their
status. If genpd gets no users, it then disables (removes the vote)
them as part of genpd_poweroff_unused()

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:24:53 -08:00
Rajendra Nayak
77b1067a19 clk: qcom: gdsc: Add support for gdscs with gds hw controller
Some gdsc power domains can have a gds_hw_controller block inside
to help ensure all slave devices within the power domain are idle
before the gdsc is actually switched off.
This is mainly useful in power domains which host a MMU, in which
case its necessary to make sure there are no outstanding MMU operations
or pending bus transactions before the power domain is turned off.

In gdscs with gds_hw_controller block, its necessary to check the
gds_hw_ctrl status bits instead of the ones in gdscr, to determine
the state of the powerdomain.

While at it, also move away from using jiffies and use ktime APIs
instead for busy looping on status bits.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:24:03 -08:00
Rajendra Nayak
c2c7f0a474 clk: qcom: gdsc: Add support for hierarchical power domains
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs
specify the parents (if any) and the driver add genpd subdomains for them.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:24:00 -08:00
Maxime Ripard
b0b6413f0d clk: sunxi: Remove clk_register_clkdev calls
Now that our protection code doesn't use the global name lookup anymore, we
can remove the clkdev registrations.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 20:05:47 +01:00
Maxime Ripard
3a4d9af48a clk: sunxi: Remove old probe and protection code
Now that we don't have any user left for the old registration code, we can
remove it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 20:05:47 +01:00
Maxime Ripard
c087230875 clk: sunxi: convert current clocks registration to CLK_OF_DECLARE
The current clock registration and protection code has a few drawbacks, the
two main ones being that we create a lot of orphans clock in the
registration phase, which will be troublesome when we will start being less
relaxed about them.

The protection code also relies on clkdev, which we don't really use but
for this particular case.

Fix both at the same time by moving everyone to the CLK_OF_DECLARE that
will probe our clock tree in the right and thus avoid orphans, and by
protecting directly the clock returned by our registration function.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 20:05:46 +01:00
Maxime Ripard
5b5226d17d clk: sunxi: Make clocks setup functions take const pointer
All the data structure that we pass to the clocks setup functions are
declared const, while our setup functions expects a regular pointer. This
was hidden by the fact that we cast a void * pointer back to these
structures, which made it go unnoticed.

Fix the functions prototype.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 18:17:04 +01:00
Maxime Ripard
96f185ac9a clk: sunxi: Make clocks setup functions return their clock
The clocks registration code in clk-sunxi was most of the time not
returning the struct clk (or struct clk array) that was registered,
preventing the users of such functions to manipulate it, for example to
protect it.

Make them return it so that we can start using it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 18:17:03 +01:00
Sylvain Lemieux
7e0810c948 clk: lpc32xx: add HCLK PLL output configuration
This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.

If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.

The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10 12:45:16 -08:00
Stephen Boyd
58bb621536 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: versatile: mask VCO bits before writing
2016-02-10 12:44:33 -08:00
Linus Walleij
df9cd56421 clk: versatile: mask VCO bits before writing
The Versatile syscon ICST driver OR:s the bits into place but
forgets to mask the previous value, making the code only work
if the register is zero or giving haphazard results. Mask the
19 bits used by the Versatile syscon interface register.

Regression caused and now fixed by yours truly.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Fixes: 179c8fb3c2 ("clk: versatile-icst: convert to use regmap")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10 09:56:31 -08:00
Sylvain Lemieux
4db9a9ba60 clk: lpc32xx: do not register clock "0"
The following errors are display in the console during the power-on:
[    0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12
[    0.000000] lpc32xx_clk_init: failed to register (null) clock: -12

There is no need to register clock "0"; the first clock used is 1;

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
[sboyd@codeaurora.org: s/prepare/register/]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09 16:19:34 -08:00
Masahiro Yamada
2430a94d1e clk: fix __clk_init_parent() for single parent clocks
Before commit b3d192d5121f ("clk: simplify __clk_init_parent()"),
__clk_init_parent() called .get_parent() only for multi-parent
clocks.  That commit changed the behavior to call .get_parent()
if available even for single-parent clocks and root clocks.

It turned out a problem because there are some single-parent clocks
that implement .get_parent() callback and return non-zero index.
The SOCFPGA clock is the case; the commit broke the SOCFPGA boards.

To keep the original behavior, invoke .get_parent() only when
num_parents is greater than 1.

Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09 10:18:48 -08:00
Sudip Mukherjee
66f5ce2538 clk: qcom: common: check for failure
We were not checking the return from devm_add_action() which can fail.
Start using the helper and devm_add_action_or_reset() and return
directly as we know that the cleanup has been done by this helper.

Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 17:06:43 -08:00
Andreas Färber
bb473593c8 clk: meson: Fix meson_clk_register_clks() signature type mismatch
As preparation for arm64 based mesongxbb, which pulls in this code once
enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch.
The loop uses a local unsigned int variable, so adopt that type,
matching the header.

Fixes: 7a29a86943 ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:22:44 -08:00
Arnd Bergmann
60ea57a433 clk: socfpga: fix __init annotation
clang found a bug with the __socfpga_pll_init definition:

drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and
      global variables

This moves the __init annotation to the right place so the function
actually gets discarded.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:13:31 -08:00
Mike Looijmans
c7d5a46b10 drivers/clk/Kconfig: Move the TI CDCE chips close together
There are two TI CDCE clock chips in this file. Move them close
together so they're easier to find.

No functional change, just cosmetic.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Alphabetize]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:10:32 -08:00
Mike Looijmans
048c58b4e1 drivers/clk/Kconfig: Fix typo "Sypport" instead of "Support"
Simple cosmetic fix.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:09:49 -08:00
Stephen Boyd
f2626ba965 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: tegra: super: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warning for pll_m
  clk: tegra: Use definition for pll_u override bit
  clk: tegra: Fix warning caused by pll_u failing to lock
  clk: tegra: Fix clock sources for Tegra210 EMC
  clk: tegra: Add the APB2APE audio clock on Tegra210
  clk: tegra: Add missing of_node_put()
  clk: tegra: Fix PLLE SS coefficients
  clk: tegra: Fix typos around clearing PLLE bits during enable
  clk: tegra: Do not disable PLLE when under hardware control
  clk: tegra: Fix pllx dyn step calculation
  clk: tegra: pll: Fix potential sleeping-while-atomic
  clk: tegra: Fix the misnaming of nvenc from msenc
  clk: tegra: Fix naming of MISC registers
  clk: tegra: Remove improper flags for lock_enable
  clk: tegra: Fix divider on VI_I2C
2016-02-08 14:01:10 -08:00
Stephen Boyd
0e954fea5b clk: tegra: Fixes for v4.5-rc3
This set contains a bunch of miscellaneous fixes that have accumulated
 over the past couple of weeks, primarily for the Tegra210 support added
 in v4.5-rc1.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJWs45sAAoJEN0jrNd/PrOh89MP/j/n0UNn0pr7WVXwRHfE71nR
 g+uRejyhXC+/6aVUsGSeHsDLhP/7buI37LhmELRiiH9vZDHm40qLsf15ovZ152Qw
 E3QLDs1ET82uAnNEEQcSu8DtC3IbzioMlUg56Nc5Mcd0nRqlL3cXP2Uswrypxmxa
 V0T85HvE/yFnx2TQJru77xmoexDGHxgEMa6owMUViGiuFjIGi509TGTg4EONJhhA
 R1Oszjx8eGGLDY5d75tbxYtotD1tcfldRQKyLAoxcRMjvk8/EPMYR6sNwhqvecX/
 7LMIoCraOVFhbsyzX6ldPDoT/dkwF3pKGPv9N1DXEbq2NShzCrlvjR9rKJ532DBR
 23Z+uSxL6OmWmqmaIMGY25zocDz323iEQUserMisJlE7R0xF0mJg/wAd4dclnRq9
 dTI4w4oajFmTSoFg0Lm4RaIwhH2MwaIu2eHjtFHdB00++8t5Le8zpODnzgzBSpB/
 R+24W+uMse+FPZj71s3ndC8GUoTf3IneIR5ma4w9LrU8Q6OcH+5IP+N884+dvMpa
 AsFclgh3rrQVuvSolblq3/E4uc9aXrJo2sosRqUVxoPe5mxtzwPj5XCb7y5mgV1D
 6OZPfZ/Coa3tPfufCngSyze5x26JtInyYnIp0KYgoiU5Y3kWg8ovOYf8NtJT6JJe
 4C7pSWDtadBdA1AhaHNT
 =zdPz
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes

Pull tegra fixes from Thierry Reding:

clk: tegra: Fixes for v4.5-rc3

This set contains a bunch of miscellaneous fixes that have accumulated
over the past couple of weeks, primarily for the Tegra210 support added
in v4.5-rc1.

* tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: super: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warning for pll_m
  clk: tegra: Use definition for pll_u override bit
  clk: tegra: Fix warning caused by pll_u failing to lock
  clk: tegra: Fix clock sources for Tegra210 EMC
  clk: tegra: Add the APB2APE audio clock on Tegra210
  clk: tegra: Add missing of_node_put()
  clk: tegra: Fix PLLE SS coefficients
  clk: tegra: Fix typos around clearing PLLE bits during enable
  clk: tegra: Do not disable PLLE when under hardware control
  clk: tegra: Fix pllx dyn step calculation
  clk: tegra: pll: Fix potential sleeping-while-atomic
  clk: tegra: Fix the misnaming of nvenc from msenc
  clk: tegra: Fix naming of MISC registers
  clk: tegra: Remove improper flags for lock_enable
  clk: tegra: Fix divider on VI_I2C
2016-02-08 13:51:04 -08:00
Yoshihiro Shimoda
7826c61138 clk: shmobile: r8a7795: Add USB-DMAC clocks
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-08 16:26:54 +01:00
Dirk Behme
90c073e539 clk: shmobile: r8a7795: Add SD divider support
This patch adds SD[0..3] clock divider support for R-Car Gen3 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-08 16:26:04 +01:00
Stephen Boyd
47b0eeb3dc clk: Deprecate CLK_IS_ROOT
We don't use CLK_IS_ROOT but in a few places in the common clk
framework core. Let's replace those checks with a check for the
number of parents a clk has instead of the flag, freeing up one
flag for something else. We don't remove the flag yet so that
things keep building, but we'll remove it once all drivers have
removed their flag usage.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-06 23:38:26 -08:00
Stephen Boyd
14b04f28a0 clk: gpio: Make into a platform driver
clk_get() for DT based clks already returns EPROBE_DEFER when the
OF clk provider is not present. So having all this code in the
clk provider to return EPROBE_DEFER when the gpio isn't ready yet
can be replaced with a platform driver that doesn't add the clk
provider until the gpio can be requested. Get rid of the
OF_CLK_DECLARE and convert this to a platform driver instead.

Tested-by: Jyri Sarha <jsarha@ti.com>
Cc: Sergej Sawazki <ce3a@gmx.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jon Nettleton <jon@solid-run.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-06 23:38:20 -08:00
Heiko Stuebner
36714529f8 clk: rockchip: convert manually created factor clocks to the new type
Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.

This also unifies the artificial separation of the hclk_vcodec etc clocks
again.

We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 15:54:20 +01:00
Heiko Stuebner
29a30c269a clk: rockchip: add a factor clock type
Add a clock type for fixed factor clocks. This allows us to define fixed
factor clocks where they appear in the clock hierarchy instead of in the
init function.

The additional factor_gate type, finally allows us to model some last
parts of the clock tree correctly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 15:49:09 +01:00
Heiko Stuebner
aebe3ad801 clk: rockchip: fix parent of hclk_vcodec on rk3036
hclk_vcodec is a child of aclk_vcodec with the fixed factor clock
hclk_vcodec_pre in between and not a child of hclk_disp_pre.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 13:53:15 +01:00
Andrzej Hajda
02ed910cb4 clk/samsung: exynos5433: add pclk_decon clock
This undocumented gate clock is used by DECON IP.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-03 11:03:50 +01:00
Andrzej Hajda
68b2206a57 clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
HDMI driver must re-parent respective muxes during HDMI-PHY on/off
to HDMI-PHY output clocks. To reference those clocks their
definitions should be added.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-03 11:03:34 +01:00
Shawn Lin
2467b6745e clk: rockchip: free memory in error cases when registering clock branches
Add free memeory if rockchip_clk_register_branch fails.

Fixes: a245fecbb8 ("clk: rockchip: add basic infrastructure...")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-02 22:09:50 +01:00
Insu Yun
4106a3d9eb clk: unlock for handling unregistered clock
If clock is already unregistered, it returns with holding lock.
It needs to be unlocked.

Signed-off-by: Insu Yun <wuninsu@gmail.com>
[sboyd@codeaurora.org: Use goto instead]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:54:07 -08:00
Arnd Bergmann
7001ec560a clk: vt8500: don't return possibly uninitialized data
The clk-vt8500.c driver would previously enter an endless loop
when invalid settings got requested, this was now fixed. However,
the driver will now return uninitialized data for a subset of those
cases instead, as the gcc correctly warns:

clk/clk-vt8500.c: In function 'wm8650_find_pll_bits':
clk/clk-vt8500.c:423:12: error: 'best_div2' may be used uninitialized in this function [-Werror=maybe-uninitialized]
  *divisor2 = best_div2;
            ^
clk/clk-vt8500.c:422:12: error: 'best_div1' may be used uninitialized in this function [-Werror=maybe-uninitialized]
  *divisor1 = best_div1;
            ^
clk/clk-vt8500.c:421:14: error: 'best_mul' may be used uninitialized in this function [-Werror=maybe-uninitialized]
  *multiplier = best_mul;

This reworks the error handling in the driver so we now return
-EINVAL from clk_round_rate() and clk_set_rate() when we get
impossible inputs.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 090341b0a9 ("clk: vt8500: fix sign of possible PLL values")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:17 -08:00
Masahiro Yamada
e8f0e68ec0 clk: slightly optimize clk_core_set_parent()
If clk_fetch_parent_index() fails, p_rate is unused.  Move the
assignment after the error checking.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:17 -08:00
Masahiro Yamada
470b5e2f97 clk: simplify clk_fetch_parent_index() function
The clk_core_get_parent_by_index can be used as a helper function
to simplify the implementation of clk_fetch_parent_index().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:16 -08:00
Masahiro Yamada
508f884a66 clk: make sure parent is not NULL in clk_fetch_parent_index()
If parent is given with NULL, clk_fetch_parent_index() could return
a positive index value.

Currently, parent is checked by the callers of this function, but
it would be safer to do it in this function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:15 -08:00
Masahiro Yamada
0e8f6e499e clk: walk the orphan clock list more simply
This loop can be much simpler. If a new parent is available for
orphan clocks, __clk_init_parent(orphan) can detect it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:14 -08:00
Masahiro Yamada
858d588156 clk: avoid circular clock topology
Currently, clk_register() never checks a circular parent looping,
but clock providers could register such an insane clock topology.
For example, "clk_a" could have "clk_b" as a parent, and vice versa.
In this case, clk_core_reparent() creates a circular parent list
and __clk_recalc_accuracies() calls itself recursively forever.

The core infrastructure should be kind enough to bail out, showing
an appropriate error message in such a case.  This helps to easily
find a bug in clock providers.  (uh, I made such a silly mistake
when I was implementing my clock providers first.  I was upset
because the kernel did not respond, without any error message.)

This commit adds a new helper function, __clk_is_ancestor().  It
returns true if the second argument is a possible ancestor of the
first one.  If a clock core is a possible ancestor of itself, it
would make a loop when it were registered.  That should be detected
as an error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:13 -08:00
Masahiro Yamada
5146e0b059 clk: simplify __clk_init_parent()
The translation from the index into clk_core is done by
clk_core_get_parent_by_index().  The if-block for num_parents == 1
case is duplicating the code in the clk_core_get_parent_by_index().

Drop the "if (num_parents == 1)" from the special case.  Instead,
set the index to zero if .get_parent() is missing.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:10 -08:00
Masahiro Yamada
3c8e77dd20 clk: move checking .get_parent to __clk_core_init()
The .get_parent is mandatory for multi-parent clocks.  Move the check
to __clk_core_init(), like other callback checkings.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
[sboyd@codeaurora.org: Squashed in error path handling, fix typos
in commit message]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:52:06 -08:00
Andre Przywara
d221b7a878 clk: sunxi: improve error reporting for the mux clock
clk_register_mux returns a pointer wrapped error value in case of
failure, so a simple NULL check is not sufficient to catch errors.
Fix that and elaborate on the failure reason on the way. The whole
function does not return any error value, so silently failing may
leave users scratching their heads because the kernel does not
provide any clues on what's wrong.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 19:02:00 +01:00
Arnd Bergmann
14b5a4bf7a clk: sunxi: don't mark sun6i_ar100_data __initconst
The clk-sun6i-ar100 clk driver is a platform driver that may use
deferred probing, so its probe function must not access
__init symbols. Kbuild warns about this:

WARNING: drivers/clk/sunxi/built-in.o(.text+0x15f0): Section mismatch in reference from the function sun6i_a31_ar100_clk_probe() to the (unknown reference) .init.rodata:(unknown)
The function sun6i_a31_ar100_clk_probe() references
the (unknown reference) __initconst (unknown).
This is often because sun6i_a31_ar100_clk_probe lacks a __initconst
annotation or the annotation of (unknown) is wrong.

Removing the __initconst annotation avoids the warning and makes
deferred probing work.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 3ca2377b6f ("clk: sunxi: rewrite sun6i-ar100 using factors clk")
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 18:33:25 +01:00
Jon Hunter
5a1d5eff3e clk: tegra: super: Fix sparse warnings for functions not declared as static
Sparse reports the following warnings for structures and functions that
should be declared static:

drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol
 'tegra_super_gen_info_gen4' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol
 'tegra_super_gen_info_gen5' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol
 'tegra_super_clk_init' was not declared. Should it be static?

Fix this by making the above static.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:34 +01:00
Jon Hunter
fd360e2084 clk: tegra: Fix sparse warnings for functions not declared as static
Sparse reports the following warnings for functions in clk-tegra210.c
that should be declared as static:

drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol
 'tegra210_pllcx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol
 '_pllc_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol
 '_pllc2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol
 '_pllc3_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol
 '_plla1_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol
 'tegra210_plla_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol
 'tegra210_plld_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol
 'tegra210_plld2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol
 'tegra210_plldp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol
 'tegra210_pllc4_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol
 'tegra210_pllre_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol
 'tegra210_pllx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol
 'tegra210_pllmb_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol
 'tegra210_pllp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol
 'tegra210_pllu_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol
 'tegra210_clk_adjust_vco_min' was not declared. Should it be static?

Fix this by declaring the above as static.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:33 +01:00
Jon Hunter
d9e657919a clk: tegra: Fix sparse warning for pll_m
Sparse generates the following warning for the pll_m params structure:

drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry
 defined twice
drivers/clk/tegra/clk-tegra210.c:1570:10:   also defined here

Fix this by correcting the index for the MISC1 register.

Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks")

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:32 +01:00
Jon Hunter
2d5b6cf84a clk: tegra: Use definition for pll_u override bit
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
the code directly uses the bit number. Therefore, use the definition,
PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:31 +01:00
Jon Hunter
0649c3232b clk: tegra: Fix warning caused by pll_u failing to lock
If the pll_u is not configured by the bootloader, then on kernel boot the
following warning is seen:

 clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
 tegra_init_from_table: Failed to enable pll_u_out1
 ------------[ cut here ]------------
 WARNING: at drivers/clk/tegra/clk.c:269
 Modules linked in:

 CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1
 Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
 task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000
 PC is at tegra_init_from_table+0x140/0x164
 LR is at tegra_init_from_table+0x140/0x164
 pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045
 sp : ffffffc0bc0abd50
 x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8
 x27: ffffffc000a06000 x26: ffffffc0bc019780
 x25: ffffffc00086a708 x24: ffffffc00086a790
 x23: ffffffc0006d7188 x22: ffffffc0bc010000
 x21: 000000000000016e x20: ffffffc0bc00d100
 x19: ffffffc000944178 x18: 0000000000000007
 x17: 000000000000000e x16: 0000000000000001
 x15: 0000000000000007 x14: 000000000000000e
 x13: 0000000000000013 x12: 000000000000001a
 x11: 000000000000004d x10: 0000000000000750
 x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0
 x7 : 0000000000000001 x6 : 0000000002d5f0f8
 x5 : 0000000000000000 x4 : 0000000000000000
 x3 : 0000000000000002 x2 : ffffffc000996724
 x1 : 0000000000000000 x0 : 0000000000000032

 ---[ end trace cbd20ae519e92ced ]---
 Call trace:
 [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
 [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
 [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
 [<ffffffc00008291c>] do_one_initcall+0x90/0x194
 [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
 [<ffffffc000636bb0>] kernel_init+0x10/0xdc
 [<ffffffc000085cd0>] ret_from_fork+0x10/0x40
 clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
 tegra_init_from_table: Failed to enable pll_u_out2
 ------------[ cut here ]------------

pll_u can be either controlled by software or hardware and this is
selected via the OVERRIDE bit in the pll_u base register. In the function
tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
hardware control of the pll. However, at the same time the pll_u clocks
are populated in the init_table for tegra210 and so software will try to
configure the pll_u if it is not already configured and hence, the above
warning is seen when the pll fails to lock. Remove the pll_u clocks from
the init_table so that software does not try to configure this pll on
boot.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:31 +01:00
Jon Hunter
4f8d444030 clk: tegra: Fix clock sources for Tegra210 EMC
The EMC clock sources for Tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If Tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.

Also add the additional pll_p clock source for the EMC.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:30 +01:00
Jon Hunter
2956994168 clk: tegra: Add the APB2APE audio clock on Tegra210
The APB2APE clock for the audio subsystem is required for powering up the
audio power domain and accessing the various modules in this subsystem on
Tegra210 devices. Add this clock for Tegra210.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:29 +01:00
Amitoj Kaur Chawla
047d6d8401 clk: tegra: Add missing of_node_put()
for_each_child_of_node() performs an of_node_get() on each iteration, so
before breaking out of the loop an of_node_put() is required.

Found using Coccinelle. The semantic patch used for this is as follows:

// <smpl>
@@
expression e;
local idexpression child;
@@

 for_each_child_of_node(root, child) {
   ... when != of_node_put(child)
       when != e = child
(
   return child;
|
+  of_node_put(child);
?  return ...;
)
   ...
 }
// </smpl>

Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:28 +01:00
Mark Kuo
442f53fb1b clk: tegra: Fix PLLE SS coefficients
The PLLE SS coefficients are different between Tegra210 and Tegra114.
Add SoC generation specific versions for Tegra114 and Tegra210 and use
them in their respective ->enable() callbacks.

Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:27 +01:00
Rhyland Klein
fd2963b071 clk: tegra: Fix typos around clearing PLLE bits during enable
While enabling PLLE on both Tegra114 and Tegra210, we should be clearing
PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting
them. This patch fixes both places where we incorrectly set instead of
cleared those bits.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:26 +01:00
Mark Kuo
f59b0168d3 clk: tegra: Do not disable PLLE when under hardware control
Software should not disable PLLE if PLLE is already put under hardware
control.

Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:25 +01:00
Rhyland Klein
3dad5c5fa1 clk: tegra: Fix pllx dyn step calculation
The logic for calculating the input rate used when figuring out the
proper dynamic steps for pllx was incorrect. It is supposed to be
calculated using parent_rate / m but it was just using the parent rate
directly, therefore using the wrong step values.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:24 +01:00
Andrew Bresticker
3eb61566a6 clk: tegra: pll: Fix potential sleeping-while-atomic
Since the ->enable() callback is called with a spinlock held, we cannot
call potentially blocking functions such as clk_get_rate() or
clk_get_parent(), so use the unlocked versions instead.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
[rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as
it isn't present upstream]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:23 +01:00
Rhyland Klein
736971bed2 clk: tegra: Fix the misnaming of nvenc from msenc
When adding the nvenc clock, it was partially named msenc in the code.
Since the msenc clock isn't present in Tegra210 and has been replaced by
the nvenc clock, its misleading to see it present. Therefore, properly
rename it.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:22 +01:00
Rhyland Klein
474f2ba268 clk: tegra: Fix naming of MISC registers
Some register for PLLM and PLLMB were named MISC0 but according to the
TRM, they have different names. Sync up the names to make it easier to
understand which register they are really referring to.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:20 +01:00
Vishnu Patekar
be338e4c58 clk: sunxi: add bus gates for A83T
A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 14:14:24 +01:00
Vishnu Patekar
2d6f5f0cf6 clk: sunxi: Add apb0 gates for A83T
APB0 is part of PRCM, and is compatible with earlier SOCs.
apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
This patch adds support for APB0 gates for A83T.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 14:11:46 +01:00
Masahiro Yamada
c44fccb5f7 clk: replace pr_warn() with pr_err() for fatal cases
These three cases let clk_register() fail.  They should be considered
as error messages.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:59 -08:00
Masahiro Yamada
3c436bf95a clk: drop the initial core->parents look-ups from __clk_core_init()
The core->parents is a cache to save expensive clock parent look-ups.
It will be filled as needed later.  We do not have to do it here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:54 -08:00
Masahiro Yamada
88cfbef2ac clk: simplify clk_core_get_parent_by_index()
Drop the "if (!core->parents)" case and refactor the function a bit
because core->parents is always allocated.  (Strictly speaking, it is
ZERO_SIZE_PTR if core->num_parents == 0, but such a case is omitted
by the if-conditional above.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:50 -08:00
Masahiro Yamada
176d11690b clk: move core->parents allocation to clk_register()
Currently, __clk_core_init() allows failure of the kcalloc() for the
core->parents.  So, clk_fetch_parent_index() and __clk_init_parent()
also try to allocate core->parents in case it has not been allocated
yet.  Scattering memory allocation here and there makes things
complicated.

Like other clk_core members, allocate core->parents in clk_register()
and let it fail in case of memory shortage.  If we cannot allocate
such a small piece of memory, the system is already insane.  There is
no point to postpone the memory allocation.

Also, allocate core->parents regardless of core->num_parents.  We want
it even if core->num_parents == 1 because clk_fetch_parent_index()
might be called against the clk_core with a single parent.

If core->num_parents == 0, core->parents is set to ZERO_SIZE_PTR. It
is harmless because no access happens to core->parents in such a case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:46 -08:00
Masahiro Yamada
3a6e845451 clk: change sizeof(struct clk *) to sizeof(*core->parents)
Now, the clock parent is not "struct clk *", but "struct clk_core *".
Of course, the size of a pointer is always same, but strictly speaking,
sizeof(struct clk *) should be sizeof(struct clk_core *) here.

This mismatch happened when we split the structure into struct clk
and struct clk_core.  For the potential possibility of future renaming,
sizeof(*core->parents) would be better.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:43 -08:00
Masahiro Yamada
027f942ce4 clk: remove unnecessary !core->parents conditional
This if-block has been here since the introduction of the common
clock framework.  Now no clock drivers are statically initialized.
core->parent is always NULL at this point.  Drop the redundant
check and the confusing comment.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:39 -08:00
Masahiro Yamada
be45ebf25f clk: rename __clk_init() into __clk_core_init()
Now this function takes clk_core as its argument.  __clk_core_init()
would be more suitable for the name of this function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:36 -08:00
Masahiro Yamada
d35c80c248 clk: change the argument of __clk_init() into pointer to clk_core
The argument clk_user is used only for the clk_user->core.  The rest
of this function only takes care of clk_core.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:32 -08:00
Masahiro Yamada
d9e743408e clk: remove unused first argument of __clk_init()
The "struct device *dev" is not used at all in this function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:28 -08:00
Arnd Bergmann
ea7743e271 ARM: pxa: define clock registers as __iomem
We should not dereference registers as pointers, so use readl/writel
instead for these registers.

The clock registers are accessed in multiple files, so we have to
change them all at once.

I stumbled over these registers while looking at something unrelated.
There are in fact other registers with the same problem, but I did
not try to address those at this point.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2016-02-01 21:43:41 +01:00
Stephen Boyd
4fcad2eaaa Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: rockchip: rk3368: fix some clock gates
  clk: rockchip: rk3036: rename emac ext source clock
  clk: rockchip: rk3036: fix the div offset for emac clock
  clk: rockchip: rk3036: fix uarts clock error
  clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-29 17:26:31 -08:00
Stephen Boyd
60c7e2d2ed Fixes for wrong register offsets in both rk3036 and rk3368.
Also rename the external input for the emac on rk3036, which
 should still be ok to do, as that binding was only introduced
 during this merge-window.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJWm9wLAAoJEPOmecmc0R2BfbUIAI7VaIzwhl4NkAO3x0P6emZT
 B/2C4RuPLW9oBf/YGxG+HsxD2iLpDjAlZADlGBXsrdkfjFuN0iULc8COrFJEGv0F
 HuFmxJz7IZCNS4BgXt+vk0yb43c1lLSMRSmTyWaY7izYUlQtcmDp/t7zTvwun9NM
 N2U44zXFsEnTtsb3gV65PivrMBT/sNK9MyOIylh3Xjs/v+fTCtsHwPVckFwiIiPx
 ER9ETDmeo/DEMtsutHTlCcujyvZXE3jsho0Ow7J/vuRJSbXkCW+Ki9CQZEvHGWXL
 7ZaST8A8LEBjvslCh9IkirZ7qi20wwk/md3zAeoE0+eimEOEIqWYF8qwsWHiJjU=
 =oT+p
 -----END PGP SIGNATURE-----

Merge tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

Pull rockchip fixes from Heiko Stuebner:

Fixes for wrong register offsets in both rk3036 and rk3368.
Also rename the external input for the emac on rk3036, which
should still be ok to do, as that binding was only introduced
during this merge-window.

* tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3368: fix some clock gates
  clk: rockchip: rk3036: rename emac ext source clock
  clk: rockchip: rk3036: fix the div offset for emac clock
  clk: rockchip: rk3036: fix uarts clock error
  clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-29 17:24:28 -08:00
Arnd Bergmann
9849fadfc0 clk: st: avoid uninitialized variable use
My previous patch fixed some warnings about printing a couple
of variables that are always uninitialized in quadfs_pll_fs660c32_set_rate(),
but I now got a warning that only shows up in some configurations (i.e.
without gcc -Os) about the params.ndiv being used uninitialized in the
error case:

drivers/clk/st/clkgen-fsyn.c: In function 'quadfs_pll_fs660c32_set_rate':
drivers/clk/st/clkgen-fsyn.c:584:75: warning: 'params.ndiv' may be used uninitialized in this function [-Wmaybe-uninitialized]
drivers/clk/st/clkgen-fsyn.c:574:16: note: 'params.ndiv' was declared here

This changes the error handling so we bail for invalid arguments rather
than continuing with uninitialized data.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 17:20:08 -08:00
Stephen Boyd
3d6f1c7212 clk: axi-clkgen: Remove sometimes impossible check
The size of unsigned long on 64-bit architectures is equal to the
size of u64, so this check is impossible there. This throws off
static checkers:

drivers/clk/clk-axi-clkgen.c:331 axi_clkgen_recalc_rate() warn:
impossible condition '(tmp > (~0)) => (0-u64max > u64max)'

Let's change this code to use min_t() instead so that we
get the same effect on architectures where sizeof(unsigned long)
doesn't equal sizeof(u64).

Cc: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 17:11:02 -08:00
Lars-Peter Clausen
62d1e7823d clk: axi-clkgen: Add multi-parent support
The clock generator has two clock inputs that can be used as the reference
clock. Add support for switching between them at runtime.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 17:06:14 -08:00
Lars-Peter Clausen
d95b599c03 clk: axi-clkgen: Remove version 1 support
Version 1 of the axi-clkgen core has not been used in new designs for over
two years now. This is a soft peripheral used in FPGAs and anybody who has
updated their kernel to the latest version will also have updated the
bitstream containing the clock generator. So it should be safe to drop
support for this now.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 17:04:07 -08:00
LABBE Corentin
8d0a69d735 clk: palmas: fix a possible NULL dereference
of_match_device could return NULL, and so cause a NULL pointer
dereference later.
Even if the probability of this case is very low, fixing it made
static analyzers happy.

Solving this with of_device_get_match_data made also code simplier.

Reported-by: coverity (CID 1324137)
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:57:09 -08:00
LABBE Corentin
93fffbbee1 clk: palmas: constify the palmas_clks_of_match_data structure
The palmas_clks_of_match_data structures are never modified.
This patch constify them.

Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:57:02 -08:00
Masahiro Yamada
653d1452b4 clk: optimize the divider walk in clk_divider_bestdiv()
Because _next_div() returns a valid divider, there is no need to
consult _is_valid_div() for the validity of the divider in every
iteration.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:45:32 -08:00
Andrzej Hajda
090341b0a9 clk: vt8500: fix sign of possible PLL values
With unsigned values underflow in loops can occur resulting in
theoretically infinite loops.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:43:58 -08:00
Masahiro Yamada
0b225e41e3 clk: add clk_unregister_fixed_rate()
Allow to unregister fixed rate clock.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:37:24 -08:00
Masahiro Yamada
cbf9591f66 clk: add clk_unregister_fixed_factor()
Allow to unregister fixed factor clock.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:35:49 -08:00
Srinivas Kandagatla
5540ac8da1 clk:gcc-msm8916: add missing mss_q6_bimc_axi clock
This clock is required for loading the qdsp firmware.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:35:22 -08:00
Stephen Boyd
4c9f242203 Merge branch 'clk-iproc' into clk-next
* clk-iproc:
  clk: iproc: Remove __init from header
  clk: iproc: Add support for Cygnus audio clocks
  Documentation: dt-bindings: Add DT bindings for Cygnus audio clock
2016-01-29 16:35:02 -08:00
Ray Jui
df416e565d clk: iproc: Remove __init from header
Remove __init macro from all function prototypes in clk-iproc.h

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:31:40 -08:00
Simran Rai
bcd8be1398 clk: iproc: Add support for Cygnus audio clocks
This patch adds support for Broadcom Cygnus audio PLL and leaf
clocks

Signed-off-by: Simran Rai <ssimran@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:31:38 -08:00
James Liao
b9e65ebc65 clk: Move vendor's Kconfig into CCF menu section
Move all vendor's Kconfig into CCF menu section to prevent
new drivers putting their Kconfig files in a wrong place.

Some Kconfigs need to be modified at the same time to avoid build
warnings.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
[sboyd@codeaurora.org: Fix typos in commit message]
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:30:06 -08:00
James Liao
4974259e18 clk: mediatek: Fix memory leak on clock init fail
mtk_clk_register_composite() may leak memory due to some error
handling path don't free all allocated memory. This patch
free all pointers that may allocate memory before error return.
And it's safe because kfree() can handle NULL pointers.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 13:02:51 -08:00
Geliang Tang
5fd9c05c84 clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.

Signed-off-by: Geliang Tang <geliangtang@163.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:59:50 -08:00
Stephen Boyd
f9285b54d6 clk: xgene: Remove return from void function
This function doesn't return anything because it's void. Drop the
return statement.

Cc: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:57:54 -08:00
Loc Ho
47727beb26 clk: xgene: Add SoC and PMD PLL clocks with v2 hardware
Add X-Gene SoC and PMD PLL clocks support for v2 hardware.
X-Gene SoC v2 and above use an slightly different SoC
and PMD PLL hardware logic.

Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:54:35 -08:00
Andi Shyti
dedbb2724d clk: s2mps11: remove redundant code
The definition of s2mps11_name is meant to resolve the name of a
given clock. Remove it because the clocks have the same name we
can get it directly from the s2mps11_clks_init structure.

While in the probe function the s2mps11_clks is used only to
iterate through the s2mps11_clks. The naming itself brings
confusion and the readability does not improve much.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:47:22 -08:00
Andi Shyti
36da4def1e clk: s2mps11: remove redundant static variables declaration
The clk_table and clk_data are declared static. The clk_table
contains the three clock data structures belonging to the s2mps11
driver. In the probe function it gets stored into clk_data.

Remove clk_table and refer directly to clk_data.

clk_data, itself, is also declared static. Declare locally it
and allocate it inside the probe function, as it is not used
anywhere else.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:47:02 -08:00
Andi Shyti
31ad0e2a9a clk: s2mps11: allocate only one structure for clock init
The driver allocates three structures, s2mpsxx_clk_init, for
three different clock types (s2mps11, s2mps13 and s2mps14). They
are quite similar but they differ only by the name. Only one of
these structures is used, while the others lie unused in the
memory.

The clock's name, though, is not such a meaningful information
and by assigning the same name to the initial data we can avoid
over allocation. The common name chosen will be s2mps11,
coherently with the device driver name, instead of the clock
device.

Therefore, remove the structures associated to s2mps13 and
s2mps14 and use only the one referred to s2mps11 for all kind of
clocks.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Suggested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:46:47 -08:00
Andi Shyti
26adc5fa27 clk: s2mps11: merge two for loops in one
The driver already loops once, there is no reason to loop again
for a different purpose. Merge the second loop into the first.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:46:06 -08:00
Heiko Stuebner
5035981979 clk-divider: make sure read-only dividers do not write to their register
Commit e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.

On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.

To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.

The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.

Fixes: e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:44:37 -08:00
Marc Gonzalez
eac2d86d60 clk: tango4: rename ARCH_TANGOX to ARCH_TANGO
Requested by arm-soc maintainer Kevin Hilman in v9 review.
http://article.gmane.org/gmane.linux.ports.arm.kernel/456331

Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:08:02 -08:00
Axel Lin
d22eb66b3c clk: scpi: Fix checking return value of platform_device_register_simple()
platform_device_register_simple() returns ERR_PTR on error.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:07:59 -08:00
Stephen Boyd
1ce133ec89 clk: mvebu: Mark ioremapped memory as __iomem
Silence the following sparse warning

drivers/clk/mvebu/dove-divider.c:252:14: warning: incorrect type in assignment (different address spaces)
drivers/clk/mvebu/dove-divider.c:252:14:    expected void *base
drivers/clk/mvebu/dove-divider.c:252:14:    got void [noderef] <asn:2>*
drivers/clk/mvebu/dove-divider.c:256:13: warning: incorrect type in argument 2 (different address spaces)
drivers/clk/mvebu/dove-divider.c:256:13:    expected void [noderef] <asn:2>*base
drivers/clk/mvebu/dove-divider.c:256:13:    got void *base
drivers/clk/mvebu/dove-divider.c:257:25: warning: incorrect type in argument 1 (different address spaces)
drivers/clk/mvebu/dove-divider.c:257:25:    expected void volatile [noderef] <asn:2>*iomem_cookie
drivers/clk/mvebu/dove-divider.c:257:25:    got void *base

Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:06:47 -08:00
Chen-Yu Tsai
8f2bf2ad96 clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very
complicated clocks, but is not really needed here.

Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux
+ divider. This makes the code easier to understand.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:29 +01:00
Chen-Yu Tsai
3ca2377b6f clk: sunxi: rewrite sun6i-ar100 using factors clk
sun6i's AR100 clock is a classic factors clk case:

AR100 = ((parent mux) >> p) / (m + 1)

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:28 +01:00
Chen-Yu Tsai
a78bb35552 clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc
The factors clk implementation has been extended to support custom
recalc callbacks to support clocks that use one factor for certain
parents only, like a pre-divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:28 +01:00
Chen-Yu Tsai
50d6ea47ba clk: sunxi: factors: Drop round_rate from clk ops
The common clock framework requires either determine_rate or round_rate
to be implemented. We use determine_rate so we can pass the parent index
to the get_factors callback. This cannot be done easily with round_rate,
so just drop it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:27 +01:00
Chen-Yu Tsai
435b7be1d8 clk: sunxi: factors: Support custom formulas
Some clocks cannot be modelled using the standard factors clk formula,
such as clocks with special pre-dividers on one parent, or clocks
with all power-of-two dividers.

Add support for a custom .recalc callback for factors clk. Also pass
the current parent index to the .get_factor and .recalc callbacks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:27 +01:00
Alexander Kochetkov
89aa027e60 clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
Allow sclk_i2s0 and i2s0_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_i2s0

Tested on radxarock-lite.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-29 10:18:49 +01:00
Shawn Lin
bb07698fc8 clk: rockchip: fix wrong mmc phase shift for rk3228
mmc sample shift is 0 for rk3228 refer to user manaul.
So it's broken if we enable mmc tuning for rk3228.

Fixes: 307a2e9ac ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-28 18:02:26 +01:00
Chen-Yu Tsai
cfa6368860 clk: sunxi: factors: Consolidate get_factors parameters into a struct
The .get_factors callback of factors_clk has 6 parameters. To extend
factors_clk in any way that requires adding parameters to .get_factors
would make that list even longer, not to mention changing all the
function declarations.

Do this once now and consolidate all the parameters into a struct.
Also drop the space before function pointer arguments, since checkpatch
complains.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27 18:57:37 +01:00
Chen-Yu Tsai
4cbeaebb8a clk: sunxi: factors: Add unregister function
sunxi's factors clk did not have an unregister function. This means
multiple structs were leaked whenever a factors clk was unregistered.

Add an unregister function for it. Also keep pointers to the mux and
gate structs so they can be freed.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27 18:57:31 +01:00
Chen-Yu Tsai
78ca95c769 clk: sunxi: factors: Add clk cleanup in sunxi_factors_register() error path
sunxi_factors_register() does not check for failures or cleanup after
clk_register_composite() or other clk-related calls.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27 18:56:42 +01:00
Chen-Yu Tsai
b3e919e03c clk: sunxi: factors: Make struct clk_factors_config table const
struct clk_factors_config contains shifts/widths for the factors of
the factors clk. This is used to read out the factors from the register
value. In no case is it written to, so make it const.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27 16:50:38 +01:00
Alexander Kochetkov
e8b63288b3 clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks
hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.

Fixes: 78eaf6095c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Cc: stable@vger.kernel.org # 4.1.x-
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26 21:09:51 +01:00
Paweł Jarosz
2c41b5a775 clk: rockchip: add tsadc clock on rk3066
Set clock id for sclk_tsadc gating clock of tsadc in rk3066

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26 01:08:02 +01:00
Heiko Stuebner
219a5859c8 clk: rockchip: fix usbphy-related clocks
The otgphy clocks really only drive the phy blocks. These in turn
contain plls that then generate the 480m clocks the clock controller
uses to supply some other clocks like uart0, gpu or the video-codec.

So fix this structure to actually respect that hirarchy and removed
that usb480m fixed-rate clock working as a placeholder till now, as
this wouldn't even work if the supplying phy gets turned off while
its pll-output gets used elsewhere.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
2016-01-25 15:00:03 +01:00
Rhyland Klein
14050118af clk: tegra: Remove improper flags for lock_enable
Most PLL's don't actually have LOCK_ENABLE bits. However, most PLL's
also had that flag set, which meant that the clk code was trying to
enable locks, and inadvertantly flipping bits in other fields.

For PLLM, ensure the correct register is used for the misc_register.
PLL_MISC0 contains the EN_LCKDET bit which should be used for enabling
the lock, and PLLM_MISC1 shouldn't be used at all.

Lastly, remove some of the settings which would point to the EN_LCKDET
bits for some PLLs. There is no need to enable the locks, and that is
done as part of the set_defaults logic already.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-01-25 13:56:30 +01:00
Rhyland Klein
21e4903246 clk: tegra: Fix divider on VI_I2C
VI-I2C has 16 bits available for its divider. Switch the divider width
to 16 instead of 8 so correct rates can be set.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-01-25 13:27:51 +01:00
zhangqing
e8099067de clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2ch
I2S_2CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25 11:06:54 +01:00
zhangqing
0bbe62eb92 clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch
SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25 11:04:51 +01:00
zhangqing
d566ebc3c0 clk: rockchip: rk3368: fix edp_24m parent
The edp_24m parent select bit define is:
1'b0:xin24m
1'b1:1'b0(dummy)
so adapt the parent sel bit to the currect one.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25 11:03:45 +01:00
Yoshihiro Shimoda
b7c9b91db2 clk: shmobile: r8a7795: Add USB3.0 clocks
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-01-25 10:40:14 +01:00
Chen-Yu Tsai
63d8c7b9c3 clk: sunxi: usb: Sort clk providers by chip family and name
The latest addition of H3 USB clocks placed them at the bottom. Move it
before A80 (sun9i), so they are sorted by SoC family then name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-25 10:26:03 +01:00
Stephen Boyd
6f31ef2c5c clk: sunxi: Drop clk.h include
This file is a clock provider, not a clk consumer. Drop the clk.h
include.

Cc: Jens Kuske <jenskuske@gmail.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-24 23:58:48 +01:00
Heiko Stuebner
fd0c0740fa clk: rockchip: rk3368: fix hdmi_cec gate-register
Fix a typo making the sclk_hdmi_cec access a wrong register to handle
its gate.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
2016-01-24 23:29:16 +01:00
Heiko Stuebner
0f28d98463 clk: rockchip: rk3368: fix parents of video encoder/decoder
The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
2016-01-24 23:29:16 +01:00
Heiko Stuebner
c6d5fe2ca8 clk: rockchip: rk3368: fix cpuclk core dividers
Similar to commit 9880d4277f ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.

And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
2016-01-24 23:29:16 +01:00
Heiko Stuebner
535ebd428a clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster
Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
2016-01-24 23:29:16 +01:00
Yakir Yang
ee16bbd289 clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for hclk_vio_bus
HCLK_VIO_BUS is the noc bus controller clock for display module,
due to it shouldn't belong to any driver, but we need it enabled,
so just mark it as the CLK_IGNORE_UNUSED flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-24 23:29:16 +01:00
Linus Torvalds
6d1c244803 ARM: DT updates for v4.5
As usual, the bulk of this release is again DT file contents.
 
 There's a huge number of changes here, and it's challenging to give a crisp
 overview of just what is in here. To start with:
 
 New boards:
 
 - TI-based DM3730 from LogicPD (Torpedo)
 - Cosmic+ M4 (nommu) initial support (Freescale Vybrid)
 - Raspberry Pi 2 DT files
 - Watchdog on Meson8b
 - Veyron-mickey (ASUS Chromebit) DTS
 - Rockchip rk3228 SoC and eval board
 - Sigma Designs Tango4
 
 Improvements:
 
 - Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files
 - Misc new devices for Rockchip rk3036 and rk3288
 - Allwinner updates for misc SoCs and systems
 
 ... and a _large_ number of other changes across the field. Devices
 added to SoC DTSI and board DTS files for a number of SoC vendors, new
 product boards on already-supported SoCs, cleanups and refactorings of
 existing DTS/DTSI files and a bunch of other changes.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWnr6fAAoJEIwa5zzehBx3p+gP+wYLUqXjCYgyu6oJPxJbWghj
 gPc4QJmhVlAWTqvE7Ut7RumWzGa7nUEH2QF9tiCLbDAw8727HJXhRHknFwaCsX45
 BsvFQaKY99ClfUhoSI9GRa8e2jEArjzEPqkynHW/8FM20qWaj/Z8DDfixG75gR8u
 onrMw6kprNGwmyQwqu5zLDXhUBCQIs1xRRSabUjV1P5420dbBaGgtmQrdj7k+JDt
 wo9SKiG6d9CSYil3r7BC+0JwzbKNBxRGs2vv1BJOfbZ3Lj+uC0vj1AxoF/p7dOHy
 ohuvt7UwwtoUzzFMcMUo7E8qxl9u6bbnPDlUoRF7DVVi5SQoeZd8BOZXOdLRN2OQ
 qtgsmziDxtvh7Ydj6i89D69x7+GurAFcP8Aturprc5Zd5lO70PAYBD379IhIZ8y1
 MVJltIEeuUZo7BaVBCHWQY9jJRtI3bAU6JdFPrFROsuo810IYd72Wbb1ZCfF7SV7
 nBRvV7e71VQxb48c3p8Et5FntHuXfUlhkMrQ7Cb+2ugB/diGgZB9NfrZbP3Azv7f
 A5Ey9tNHaOCUxzYDCw80jTa7OwVWNJf2kOT1yikASk3vODKLv4E5YQ2DULnObWG7
 iRmLYuuGka4sMs0ZjpV3kaqs+8rWu08x2rEr5X0wfU+DalIzUWA2oDKSgPLJoacV
 gXKP039CIxQAiottcppA
 =XDLa
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "As usual, the bulk of this release is again DT file contents.

  There's a huge number of changes here, and it's challenging to give a
  crisp overview of just what is in here.  To start with:

  New boards:

   - TI-based DM3730 from LogicPD (Torpedo)
   - Cosmic+ M4 (nommu) initial support (Freescale Vybrid)
   - Raspberry Pi 2 DT files
   - Watchdog on Meson8b
   - Veyron-mickey (ASUS Chromebit) DTS
   - Rockchip rk3228 SoC and eval board
   - Sigma Designs Tango4

  Improvements:

   - Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files
   - Misc new devices for Rockchip rk3036 and rk3288
   - Allwinner updates for misc SoCs and systems

  ... and a _large_ number of other changes across the field.  Devices
  added to SoC DTSI and board DTS files for a number of SoC vendors, new
  product boards on already-supported SoCs, cleanups and refactorings of
  existing DTS/DTSI files and a bunch of other changes"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (469 commits)
  ARM: dts: compulab: add new board description
  ARM: versatile: add the syscon LEDs to the DT
  dts: vt8500: Fix errors in SDHC node for WM8505
  ARM: dts: imx6q: clean up unused ipu2grp
  ARM: dts: silk: Add compatible property to "partitions" node
  ARM: dts: gose: Add compatible property to "partitions" node
  ARM: dts: porter: Add compatible property to "partitions" node
  ARM: dts: koelsch: Add compatible property to "partitions" node
  ARM: dts: lager: Add compatible property to "partitions" node
  ARM: dts: bockw: Add compatible property to "partitions" node
  ARM: dts: meson8b: Add watchdog node
  Documentation: watchdog: Add new bindings for meson8b
  ARM: meson: Add status LED for Odroid-C1
  ARM: dts: uniphier: fix a typo in comment block
  ARM: bcm2835: Add the auxiliary clocks to the device tree.
  ARM: bcm2835: Add devicetree for bcm2836 and Raspberry Pi 2 B
  ARM: bcm2835: Move the CPU/peripheral include out of common RPi DT.
  ARM: bcm2835: Split the DT for peripherals from the DT for the CPU
  ARM: realview: set up cache correctly on the PB11MPCore
  ARM: dts: Unify G2D device node with other devices on exynos4
  ...
2016-01-20 18:16:29 -08:00
Linus Torvalds
6b5a12dbca ARM: SoC multiplatform code changes for v4.5
This branch is the culmination of 5 years of effort to bring the ARMv6
 and ARMv7 platforms together such that they can all be enabled and
 boot the same kernel. It has been a tremendous amount of cleanup and
 refactoring by a huge number of people, and creation of several new
 (and major) subsystems to better abstract out all the platform details
 in an appropriate manner.
 
 The bulk of this branch is a large patchset from Arnd that brings several
 of the more minor and older platforms we have closer to multiplatform
 support.  Among these are MMP, S3C64xx, Orion5x, mv78xx0 and realview
 Much of this is moving around header files from old mach directories,
 but there are also some cleanup patches of debug_ll (lowlevel debug
 per-platform options) and other parts.
 
 Linus Walleij also has some patchs to clean up the older ARM Realview
 platforms by finally introducing DT support, and Rob Herring has some
 for ARM Versatile which is now DT-only. Both of these platforms are
 now multiplatform.
 
 Finally, a couple of patches from Russell for Dove PMU, and a fix from
 Valentin Rothberg for Exynos ADC, which were rebased on top of the
 series to avoid conflicts.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIUAwUAVqAGcmCrR//JCVInAQLDog/4x9F0PHGmZhexGfFOpi2Od63Jjx55izRU
 zRXqRjjFjambOrZuOx8lEGDy/qzqKbsDU8D1P4IUugkDr2bLSXv+NTLZL1kNBIdm
 YOlJhw/BmzLYqauOHmBzGhtv1FDUk3rqbgTsP5tTWj5LpSkwjmqui3HBZpi+f3Rr
 YOn+NeQSARiw+51D0b106a9RFshQXRGgn5m3xFjLWhJqshb2z2Ew5cogX/zdwrrM
 ss1BFomxsvgk6S+snN6v7cEX2iXe3r89qNR5jEW5BgNpQGFsAUeXPr9zzH07L/Qq
 O7XLw9jt5MX/X5372zVHPb57WoflLbF9cFaaDUZV3eTqt3lC67BTxOtYIdC2i90k
 E5GYlsy88CRwT2EO+ok/6UTryph+hVv7JqHfbKfnISrbraMCK36DtDTpBIpZ9uYF
 rRB7ncJZUWBcyoe+qvitSl+2KV54iB1ez2RXsketxM98dDZsfB2M2ImFou1F/Pgg
 ALvpifPubi/uDe7xNUsSuaT6/3jAomBuNsxnkYJ3NeiH/+duZbOYGkzK/LlcjZyc
 UrA0IpLfwIFsBNzwfpZPZ1lkEu8Y1YZZ+Hv9k65q1wMuBDgrFI5zUeYrPZi4pN9T
 Yo1xP9FstVLDouJrpGZo12VIIxR1UBeGqfRI/BZ58LEF3PRq/g2OVFsdQia5gZKr
 ddiJKSL1Vw==
 =z1AW
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC multiplatform code updates from Arnd Bergmann:
 "This branch is the culmination of 5 years of effort to bring the ARMv6
  and ARMv7 platforms together such that they can all be enabled and
  boot the same kernel.  It has been a tremendous amount of cleanup and
  refactoring by a huge number of people, and creation of several new
  (and major) subsystems to better abstract out all the platform details
  in an appropriate manner.

  The bulk of this branch is a large patchset from Arnd that brings
  several of the more minor and older platforms we have closer to
  multiplatform support.  Among these are MMP, S3C64xx, Orion5x, mv78xx0
  and realview Much of this is moving around header files from old mach
  directories, but there are also some cleanup patches of debug_ll
  (lowlevel debug per-platform options) and other parts.

  Linus Walleij also has some patchs to clean up the older ARM Realview
  platforms by finally introducing DT support, and Rob Herring has some
  for ARM Versatile which is now DT-only.  Both of these platforms are
  now multiplatform.

  Finally, a couple of patches from Russell for Dove PMU, and a fix from
  Valentin Rothberg for Exynos ADC, which were rebased on top of the
  series to avoid conflicts"

* tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits)
  ARM: realview: don't select SMP_ON_UP for UP builds
  ARM: s3c: simplify s3c_irqwake_{e,}intallow definition
  ARM: s3c64xx: fix pm-debug compilation
  iio: exynos-adc: fix irqf_oneshot.cocci warnings
  ARM: realview: build realview-dt SMP support only when used
  ARM: realview: select apropriate targets
  ARM: realview: clean up header files
  ARM: realview: make all header files local
  ARM: no longer make CPU targets visible separately
  ARM: integrator: use explicit core module options
  ARM: realview: enable multiplatform
  ARM: make default platform work for NOMMU
  ARM: debug-ll: move DEBUG_LL_UART_EFM32 to correct Kconfig location
  ARM: defconfig: use correct debug_ll settings
  ARM: versatile: convert to multi-platform
  ARM: versatile: merge mach code into a single file
  ARM: versatile: switch to DT only booting and remove legacy code
  ARM: versatile: add DT based PCI detection
  ARM: pxa: mark ezx structures as __maybe_unused
  ARM: pxa: mark raumfeld init functions as __maybe_unused
  ...
2016-01-20 18:03:56 -08:00
Linus Torvalds
0c582826a1 ARM: SoC non-urgent fixes for v4.5
As usual, we queue up a few fixes that don't seem urgent enough to go in
 through -rc.
 
  - MAINTAINERS updates to add a list for brcmstb and fix a typo
  - A handful of fixes for OMAP 81xx, a recently resurrected platform so these
    can't be considered real regressions and thus got queued.
  - A couple of other small fixes for scoop, sa1100 and davinci
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWnrNxAAoJEIwa5zzehBx3UwUQAJ0sX5ScDfOjUJFn8ridx4OY
 8mcOuR+ij/f2srNUlvBFV4h/j+vOauZ2zlNAjhQtgAJH0PV1pQyTkyLRGoDSwIzI
 BDl79IhlMKte3iZ460q3fsVovgF2OwmDVfx0WXC72X6oOv3xt+FPlE4B543Q/v/r
 WmL+PvLitaUA44/aK7QwlXg+IVQn2jDP64Uqkal5oVuQCjpeu4tcL99AbCLi4FiZ
 XA5wcofKCo/wDeRK0uLWgcrHklVF4QIcvOPRIqvPvFc8V6OldAb22hTOozNa5gSp
 QG3S9IFO4OHrcEH6M7XqLaTQv8KXEwzAqFlrciJUBX7rm0cUlzRKwctr1MmLsnKi
 UpbHAqUHTLeJaNjKQGEX+vVKBa8PjLN4E05AuSa6TOgDbNgxRu0XUDbLR/9/bgbL
 towtcUGTLBYc8itWx+0jhy4ABU0/kZiUbVOdWi5ex76BHI8lnXSvV8dD02iLHmfU
 yLskruj/RMubvZxdj/kb7f/Tqn0eyi9TUGS2lqGE3Twj2MUwUaZaPskMEYMQgSZf
 U3NWTPCDWvXsBnaO3yENBWUBGA54fy7YfB0gZc7W9Lg+vbnw6j+I4/GX1Eb2toA+
 EU9qn6nZ3kI6NAo/2snVsaGLFnAAnsslX6evnFea9mqPMEbrzd9Yg5rUMK7nfsvv
 5DpvnsMKnlL80YykQ4yC
 =W+es
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull non-urgent ARM SoC fixes from Olof Johansson:
 "As usual, we queue up a few fixes that don't seem urgent enough to go
  in through -rc.

   - MAINTAINERS updates to add a list for brcmstb and fix a typo
   - A handful of fixes for OMAP 81xx, a recently resurrected platform
     so these can't be considered real regressions and thus got queued.
   - A couple of other small fixes for scoop, sa1100 and davinci"

* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: OMAP2+: Fix randconfig build warning for dm814_pllss_data
  ARM: sa1100/simpad: Be sure to clamp return value
  ARM: scoop: Be sure to clamp return value
  ARM: davinci: fix a problematic usage of WARN()
  ARM: davinci: only select WT cache if cache is enabled
  ARM: OMAP2+: Remove useless check for legacy booting for dm814x
  ARM: OMAP2+: Enable GPIO for dm814x
  ARM: dts: Fix dm814x pinctrl address and mask
  ARM: dts: Fix dm8148 control modules ranges
  ARM: OMAP2+: Fix timer entries for dm814x
  ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting
  ARM: OMAP2+: Add DPPLS clock manager for dm814x
  clk: ti: Add few dm814x clock aliases
  ARM: dts: Fix dm814x entries for pllss and prcm
  MAINTAINERS: gpio-brcmstb: Remove stray '>'
  MAINTAINERS: brcmstb: Include Broadcom internal mailing-list
2016-01-20 17:44:16 -08:00
Linus Torvalds
e3de671dd6 asm-generic changes for 4.5
The asm-generic tree this time contains one series from Nicolas Pitre
 that makes the optimized do_div() implementation from the ARM
 architecture available to all architectures. This also adds stricter
 type checking for callers of do_div, which has uncovered a number
 of bugs in existing code, and fixes up the ones we have found.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIVAwUAVqARKWCrR//JCVInAQJrBhAAlwZL0IiVGFfDXWtvQGOm+yC5j4vdIhMf
 1scsvRbk3ln1xUk5+NM61NpxbQotro78K5HxFZFhaVGUTbbFXM9w2VZSyI8ZaGAJ
 Od6lBUUyLQmzlbHDJ3v/zrZn8Up7qZlRApmXcbUVDtssfnEfKk4xA2RG9JwIMS1c
 uZMvnD7N3P9vxDPl+CsYlB2osi6Yks3VQ1tXYe2z6siO+H67zHaF08+ls7fbsd3d
 oyKjZqlaQ02MIOr+AdR0h9iKyJJ6SXT0DQlsMyzB6aBWmeBCNLNALNIiukDk9Qc1
 VV3sF1MOS3LtfU2TeOx4Na7hcd2iC6WYLb271iApO2Ww7t16n+de3i6AipZxLUJ0
 08jiRlisTzUhXDobRSqI3mcQlxrB5UGfyblab2z/MqGGmIGJSPPRdTPRQUgi0ZKg
 jksSmsaPwOQp64FhTgECLJthlYX7h6ULjkvJ9h60gZHa4jhGZbGPeMwHPf1uSm95
 EvQE971Ssgm4jwhvxZ/kt1ruuZI/fxxG1Qfw+C25QkXZGKye2nB+icLWeMwz+FXG
 HLqkmaAjasf5MAV1GiK8U6zoC6bCOLU0Lea83hOwRPZ999v3Nym1giSatNv4/pB+
 QmkXRvFi93cdQ643l7xcUEDT2zpk4pogF3xREiBhyaXtqLlT7pPMKsBQOgdWvFuu
 Ou0ZbEAwIVo=
 =4psa
 -----END PGP SIGNATURE-----

Merge tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pull asm-generic updates from Arnd Bergmann:
 "The asm-generic tree this time contains one series from Nicolas Pitre
  that makes the optimized do_div() implementation from the ARM
  architecture available to all architectures.

  This also adds stricter type checking for callers of do_div, which has
  uncovered a number of bugs in existing code, and fixes up the ones we
  have found"

* tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
  ARM: asm/div64.h: adjust to generic codde
  __div64_32(): make it overridable at compile time
  __div64_const32(): abstract out the actual 128-bit cross product code
  do_div(): generic optimization for constant divisor on 32-bit machines
  div64.h: optimize do_div() for power-of-two constant divisors
  mtd/sm_ftl.c: fix wrong do_div() usage
  drm/mgag200/mgag200_mode.c: fix wrong do_div() usage
  hid-sensor-hub.c: fix wrong do_div() usage
  ti/fapll: fix wrong do_div() usage
  ti/clkt_dpll: fix wrong do_div() usage
  tegra/clk-divider: fix wrong do_div() usage
  imx/clk-pllv2: fix wrong do_div() usage
  imx/clk-pllv1: fix wrong do_div() usage
  nouveau/nvkm/subdev/clk/gk20a.c: fix wrong do_div() usage
2016-01-20 17:30:20 -08:00
Jianqun xu
8931f8e029 clk: rockchip: rk3368: fix some clock gates
Reference to the Rockchip RK3368 TRM v1.1, some clock
gates need to be updated.

Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Xing Zheng
3d667920bc clk: rockchip: rk3036: rename emac ext source clock
There is only support rmii in the RK3036, so we should use the correct
ext clock name as described in the TRM.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
[update dt-binding document as well]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Xing Zheng
c40519350e clk: rockchip: rk3036: fix the div offset for emac clock
Due to reference to old version TRM, there are incorrect emac clock node.
The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the
child div.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Xing Zheng
b29de2de50 clk: rockchip: rk3036: fix uarts clock error
Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Xing Zheng
99222c9e4d clk: rockchip: rk3036: fix the FLAGs for clock mux
The DFLAGS are used for the clock dividers, the CLKSEL_CON flags
of COMPOSITE_NODIV type should be MFLAGS.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16 16:01:21 +01:00
Vladimir Zapolskiy
3da834e3e5 clk: remove duplicated COMMON_CLK_NXP record from clk/Kconfig
Presumably the second COMMON_CLK_NXP config option in
drivers/clk/Kconfig appeared after a merge conflict resolution, remove
the wrong record of two.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-01-13 18:09:52 -08:00
Michael Turquette
b360ada3f1 clk: tegra: Changes for v4.5-rc1
This set of changes adds support for the Tegra210 SoC and contains a
 couple fixes and cleanups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJWcq0qAAoJEN0jrNd/PrOhxXIP/Rs/Iw27BVfk/ZYA+9SaYlNz
 vxqzGqWincnlaArLuhAnUHciAv5kl3HnHEuOyAgFevX/KrnmAb5JMXuw2FaSmzPc
 hjI5QqeieEHqp0wFSms/+abTiLX5t36bsY91QM8LfsdDOotrYGwEJcqDVEZkvMF2
 j3U4RuXEqt/C0r436lPcxf+flvy70K1cQkywsKupcS4YGl0QiQVeY80tHmIIyrkA
 2KLkxH5zgs/6xlcGblqzkFmrQntp5XJVgdlg1e2SZ5MOOme9fQCU0F3VueOX+WZH
 FL4C05eaXCaga398Z/UgJru1X8HWUKzrGBX6XXktxeTjt8ruKD8PEjX7SVPYMRI9
 Kzb3NE5qC0LEwe/BAX/4scZ6fZFyk+zfiC566YA3rcM1sg5mm4k8PCH3x2ktxXI1
 SZYmIrm+9hXXWfvXlKysaIsmGL0hlsRlu6m6g2OEYTUABDMBLnMsTbeC6Li4Gh0Q
 kXISNZpMhRaiB1hba3z2J/sVuMQcR33e86IaAX7WFY4ZRTNKfD0oB2zN5lZjPO6o
 U9ATB5ApPWn3t0JR88jaApPVELVb5q6ufra2zPesnS25CfS+zSXbskgnZe9UkPAs
 XVUprlmsNm+vZbZJpf3eNtW2IS0c0vCAYkafY3KjWcKVKvgKw5Zu8Kdo1TAJTHbP
 +xfWr3/iiwN5NNsYZbiH
 =/f1y
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-4.5-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

clk: tegra: Changes for v4.5-rc1

This set of changes adds support for the Tegra210 SoC and contains a
couple fixes and cleanups.
2016-01-04 16:16:45 -08:00
Russell King
7ed88aa2ef clk: fix clk-gpio.c with optional clock= DT property
When the clock DT property is not given, of_clk_get_parent_count()
returns -ENOENT, which then tries to allocate -2 x 4 bytes of memory,
which of course fails, causing the whole driver to fail to create
the clock.

This causes the SolidRun platforms to fail probing the SDHCI1 interface
which is connected to the WiFi.

Fix this by detecting errno codes, skipping the allocation, and fixing
of_clk_gpio_gate_delayed_register_get() to handle a NULL parent_names
array.

Fixes: 80eeb1f0f7 ("clk: add gpio controlled clock multiplexer")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-01-02 23:19:50 -08:00
Michael Turquette
49dea76aeb Merge branch 'clk-rockchip' into clk-next 2016-01-02 13:41:09 -08:00
Heiko Stübner
5b73840375 clk: rockchip: fix section mismatches with new child-clocks
To model the muxes downstream of fractional dividers we introduced the
child property, allowing to describe a direct child clock.
The first implementation seems to cause section warnings, as the core
clock-tree is marked as initdata while the data pointed to from the
child element is not.

While there may be some way to also set that missing property in the
inline notation I didn't find it, so to actually fix the issue for now
move the sub-definitions into separate declarations that can have
their own __initdata properties.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-01-02 13:40:29 -08:00
Brian Norris
0b2e78865d clk: gpio: handle error codes for of_clk_get_parent_count()
We might make bad memory allocations if we get (e.g.) -ENOSYS from
of_clk_get_parent_count().

Noticed by Coverity.

Fixes: f66541ba02 ("clk: gpio: Get parent clk names in of_gpio_clk_setup()")
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Jyri Sarha <jsarha@ti.com>
Cc: Sergej Sawazki <ce3a@gmx.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31 21:54:45 -08:00
Sudip Mukherjee
c76eb11c8f clk: gpio: fix memory leak
If we fail to allocate parent_name then we are returning but we missed
freeing data which has already been allocated.

Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31 21:31:58 -08:00
Michael Turquette
9e256c722f Merge branch 'clk-renesas' into clk-next 2015-12-31 15:17:39 -08:00
Ulrich Hecht
c1c5864d94 clk: shmobile: r8a7795: Add SATA0 clock
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31 15:15:30 -08:00
Arnd Bergmann
d731afa460 Samsung DeviceTree updates and improvements for 4.5
1. eMMC/SDIO minor fixes usage of bindings on Snow and Peach
    Chromebooks.
 2. Remove FIMD from Odroid XU3-family because on XU3 it cannot be used
    yet and on XU3-Lite and XU4 it is not supported.
 3. Remove deprecated since June 2013 samsung,exynos5-hdmi.
 4. Add support for Pseudo Random Generator on Exynos4 (Trats2 for now).
    This depends on new SSS clock.
 5. Add rotator nodes for Exynos4 and Exynos5.
 6. Switch DWC3_1 on Odroid XU3 and XU3-Lite to peripheral mode because
    now it cannot be used as OTG.
 7. Cleanup the G2D usage on Exynos4 and add it to a proper domain
    in case of Exynos4210.
 8. Put MDMA1 in proper domain on Exynos4210 as well.
 9. Minor cleanups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWgc9VAAoJEME3ZuaGi4PXv+QP/iegxXdOr6Ta0usArPqzzkg3
 G1r6gcK/izjtEmGVqQDZjAN8HH9NeEpQnmirAttH7saqLW3+2GxQJkyekgUNruBN
 KT9igUtZpUAYD9JWBc2Q9OX6NTFBBn1zOt4d1Ea16u7uHllvvJl4jI4j3GAa8a5+
 OBA1nHP0Vg3ODWXhck67V/WojmH5XyTSBDspMimjAc9YShjM3vRc4rIfkGWieVCW
 /Hvu+dRJl2DKxrrQ8rHRnOUImQqVLN4V/1lUChhhZrecpFFn+2znKMgzmIVZDKNk
 oCW/uAHDR/i9O7GcLRbgzSfDRSwm1zM7DQKsffJmjdun6+46A04R8gPoF94uKKAk
 THG0yIsAqPn8wqHGAzNEPQPlCQ1u8iMBesNyrzZ6UqXbTBWXW/z9ueWQFb2TOQ7c
 gkr1trbfAjOxeeZ+fbOX7zOy+ghDyphSf6NytH147RIAPtVotNfEzPUFda+k7KyU
 CXGiSPVHaKntFhrr25PDk7iHXbMFUfMiGFGzz3sHaYD1FKHMJN0Simp+H1uK1sgA
 I5HXwtzkORLaM2HMR5+vfJlptks9PO9oEOioVxZbe9/VLo1/Iuylf09h6xgzJ2W6
 jE0rRWogBD6mntcGd+HpBN/4p09IIfHC1KocrryltzIJKvebeaoDvcnZKfBy3Hzd
 GDaBtsyg+BNb6LZiRRS6
 =LMzD
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt-4.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Merge "Samsung DeviceTree updates and improvements for 4.5" from Krzysztof Kozlowski:

1. eMMC/SDIO minor fixes usage of bindings on Snow and Peach
   Chromebooks.
2. Remove FIMD from Odroid XU3-family because on XU3 it cannot be used
   yet and on XU3-Lite and XU4 it is not supported.
3. Remove deprecated since June 2013 samsung,exynos5-hdmi.
4. Add support for Pseudo Random Generator on Exynos4 (Trats2 for now).
   This depends on new SSS clock.
5. Add rotator nodes for Exynos4 and Exynos5.
6. Switch DWC3_1 on Odroid XU3 and XU3-Lite to peripheral mode because
   now it cannot be used as OTG.
7. Cleanup the G2D usage on Exynos4 and add it to a proper domain
   in case of Exynos4210.
8. Put MDMA1 in proper domain on Exynos4210 as well.
9. Minor cleanups.

* tag 'samsung-dt-4.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (21 commits)
  ARM: dts: Unify G2D device node with other devices on exynos4
  ARM: dts: Add power domain to G2D device on exynos4210
  ARM: dts: MDMA1 device belongs to LCD0 power domain on exynos4210
  ARM: dts: Remove unneeded GPIO include in exynos4412-odroidu3
  ARM: dts: exynos4210-universal_c210: Disable DMA for UARTs
  ARM: dts: Use peripheral mode for dwc3_1 on exynos5422-odroidxu3
  ARM: dts: Add rotator node on exynos5420
  ARM: dts: Add rotator node on exynos5250
  ARM: dts: Fix power domain for sysmmu-rotator device on exynos4
  ARM: dts: Add rotator nodes on exynos4
  ARM: dts: Enable PRNG module on exynos4412-trats2
  ARM: dts: Add PRNG module for exynos4
  dt-bindings: remove deprecated compatible string from exynos-hdmi
  ARM: dts: Remove fimd node from exynos5422-odroidxu3-common
  ARM: dts: Mark eMMC as non-removable in exynos5250-snow-common
  ARM: dts: Remove broken-cd from eMMC node in exynos5420-peach-pi
  ARM: dts: Remove broken-cd from eMMC node in exynos5800-peach-pi
  ARM: dts: Mark SDIO as non-removable in exynos5250-snow-common
  ARM: dts: Mark SDIO as non-removable in exynos5420-peach-pit
  ARM: dts: Mark SDIO as non-removable in exynos5800-peach-pi
  ...
2015-12-31 17:31:56 +01:00
Arnd Bergmann
d4e68fa37f Add minimal device tree support for dra62x also known j5eco. It is
related to dm814x, just the clocks are a bit different and it has a
 different set of integrated devices. And let's get some basic dm814x
 and dra62x devices working as many of the devices are like on am33xx::
 
 - pinctrl using the pinctrl defines as for am33xx
 
 - Updated EDMA bindings with support for using exma_xbar
 
 - MMC support for dm814x-evm, t410 and dra62x-j5eco-evm
 
 - USB support for dm814x-evm, t410 and dra62x-j5eco-evm
 
 This branch depends on an earlier omap-for-v4.5/81xx-fixes-signed
 branch that has dm814x dts fixes interlaced with SoC related fixes to
 keep things booting. The interlaced SoC and dts fixes were needed
 because of issues with the device tree defined clocks that just
 happened to work on bootloader timings for t410 earlier.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWeewGAAoJEBvUPslcq6Vz+5UQAJDZH9+kELrI1i1ymWg50q2+
 HdnswijaQVuX1ZZeyarytvMT00s6bkouaGTLYrPGlifuJuBAAZ3PewZ4FVgIkA4A
 V4QAl3+vZ0wU+TjwWLlODXwd20xAeGY5LmhLkaHheP8Dbnd1OLm2BxJlps+zK3WJ
 a9Wv0rcwJuJt9dBGdELDcj04SlHd6oOmy+bHeoUi0VBcb+ZJD8+WaWQB1qkvae46
 IitA74nDLY0Ejezf3lJ8Bu+I1NKv5tGg//SEJTZQfaSFxGoYbfcHkOKrBP8MAM8U
 IQZHxz0izeKaAyra7qrqiHox4GVJpKFVkvHrDlox9GDSUKxP0cRpahLEqjUF1VMm
 FYE2dh/JjWFhPaGMVIQIiVQNND6NZlycBc1fcEKuT+2tXjqALQ1qDZwb6S44q5/r
 1QL+pBIZVMl5YaTpt/yh7COhpMtKbofamzJkzUTVwx6ao/a1uK2G+K83ZB9wkPkw
 YUBL68oD8EN+fSnZMVlFQkwJGgmoMzaFuqLJMjV0RQWTmzHH43Nyg76muMCIiKwf
 Xu4ZdNUS7VkHYdjVJXQcXU4igLejj6Q/Qmvw1M+LxsyDH+I4WRgWgYB11T45f0Lf
 eafwSkAayq7dBzuXJ4kOuK5sR9LOYA7Le9XRvu9f8KOY2aKWoZiVB2KPCz7BaoNs
 BZH5tf0C7D5mXQz8sXik
 =W/MF
 -----END PGP SIGNATURE-----

Merge tag 'omap-for-v4.5/81xx-dts-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Pull "reworked dts changes for ti81xx devices and minimal
dra62x j5ec-evm support" from Tony Lindgren:

Add minimal device tree support for dra62x also known j5eco. It is
related to dm814x, just the clocks are a bit different and it has a
different set of integrated devices. And let's get some basic dm814x
and dra62x devices working as many of the devices are like on am33xx::

- pinctrl using the pinctrl defines as for am33xx

- Updated EDMA bindings with support for using exma_xbar

- MMC support for dm814x-evm, t410 and dra62x-j5eco-evm

- USB support for dm814x-evm, t410 and dra62x-j5eco-evm

This branch depends on an earlier omap-for-v4.5/81xx-fixes-signed
branch that has dm814x dts fixes interlaced with SoC related fixes to
keep things booting. The interlaced SoC and dts fixes were needed
because of issues with the device tree defined clocks that just
happened to work on bootloader timings for t410 earlier.

* tag 'omap-for-v4.5/81xx-dts-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
  ARM: dts: Add usb support for j5-eco evm
  ARM: dts: Add usb support for hp t410
  ARM: dts: Add usb support for dm814x-evm
  ARM: dts: Add usb support for dm814x and dra62x
  ARM: dts: Enable emmc on hp t410
  ARM: dts: Add mmc support for dra62x j5-eco evm
  ARM: dts: Add mmc support for dm8148-evm
  ARM: dts: Add mmc device entries for dm814x
  ARM: dts: Update edma bindings on dm814x to use edma_xbar
  ARM: dts: Add pinctrl macros for dm814x
  ARM: dts: Add minimal dra62x j5-eco evm support
  ARM: dts: Add basic support for dra62x j5-eco SoC
  ARM: OMAP2+: Remove useless check for legacy booting for dm814x
  ARM: OMAP2+: Enable GPIO for dm814x
  ARM: dts: Fix dm814x pinctrl address and mask
  ARM: dts: Fix dm8148 control modules ranges
  ARM: OMAP2+: Fix timer entries for dm814x
  ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting
  ARM: OMAP2+: Add DPPLS clock manager for dm814x
  clk: ti: Add few dm814x clock aliases
  ...
2015-12-31 16:25:22 +01:00
Michael Turquette
82d0f8bc4b Merge branch 'clk-bcm2835' into clk-next 2015-12-24 20:39:02 -08:00
Remi Pommarel
cfbab8fbab clk: bcm2835: Add PWM clock support
Register the pwm clock for bcm2835.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24 20:38:38 -08:00
Remi Pommarel
6d18b8adbe clk: bcm2835: Support for clock parent selection
Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple
parent clocks. These clocks divide the rate of a parent which can be selected by
setting the proper bits in the clock control register.

Previously all these parents where handled by a mux clock. But a mux clock
cannot be used because updating clock control register to select parent needs a
password to be xor'd with the parent index.

This patch get rid of mux clock and make these clocks handle their own parent,
allowing them to select the one to use.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24 20:38:30 -08:00
Remi Pommarel
9c95b32ca0 clk: bcm2835: add a round up ability to the clock divisor
Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor
so that the resulting average rate will not be higher than the requested one.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24 20:38:06 -08:00
Michael Turquette
5b50c522d5 Merge branch 'clk-lpc32xx' into clk-next 2015-12-24 12:34:29 -08:00
Vladimir Zapolskiy
f7c82a60ba clk: lpc32xx: add common clock framework driver
Add support for all configurable clocks found on NXP LPC32xx SoC.

The list contains several heterogenous groups of clocks:
* system clocks including multiple dividers and muxes,
* x397 PLL, HCLK PLL and USB PLL,
* peripheral clocks inherited from rtc, hclk and pclk,
* USB controller clocks: AHB slave, I2C, OTG, OHCI and device.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24 12:31:26 -08:00
Vladimir Zapolskiy
8a896310a7 clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbol
The change adds COMMON_CLK_NXP configuration symbol and enables it for
NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp
folder for NXP common clock framework drivers other than LPC18XX one.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24 12:31:24 -08:00
Michael Turquette
cf87a88f51 Allwinner clocks changes for 4.5
Clock patches for the Allwinner SoCs:
   - H3 clocks
   - A10/A20 Video Engine clocks
   - DRAM gates
   - A80 special CPU clock
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWcyKFAAoJEBx+YmzsjxAgtNMP/jJWzfh8bLB+eCZHGtBm/Y86
 em0DaAFWoAYOo0iFGRNkiJ+Gk5lOFx/qLjMbHitfEk00lNs9L2Goyzhko1WnaLQ6
 ZmJK1X3bcd5Uyqa3O8RP3zu0NUDin4sU4ZhKT8PuSkPEO69wSlgn+4R3e46jlRVg
 +1dbeEs68N10PjIBPqoCDYuP3YJW+nbdJQ03M4M9W6xNVgxtz/FVv1i3W61m3+r2
 LInUfr4A/+Mr3hNlGol4PEq8HP4xdfXRnrnSPNKJfysxc+9e2al6hmfiiBlSyhV2
 Z6HPG2qaxWMGCBG/q0SOh0I1vL8CgWbw0E04Wu5hzSBBaaS+KIEU6KqMQKFLyw5C
 U5V4z0g2ePs8SZD3SB1taB2y3dVtCwtOWvo/teAOKc7zXe/3wPRAWyxg4N5IGX/C
 bwHQGrDKuwsXVySAXqPXEojwTToF/TxqsS1RpunjLA2JIb1dvREUP0MMPXgPZJKN
 yiZLfeWw4SDonSPagSy/AQuEjih5ekZmT2aIOU4oCAqjpre6gQaolQn1xriL+ACf
 qdT4Hcg2hzlkjPB0N9izI7Krcef4oZpzZqls2/M9CnmTeMY4l2z9lZylqto4HnLF
 VT3duWXlmh8g9YGiWpMWwtcl0kXxP2mYM959k9KFrtvX7lhN4T2hmJwRnnCRCKre
 Zpt/9dotvmyM5Dno0Pee
 =Tahe
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clocks-for-4.5' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner clocks changes for 4.5

Clock patches for the Allwinner SoCs:
  - H3 clocks
  - A10/A20 Video Engine clocks
  - DRAM gates
  - A80 special CPU clock
2015-12-23 23:23:18 -08:00
Michael Turquette
a915e30dd2 Merge branch 'clk-rockchip' into clk-next 2015-12-23 13:08:56 -08:00
Xing Zheng
b0158bb27c clk: rockchip: rk3036: include downstream muxes into fractional dividers
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported RK3036 SoCs.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:31 -08:00
Heiko Stuebner
2eb8c7104c clk: add flag for clocks that need to be enabled on rate changes
Some clocks need to be enabled to accept rate changes. This patch adds a
new flag CLK_SET_RATE_UNGATE that lets clk_change_rate enable the clock
before trying to change the rate and disable it again afterwards.
This of course doesn't effect clocks that are already running at that
point, as their refcount will only temporarily increase.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:31 -08:00
Sjoerd Simons
84a8c54166 clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288
SoCs only feed those clocks, allow those clocks to change their parents
all the way up the hierarchy.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:30 -08:00
Heiko Stuebner
6674642089 clk: rockchip: include downstream muxes into fractional dividers
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported Rockchip SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:30 -08:00
Heiko Stuebner
8ca1ca8f60 clk: rockchip: handle mux dependency of fractional dividers
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature"
that requires the downstream mux to actually point to the fractional
divider and the fractional divider gate to be enabled, for it to really
accept changes to the divider ratio.

The downstream muxes themselfs are not generic enough to include them
directly into the fractional divider, as they have varying sources of
parent clocks including not only clocks related to the fractional
dividers but other clocks as well.

To solve this, allow our clock branches to specify direct child clock-
branches in the new child property, let the fractional divider register
its downstream mux through this and add a clock notifier that temporarily
switches the mux setting when it notices rate changes to the fractional
divider.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23 12:57:29 -08:00
Michael Turquette
ce6dd266d5 Merge branch 'clk-bcm2835' into clk-next 2015-12-22 16:49:38 -08:00
Eric Anholt
5e63dcc74b clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.
There are a pair of SPI masters and a mini UART that were last minute
additions.  As a result, they didn't get integrated in the same way as
the other gates off of the VPU clock in CPRMAN.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22 16:47:17 -08:00
Olof Johansson
84829814d6 The i.MX device tree updates for 4.5:
- New boards support: imx51-ts4800, imx6q-novena, CompuLab imx7d SoM/SBC,
   vf610m4-cosmic
 - Add ADC device support for imx6ul and imx7d
 - Remove config space from PCIe controller ranges property for i.MX6
 - Add Vivante GPU nodes for i.MX6
 - Add DCU, LCD, and SATA devices for LS1021A
 - A series to update Ventana gw5xxx boards getting HDMI and LVDS to work
   simultaneously and devices like PWM and SPI added
 - Quite a few random cleanups and minor updates
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJWeV5EAAoJEFBXWFqHsHzOk8YH/RrzIcDxVa7E6PiVErJmDluH
 ihMgY1mQcgXBcBEVKc0F9gKXZVN7W1xHGTHxVZp83mTxEJArBjFhojFQYReUaALU
 sQKot0sD8EWBlcC+fvuLzhHc8jE2Udioi/Ys/kgl8T82Q/LXTCnUmBnsPaVshqod
 WQ4i4Hk/QV6FbCEgvJvwEMEth53JYLVlAkuVbXi32eo7iv6u6d/LEdCW88bpV8Gv
 OxnGg8BiBV3TdAaAcNX72p5IRy9AYMY2hYIx9MCec+H2ws/jzn7xvfkhLta6luTP
 4JMvdToQWkhscIEDK1Q/3PtJVmX1al1PWKLTve3tza6jTTc7Opav8XN1hH3nJls=
 =hXxT
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

The i.MX device tree updates for 4.5:
- New boards support: imx51-ts4800, imx6q-novena, CompuLab imx7d SoM/SBC,
  vf610m4-cosmic
- Add ADC device support for imx6ul and imx7d
- Remove config space from PCIe controller ranges property for i.MX6
- Add Vivante GPU nodes for i.MX6
- Add DCU, LCD, and SATA devices for LS1021A
- A series to update Ventana gw5xxx boards getting HDMI and LVDS to work
  simultaneously and devices like PWM and SPI added
- Quite a few random cleanups and minor updates

* tag 'imx-dt-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits)
  ARM: dts: imx7d: sbc-imx7: add basic board support
  ARM: dts: imx7d: cl-som-imx7: add basic module support
  ARM: dts: TS-4800: add touchscreen support
  ARM: dts: ts-4800: Add LCD support
  ARM: dts: imx6q: add Novena board
  devicetree: bindings: Add vendor prefix for Kosagi
  ARM: dts: TS-4800: use weim IP to map the FPGA
  ARM: dts: TS-4800: drop uart rts/cts pin reservations
  ARM: dts: imx6: add Vivante GPU nodes
  ARM: dts: imx28: add alternate auart4 pinmux
  ARM: dts: ls1021a: add sata node to dts
  ARM: dts: TS-4800: add basic device tree
  of: documentation: add bindings documentation for TS-4800
  of: add vendor prefix for Technologic Systems
  ARM: dts: imx7d-sdb: add ADC support
  ARM: dts: imx7d.dtsi: add ADC support
  ARM: dts: vf-colibri: add CAN support
  ARM: mxs: dt: cfa10057: fix backlight PWM
  ARM: dts: imx6qdl: move GIC to right location in DT
  ARM: dts: imx6qdl: add IPU aliases
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2015-12-22 14:59:55 -08:00
Michael Turquette
471a9abeb1 Merge branch 'clk-dove' into clk-next 2015-12-22 12:34:39 -08:00
Russell King
63b8d92c79 clk: add Dove PLL divider support for GPU, VMeta and AXI clocks
Add support for the Dove PLL dividers, which are used to generate the
clocks for the AXI bus, as well as the GPU and VMeta peripherals.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22 12:25:00 -08:00
Michael Turquette
1807b34f95 Merge tag 'clk-samsung-4.5' of git://linuxtv.org/snawrocki/samsung into clk-next
drivers/clk/samsung updates (mostly bug fixes):
 - instantiation of the cpu clocks and addition of the GSCL
   IP parent clocks to the list of available consumer clocks
   for exynos542x SoCs;
 - MFC IP parent clock fix for exynos542x;
 - fix of locking bug in samsung/clk-cpu.c which caused
   system crashes with cpufreq enabled;
 - minor cleanup for s3c2410.
2015-12-22 11:57:37 -08:00
Michael Turquette
b8f15e7119 Merge commit 'fe5fa8fbd4d47f40a45fa29ee1abdb10cb061ec2' into clk-next 2015-12-22 11:57:35 -08:00
Michael Turquette
fcd5ac1a41 Merge tag 'imx-clk-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
The i.MX clock updates for 4.5:
- Add is_prepared function callback for pllv3 clock driver
- Use imx_check_clocks() on imx6ul and imx7d clock drivers to save
  some code
- Add a core clock for imx7d to support generic cpufreq driver
- Support imx6q clock routing with OSC to anaclk2/2b
- To support more precise pixel clocks on imx5, allow ipu_di_sel clock
  selectors to influence the PLLs that they are derived from
- A cleanup on imx25 OSC clock
2015-12-22 11:57:34 -08:00
Michael Turquette
eaaa6fb53f Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Rockchip clock changes for 4.5 containing
- a new pll-type used on rk3036 and other Cortex-A7 socs
- new clock-trees for rk3036 and rk3228
- switch rk3288 plls to slow mode on reboot
- a bunch of new clock ids
- some more critical clocks
- wrong register offsets for the rk3368 cpuclks
- allowing more than 2 parents for the cpuclk
2015-12-22 11:57:33 -08:00
Michael Turquette
d90e149666 Merge branch 'clk-shmobile-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next 2015-12-22 11:57:32 -08:00
Masahiro Yamada
3837bd277a clk: fix codying style of if ... else blocks
This code is unreadable due to the blank line between if and else
blocks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22 10:11:52 -08:00
Shawn Guo
c89dcce4e1 Merge branch 'imx/clk' into imx/dt 2015-12-22 20:40:27 +08:00
Heiko Stuebner
dfff24bde7 clk: rockchip: only enter pll slow-mode directly before reboots on rk3288
As commit 1d33929e2a ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.

The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.

Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.

This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.

For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.

With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.

Fixes: 1d33929e2a ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288")
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-21 02:01:19 +01:00
Arnd Bergmann
d0b6342df0 Merge branch 'fixes' into next/multiplatform
The 'fixes' branch contains d5d4fdd86f ("irqchip/versatile-fpga:
Fix PCI IRQ mapping on Versatile PB") that is required for booting
the versatile platform prior to the rework in this branch, but
including both causes a build-time error.

I'm doing an evil merge here to pull in the fixes branch so we have
that commit included but at the same time revert the trivial change.
This gives us a bisectable history.

* fixes: (22 commits)
  fsl-ifc: add missing include on ARM64
  ls2080a/dts: Add little endian property for GPIO IP block
  dt-bindings: define little-endian property for QorIQ GPIO
  ARM64: dts: ls2080a: fix eSDHC endianness
  ARM: dts: vf610: use reset values for L2 cache latencies
  ARM: pxa: use PWM lookup table for all machines
  ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1
  ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock
  ARM: dts: am4372: fix clock source for arm twd and global timers
  ARM: at91: fix pinctrl driver selection
  ARM: at91/dt: add always-on to 1.8V regulator
  ARM: dts: vf610: fix clock definition for SAI2
  ARM: imx: clk-vf610: fix SAI clock tree
  ARM: ixp4xx: fix read{b,w,l} return types
  irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB
  ARM: OMAP2+: enable REGULATOR_FIXED_VOLTAGE
  ARM: dts: add dm816x missing spi DT dma handles
  ARM: dts: add dm816x missing #mbox-cells
  cpufreq: s3c24xx: Do not mark s3c2410_plls_add as __init
  bus: sunxi-rsb: unlock on error in sunxi_rsb_read()
  ...
2015-12-17 22:33:58 +01:00
Bill Huang
2d7f61f377 clk: tegra: Read correct IDDQ register in PLL_SS registration
This fixes a bug in tegra_clk_register_pllss() which mistakenly assume
the IDDQ register is the PLL base address.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:58 +01:00
Bill Huang
a4ca2b2fe7 clk: tegra: Fix WARN_ON in PLL_RE registration
This fixes two things.

- Read the correct IDDQ register
- Check the correct IDDQ bit position

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:57 +01:00
Andrew Bresticker
afff455cf4 clk: tegra: pll: Fix issues with rates for VCO PLLs
Without this change clk_get_rate would return the final output
rather than the VCO output as it would factor in the pdiv when
it shouldn't. This will cause problems for all dividers in the
subtree of the VCO PLL.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:57 +01:00
Rhyland Klein
6b301a059e clk: tegra: Add support for Tegra210 clocks
Implement clock support for Tegra210.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:56 +01:00
Bill Huang
139fd30943 clk: tegra: Add Super Gen5 Logic
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:55 +01:00
Bill Huang
0ef9db6cf2 clk: tegra: pll: Add logic for SS
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:55 +01:00
Rhyland Klein
17e9273a9e clk: tegra: pll: Add dyn_ramp callback
Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:54 +01:00
Bill Huang
b985114e2f clk: tegra: pll: Add Set_default logic
Add logic which (if specified for a pll) can verify that a PLL is set
to the proper default value and if not can set it. This can be
specified per PLL as each will have different default values.

Based on original work by Aleksandr Frid <afrid@nvidia.com>

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:54 +01:00
Bill Huang
b5512b45d5 clk: tegra: pll: Adjust vco_min if SDM present
This code makes use of the SDM fractional divider if present to
constrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.

Based on original work by Aleksandr Frid <afrid@nvidia.com>

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:53 +01:00
Rhyland Klein
6929715cf6 clk: tegra: pll: Add support for PLLMB for Tegra210
Tegra210 SoC's have 2 PLLs for memory usage. Add plumbing to register
and handle PLLMB.

PLLMB is used to allow switching between 2 PLLM's without having to use
and intermediate backup PLL, as we need to lock the PLL before we can
switch to it.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:53 +01:00
Rhyland Klein
dd322f047d clk: tegra: pll: Add specialized logic for Tegra210
On Tegra210 SoC's, the logic to enable several of the plls is different
from previous generations. Therefore, add registration functions specific
to Tegra210 which will handle them appropriately.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:52 +01:00
Yakir Yang
2abc02fc49 clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vio
ACLK_VIO is the noc bus clock for display module, display cann't
read data from ddr without this clock enabled.

Due to it shouldn't belong to any driver, but we need it enabled,
so just mark it as the CLK_IGNORE_UNUSED flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-16 22:24:13 +01:00
Prasanna Karthik
c5e949c1c2 clk: s3c2410: removed unneeded variable in s3c24xx_clkout_set_parent
Remove unneeded variable used to store return value.

Signed-off-by: Prasanna Karthik <mkarthi3@visteon.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16 16:36:04 +01:00
Marek Szyprowski
6b4feaea25 clk: exynos: use irqsave version of spin_lock to avoid deadlock with irqs
It is allowed to enable/disable clocks from interrupts, so common Exynos
ARM clock management code for CPUfreq should use 'irqsave' version of
spin_lock calls to avoid potential deadlock caused by spin_lock recursion.
The same spin_lock is used by gate/mux clocks during enable/disable calls.

This deadlock, can be reproduced by enabling CPUfreq (ondemand or
userspace) and decoding video with s5p-mfc driver.

Relevant stack trace:
[ 5928.061534] BUG: spinlock recursion on CPU#0, bash/1252
[ 5928.061609]  lock: 0xee80454c, .magic: dead4ead, .owner: bash/1252, .owner_cpu: 0
[ 5928.068586] CPU: 0 PID: 1252 Comm: bash Tainted: G        W       4.4.0-rc4-00001-g447a7fd #678
[ 5928.077260] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[ 5928.083359] [<c00153dc>] (unwind_backtrace) from [<c00121b4>] (show_stack+0x10/0x14)
[ 5928.091072] [<c00121b4>] (show_stack) from [<c0213e28>] (dump_stack+0x68/0xb8)
[ 5928.098275] [<c0213e28>] (dump_stack) from [<c005c1ec>] (do_raw_spin_lock+0x184/0x1ac)
[ 5928.106177] [<c005c1ec>] (do_raw_spin_lock) from [<c05cfa98>] (_raw_spin_lock_irqsave+0x20/0x28)
[ 5928.114943] [<c05cfa98>] (_raw_spin_lock_irqsave) from [<c0468698>] (clk_gate_endisable+0x24/0x98)
[ 5928.123882] [<c0468698>] (clk_gate_endisable) from [<c0464d40>] (clk_core_disable+0x60/0x84)
[ 5928.132299] [<c0464d40>] (clk_core_disable) from [<c0465e00>] (clk_disable+0x24/0x30)
[ 5928.140117] [<c0465e00>] (clk_disable) from [<c03f3b80>] (s5p_mfc_handle_frame+0x254/0x860)
[ 5928.148445] [<c03f3b80>] (s5p_mfc_handle_frame) from [<c03f4b34>] (s5p_mfc_irq+0x890/0xa24)
[ 5928.156778] [<c03f4b34>] (s5p_mfc_irq) from [<c00627bc>] (handle_irq_event_percpu+0x50/0x14c)
[ 5928.165283] [<c00627bc>] (handle_irq_event_percpu) from [<c00628f0>] (handle_irq_event+0x38/0x5c)
[ 5928.174143] [<c00628f0>] (handle_irq_event) from [<c0065864>] (handle_fasteoi_irq+0xdc/0x1a4)
[ 5928.182645] [<c0065864>] (handle_fasteoi_irq) from [<c0062090>] (generic_handle_irq+0x18/0x28)
[ 5928.191236] [<c0062090>] (generic_handle_irq) from [<c00621a4>] (__handle_domain_irq+0x6c/0xdc)
[ 5928.199917] [<c00621a4>] (__handle_domain_irq) from [<c0009470>] (gic_handle_irq+0x4c/0x98)
[ 5928.208249] [<c0009470>] (gic_handle_irq) from [<c0012c54>] (__irq_svc+0x54/0x90)
[ 5928.215709] Exception stack(0xeddb5cb8 to 0xeddb5d00)
[ 5928.220745] 5ca0:                                                       ee80454c faddfadc
[ 5928.228906] 5cc0: 00000000 01000001 ee831ce0 f8114200 ee807c00 01130520 00000403 eddb5d84
[ 5928.237063] 5ce0: ee807c48 2faf0800 ee807c0c eddb5d08 c046b618 c046b634 20000053 ffffffff
[ 5928.245225] [<c0012c54>] (__irq_svc) from [<c046b634>] (exynos_cpuclk_notifier_cb+0x170/0x270)
[ 5928.253823] [<c046b634>] (exynos_cpuclk_notifier_cb) from [<c003cb58>] (notifier_call_chain+0x44/0x84)
[ 5928.263106] [<c003cb58>] (notifier_call_chain) from [<c003ccd4>] (__srcu_notifier_call_chain+0x6c/0x9c)
[ 5928.272480] [<c003ccd4>] (__srcu_notifier_call_chain) from [<c003cd1c>] (srcu_notifier_call_chain+0x18/0x20)
[ 5928.282288] [<c003cd1c>] (srcu_notifier_call_chain) from [<c0464ed0>] (__clk_notify+0x6c/0x74)
[ 5928.290881] [<c0464ed0>] (__clk_notify) from [<c0465388>] (clk_propagate_rate_change+0xa0/0xac)
[ 5928.299561] [<c0465388>] (clk_propagate_rate_change) from [<c0465378>] (clk_propagate_rate_change+0x90/0xac)
[ 5928.309370] [<c0465378>] (clk_propagate_rate_change) from [<c04666fc>] (clk_core_set_rate_nolock+0x64/0xa8)
[ 5928.319091] [<c04666fc>] (clk_core_set_rate_nolock) from [<c0466760>] (clk_set_rate+0x20/0x30)
[ 5928.327686] [<c0466760>] (clk_set_rate) from [<c0428c70>] (set_target+0xe8/0x23c)
[ 5928.335152] [<c0428c70>] (set_target) from [<c04244d0>] (__cpufreq_driver_target+0x184/0x29c)
[ 5928.343655] [<c04244d0>] (__cpufreq_driver_target) from [<c0427128>] (cpufreq_set+0x44/0x64)
[ 5928.352074] [<c0427128>] (cpufreq_set) from [<c0423948>] (store_scaling_setspeed+0x5c/0x74)
[ 5928.360407] [<c0423948>] (store_scaling_setspeed) from [<c04238d0>] (store+0x7c/0x98)
[ 5928.368221] [<c04238d0>] (store) from [<c0132540>] (sysfs_kf_write+0x44/0x48)
[ 5928.375338] [<c0132540>] (sysfs_kf_write) from [<c0131b9c>] (kernfs_fop_write+0xb8/0x1bc)
[ 5928.383496] [<c0131b9c>] (kernfs_fop_write) from [<c00d71f8>] (__vfs_write+0x2c/0xd4)
[ 5928.391308] [<c00d71f8>] (__vfs_write) from [<c00d7de8>] (vfs_write+0xa0/0x144)
[ 5928.398598] [<c00d7de8>] (vfs_write) from [<c00d8048>] (SyS_write+0x44/0x84)
[ 5928.405631] [<c00d8048>] (SyS_write) from [<c000f540>] (ret_fast_syscall+0x0/0x3c)

CC: stable@vger.kernel.org  # v4.2+
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16 16:36:03 +01:00
Marek Szyprowski
34d3b67467 clk: samsung: exynos542x: fix MFC clock hierarchy parent
Proper source for MFC block is mout_user_aclk333 (in datasheet named
USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16 16:36:02 +01:00
Bartlomiej Zolnierkiewicz
54abbdb4ee clk: samsung: exynos542x/5800: fix cpu clock configuration data
Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).

Based on Hardkernel's kernel for ODROID-XU3 board.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16 16:35:57 +01:00
Thomas Abraham
bee4f87f01 clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.

Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16 16:35:26 +01:00
Marek Szyprowski
c0feb268da clk: samsung: exynos542x: add missing parent GSCL block clocks
This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16 16:35:17 +01:00
Arnd Bergmann
22ba14f41c The board and infrastructure changes for RealView
multiplatform and extended DT support.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWb9LqAAoJEEEQszewGV1z1I4QAIgylTG1hftD5xCtaKsgJv5X
 pcp+eVVCeYjeO3AbknrXzBlty0u3/rDOR6n9aUn7ci63qErGi2GeoZ5glo6y3aOU
 qKo2/M0LOoP3y6SGxMjaPTTpStjKsaj2XLjHLNrSHAKXsvoFB69vnAlQh2jU+ohX
 JEl9wvkugMWicGaiooWQfG7OAf2Gb6AFAKQUfYNVNNXBTD13oQcFRgLwBKDkNlc9
 7N6yzPQDNQiauytr7Ji/49fbkiOLFSB5yllhecb37F/b56XprGvsXJTRwsQhPwbj
 ig28qu/g7LhfnkZUOTwhWH6WdyFarMlpA8oHHKrZBeGySgvdjXBVYH4IQAfhT2N9
 WSh/he+w8T2+oMVj97gLSxKiP4ugUSsBR6daq5X8NESobxFVYzmFIYQxKxOwFif4
 JDWvOKaQsRhx42iAq3CIMkh7yQsBC4tJjtyvVwHuGeC2zRlyODbBCnN4OGKDdYpJ
 +VY4kr48Yld5IxYm6J6fXOEWTcFw2n/hvEVsik5mmgw1rYivJsCcvcVxv04xZYCl
 6d13eCaSh2TfeKYs/Qf2yy3hmps4dWFcd18/xWRyFdnkCs5qGRbtgLiAQtUnQAGm
 bpaI/rYeRnnF80af2dhpZT2i0zBL9uuur7FYZDB9xsQDOkqnCYxKvSW1CfNg5Gtc
 senI3dczeTC3NtwRp4eC
 =Zhx3
 -----END PGP SIGNATURE-----

Merge tag 'realview-base-armsoc-1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/multiplatform

Merge "Realview multiplatform support" from Linus Walleij:

The board and infrastructure changes for RealView
multiplatform and extended DT support.

* tag 'realview-base-armsoc-1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  ARM: realview: add an DT SMP boot method
  ARM: realview: select SP810 and ICST for the DT variant
  soc: versatile: add support for the PB11MPCore
  clk: versatile-icst: add device tree support
  clk: versatile-icst: refactor to allocate regmap separately
  clk: versatile-icst: convert to use regmap
  ARM: realview: remove private barrier implementation
  ARM: no longer force unbuffered DMA for realview
  clk/realview: stop using machine headers
  ARM: realview: don't map undefined PCI registers
  ARM: realview: remove sparsemem hack

Conflicts:
	drivers/clk/versatile/Kconfig
2015-12-16 00:56:18 +01:00
Arnd Bergmann
7379d96bda Merge branch 'versatile/multiplatform' into next/multiplatform
Merge "ARM Versatile multi-platform support" from Rob Herring:

Arnd lit a fire under me to dust this off and get it merged. So here it
is. The main change from prior version is I merged all the code to a
single file. It's a bigger patch than I'd like, but I don't think trying
to do it in multiple steps is worth it.

This is dependent on some solution for the default platform choice on
!MMU builds (allnoconfig) as it can't be Versatile after this series.
Arnd has some ideas on how to address that.

This is tested under QEMU. Linus previously tested this on actual h/w
and had a problem with the display identification which needs
investigation or agreement to worry about it if and when someone
actually cares.

* versatile/multiplatform:
  ARM: versatile: convert to multi-platform
  ARM: versatile: merge mach code into a single file
  ARM: versatile: switch to DT only booting and remove legacy code
  ARM: versatile: add DT based PCI detection

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-15 23:55:32 +01:00
Rob Herring
16956fed35 ARM: versatile: switch to DT only booting and remove legacy code
With DT support for clocks, irqchips, timers, and PCI now in place, DT
based booting has feature parity with non-DT legacy boot. The final
piece is actually enabling common clock support on Versatile. Enabling
full DT support requires either removing the old Versatile clock code,
updating the legacy boot to use the common clock code, or making DT and
legacy boot mutually exclusive. Given that removing legacy boot code is
the goal anyway, I am going with the 1st option.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-12-15 23:53:21 +01:00
Arnd Bergmann
8864eaca90 Merge branch 'mmp/multiplatform' into next/multiplatform
* mmp/multiplatform:
  ARM: mmp: avoid unused functions
  ARM: mmp: move into ARCH_MULTIPLATFORM
  ARM: mmp: make all header files local
  ARM: mmp: make plat-pxa build standalone
  ARM: mmp: remove remaining legacy pxa-dma support
  ARM: mohawk: allow building with MMU disabled
  ARM: make xscale iwmmxt code multiplatform aware
  clk: mmp: stop using platform headers
2015-12-15 23:45:45 +01:00
Linus Walleij
d430819d69 clk: versatile-icst: add device tree support
This adds support for the ARM syscon ICST clocks to initialized
directly from the device tree syscon node on ARM Integrator,
Versatile and RealView reference designs.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-15 09:42:50 +01:00
Linus Walleij
384d977d74 clk: versatile-icst: refactor to allocate regmap separately
Break out the registration function so it creates a regmap and
pass to the setup function, so the latter can be shared with
a device tree probe function that already has a regmap.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-15 09:42:49 +01:00
Linus Walleij
179c8fb3c2 clk: versatile-icst: convert to use regmap
Instead of passing around register bases, pass around a regmap
in this driver. This refactoring make things so much easier when
we later want to manage an ICST that is part of a syscon.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-15 09:42:48 +01:00
Arnd Bergmann
3c30a4a357 clk/realview: stop using machine headers
In order to move realview into multiplatform, we have to prevent device
drivers from accessing the machine header files.

In case of the clk driver, this is very simple, we just copy the
small set of register definitions into the driver that needs them.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-15 09:41:33 +01:00
Andrzej Hajda
fee3103ac3 clk: sunxi: fix handling return value of of_property_match_string
The function can return negative values, so its result should
be assigned to signed variable.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2046107

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-14 13:54:11 +01:00