Add the USB OTG phy under the CREG syscon node and attach it to
the USB0 EHCI controller.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The CREG block contains a collection of miscellaneous
configuration register like Ethernet phy mode, low
power clocks and DMA multiplexer. These registers
needs to be accessed from other drivers and syscon
provides this capability.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add gpio and mapping between pinctrl/gpio namespace with
gpio-ranges property.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add CGU and CCU clock-controller nodes for lpc18xx together with
the fixed input clocks. Also remove the temporary fixed-factor
pll1 clock from both lpc18xx and lpc4350-hitex-eval DTS now that
proper clock drivers are inplace.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
NXP LPC18xx/43xx SoCs are very similar devices and should be able to
share a common base (lpc18xx.dtsi). Diffences between the devices are
put in a dtsi which is specific to that device.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
