Pins used for joystick are all configured as input. "push-pull" is not a
valid setting for an input pin.
Fixes: a502b343eb ("pinctrl: stmfx: update pinconf settings")
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
"push-pull" configuration is now fully handled by the gpiolib and the
STMFX pinctrl driver. There is no longer need to declare a pinctrl group
to only configure "push-pull" setting for the line. It is done directly by
the gpiolib.
Fixes: a502b343eb ("pinctrl: stmfx: update pinconf settings")
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Split the 10Kbytes CAN message RAM to be able to use simultaneously
FDCAN1 and FDCAN2 instances.
First 5Kbytes are allocated to FDCAN1 and last 5Kbytes are used for
FDCAN2. To do so, set the offset to 0x1400 in mram-cfg for FDCAN2.
Fixes: d44d6e0213 ("ARM: dts: stm32: change CAN RAM mapping on stm32mp157c")
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
The HDMI controller definition in the A31 DTSI has a reset-names property,
yet the binding for that controller doesn't declare it.
Remove it.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Allwinner H3 SoC contains deinterlace unit, which can be used in
combination with VPU unit to decode and process interlaced videos.
Add a node for it.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Both, H3 and H5, contain MBUS, which is the bus used by DMA devices to
access system memory.
MBUS controller is responsible for arbitration between channels based
on set priority and can do some other things as well, like report
bandwidth used. It also maps RAM region to different address than CPU.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The ECSPI1 is not used for a FRAM chip, so remove the comment.
While at it, also change some whitespaces to tabs to comply with the
indentation style of the rest of the file.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
To silence the warnings shown by the driver at boot time, we add a
fixed regulator for the 5V supply of usbotg2 and specify the polarity
of the overcurrent signal for usbotg1.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Kontron N6x1x SoMs all use uart4 as a debug serial interface.
Therefore we set it in the 'chosen' node.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The 'N6311 S' and the 'N6411 S' are similar to the Kontron 'N6310 S'
evaluation kit boards. Instead of the N6310 SoM, they feature a N6311
or N6411 SoM.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The baseboard for the Kontron N6310 SoM is also used for other SoMs
such as N6311 and N6411. In order to share the code, we move the
definitions of the baseboard to a separate dtsi file.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The snvs-poweroff driver can power off the system by pulling the
PMIC_ON_REQ signal low, to let the PMIC disable the power.
The Kontron SoMs do not have this signal connected, so let's remove
the node.
This fixes a real issue when the signal is asserted at poweroff,
but not actually causing the power to turn off. It was observed,
that in this case the system would not shut down properly.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Fixes: 1ea4b76cdf ("ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The N6311 and the N6411 SoM are similar to the Kontron N6310 SoM.
They are pin-compatible, but feature a larger RAM and NAND flash
(512MiB instead of 256MiB). Further, the N6411 has an i.MX6ULL SoC,
instead of an i.MX6UL.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Kontron N6311 and N6411 SoMs are very similar to N6310. In
preparation to add support for them, we move the common nodes to a
separate file imx6ul-kontron-n6x1x-som-common.dtsi.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds a devicetree for the Kobo Clara HD Ebook reader. It
is on based on boards called "e60k02". It is equipped with an
imx6sll SoC.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Netronix board E60K02 can be found some several Ebook-Readers,
at least the Kobo Clara HD and the Tolino Shine 3. The board
is equipped with different SoCs requiring different pinmuxes.
For now the following peripherals are included:
- LED
- Power Key
- Cover (gpio via hall sensor)
- RC5T619 PMIC (the kernel misses support for rtc and charger
subdevices).
- Backlight via lm3630a
- Wifi sdio chip detection (mmc-powerseq and stuff)
It is based on vendor kernel but heavily reworked due to many
changed bindings.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
- Enable L2 cache parity and ECC on a Armada XP SoC family and allow
to use in on the Armada 38x SoCs too.
- Use correct name for the rs5c372a on synology (Kirkwood based)
- Rename "sa-sram" node to "sram" on dove
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXb9ANAAKCRALBhiOFHI7
1YxGAJ42trDdNhPczQeHvNx2UcvmSKU8rQCfdNMvDGGosrbJ/aWklGPQfU4iano=
=0o2E
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu into arm/dt
mvebu dt for 5.5 (part 1)
- Enable L2 cache parity and ECC on a Armada XP SoC family and allow
to use in on the Armada 38x SoCs too.
- Use correct name for the rs5c372a on synology (Kirkwood based)
- Rename "sa-sram" node to "sram" on dove
* tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada-xp: add label to sdram-controller node
ARM: dts: mvebu: add sdram controller node to Armada-38x
ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
ARM: dts: dove: Rename "sa-sram" node to "sram"
ARM: dts: kirkwood: synology: Fix rs5c372 RTC entry
Link: https://lore.kernel.org/r/8736f44q9l.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC
frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the
STMPE ADC found on Toradex T30 modules as well as fixes for eDP
support on Venice2.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl29juUTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoZ7rD/9XhTBgFXzd5C6yyJpjIBD/3F/4vnlK
SZ/3ZktWe9ZzwQJhMXaURxaggrTD0MXJj95/Ga03FSxtYBgb7mT6TL0m7QCnMjhR
MSekoWQaBU+MUTIUbfT/2YS1+6JTnwRxQBDD+2/qPwI6HcnJ/BIzIN7fRlAh4Xu8
TwzQdzE2pym4PPIAkiiu7iTcF468tFiRUWj01o06B/k21tHNnNqYUP/1KLY6N5pZ
oqn+FAXfgLFrmjUQi28Z+0UyAekeDl7kLmoNMUerFqI53j3+n5iosogUWznnO9NG
tN88ftULL7lA29NR7nnu++Ev5UiE/40HrpuxTcQkHLE4mNQX9eGHrhZ1/kP9ZLnN
bysYxlzr1IXZ8Mefe8Z422wQvNlQWuvNfbS0no0Xkn4H3HH0ajmYF5uv0tIna9q2
A0eWGWbhbEyuaPzSiOWMpo4Ae/bgV7PWQSdVyBluB+yX8bXoSRr8o8I3xd6uWjaY
cgF5BN32AwM44k3jgI8+HkdSxzvpdrPsxGitwpy+Yr3AW15SJ3uWA0sEemuZQ81P
+ZX+YEepCwVIgDp34oP+vWwfbGRoo3rNJrOM2CCADHQ+p1pXARKQmHRpxU2X3L35
akYNdjhvi04cIoLcP748YZYQ0Z8/Kjiofg1dMSGjmAVQZgOyF7YUrURm3x9qR6rU
yVlQPmJDj0gF5A==
=rlo7
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.5-rc1
Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC
frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the
STMPE ADC found on Toradex T30 modules as well as fixes for eDP
support on Venice2.
* tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: cardhu-a04: Add CPU Operating Performance Points
ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS
ARM: tegra: trimslice: Add CPU Operating Performance Points
ARM: tegra: paz00: Add CPU Operating Performance Points
ARM: tegra: paz00: Set up voltage regulators for DVFS
ARM: tegra: Add CPU Operating Performance Points for Tegra30
ARM: tegra: Add CPU Operating Performance Points for Tegra20
ARM: tegra: Add Tegra30 CPU clock
ARM: tegra: Add Tegra20 CPU clock
ARM: tegra: Add External Memory Controller node on Tegra30
ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6
ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30
ARM: tegra: Add eDP power supplies on Venice2
ARM: tegra: Add SOR0_OUT clock on Tegra124
ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules
Link: https://lore.kernel.org/r/20191102144521.3863321-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This series of changes adds the PRM reset driver nodes for am3/4, omap4/5
and dra7 SoCs. The reset driver changes make it easier to add support for
various accelerators for TI SoCs in a more generic way.
Note that this branch is based on the PRM reset driver changes branch.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl28UrgRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPQvw/+Kz/OaUWXc6NCGqbgrjvQZbJMzWykeuP3
QyIzQ/k6x9B1VqkHvnmbAUKEpROXe7/t8QaVZs2WfQLb/3QvOJtEN5KlgGOC1ofF
VLWR1aSU1bApDIbTf0tIhIEkmsm/qJvm4QlRBLahQEtP/2LRuZMybikBgbEteFMB
zgMUPjqc//gGI1Y8H90ntWlCA0runosrxJ83qJ4O74RMzBiH30h3qZFq7Xt4O/az
x0B4u+RBB3hnetq6oHBsk6TFbE0qmOBYSx81w40GM4Rn5Xgvq62PaoRHez/qLRRB
3GhtfIUb5bJX3w8wQF6wyIUQfIFjYKDut3mldx1zR01x8QwYMl5b8aD9M5MIern4
+KVT5rtjllnbMQYhOmQKky5UCKU1SOvYZDfN//4S68YF0DZ257vYFkeXIWHYA+pr
Cc8lVAgCqDV5WlBBXy2F6uZC7vQCdpPFI2ljEPryiEumJ3FlK+nY7WmpusJ6grau
BiJakyYS0dqqoJS+LH7GtB3PLChgGXIQd9SWF5NvCzbtr+4ve7dUCzTs/UitUpET
9B3kaoHE9s9UvozZkHFPxIhR7o2uAfSqUUMNCWplXy5jhPl6RFPB0myV66ai8v3U
ZVO+EAF0Bx47zz0riBlqraiMBybohohZAijZjQztHyeKE2CfBc1ErUPFAur32bF6
ML9ze/G+SkI=
=4DAS
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
PRM reset control dts changes for v5.5 merge window
This series of changes adds the PRM reset driver nodes for am3/4, omap4/5
and dra7 SoCs. The reset driver changes make it easier to add support for
various accelerators for TI SoCs in a more generic way.
Note that this branch is based on the PRM reset driver changes branch.
* tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap5: Add PRM data
ARM: dts: am43xx: Add PRM data
ARM: dts: am33xx: Add PRM data
ARM: dts: omap4: add PRM nodes
ARM: dts: dra7: add PRM nodes
soc: ti: omap-prm: add omap5 PRM data
soc: ti: omap-prm: add am4 PRM data
soc: ti: omap-prm: add dra7 PRM data
soc: ti: omap-prm: add data for am33xx
soc: ti: omap-prm: add omap4 PRM data
soc: ti: omap-prm: add support for denying idle for reset clockdomain
soc: ti: omap-prm: poll for reset complete during de-assert
soc: ti: add initial PRM driver with reset control support
dt-bindings: omap: add new binding for PRM instances
Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Make sure UART3, where the console is, is called ttyS2. That is
consistent with the early console.
Link: https://lore.kernel.org/r/20191031163455.1711872-5-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
Ponted out by DTC:
<stdout>: Warning (unit_address_vs_reg): /memory: node has a reg or ranges
property, but no unit name
Link: https://lore.kernel.org/r/20191031163455.1711872-4-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
There's a typo there that rightfully upsets DTS:
<stdout>: Warning (simple_bus_reg): /soc/watchdog@2c000620: simple-bus
unit address format error, expected "e0000620"
Link: https://lore.kernel.org/r/20191031163455.1711872-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
It should have one and DTC is indeed unhappy about its absence:
<stdout>: Warning (unit_address_vs_reg): /soc/clocks: node has a reg or
ranges property, but no unit name
Link: https://lore.kernel.org/r/20191031163455.1711872-2-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers
in this SoC with maximum of 32 gpios. Except GPIOC, all controllers
are capable of generating edge/level interrupts from first 8 lines.
Link: https://lore.kernel.org/r/20191030101154.6312-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
- Get SNVS power key back to work for imx6-logicpd board. It was
accidentally disabled by commit 770856f0da ("ARM: dts: imx6qdl:
Enable SNVS power key according to board design").
- Fix sparse warnings in IMX GPC driver by making the initializers
in imx_gpc_domains C99 format.
- Fix an interrupt storm coming from accelerometer on imx6qdl-sabreauto
board. This is seen with upstream version U-Boot where pinctrl is not
configured for the device.
- Fix sdma device compatible string for i.MX8MM and i.MX8MN SoC.
- Fix compatible of PCA9547 i2c-mux on LS1028A QDS board to get the
device probed correctly.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJdt+NxAAoJEFBXWFqHsHzO9dQIAItV9GBySkuQ74/LBBp9WHfi
Y708jUcbm/oEkic3bW+RdXpr+Xo3nP1E1VrdogqwWZStePS4JQtRWs7/+NAC/aiw
wrUDoCXnZYiSLtp+f/1OSs7mUSG13Ip+Um9VxjI1AI9ld1YKg8sSeg0Xlk5oNsk4
1/2c1P9nW0XjWMkpLqYzIbbtb+sisCX0/Ftyxw7vrjhpgJSDDUTE37IFgmdskZg6
ILl00chE4E+8AlLm9kdtqOgzihtFVbSIrhF99gbF6R9vZQGoYgOE3QM2YG+qhEOd
56bQTJJRVwutSbBGGv1ya/J5cmtZYDzoi10JEEQ+zkyrcU+G3qj9+8/wZORba5o=
=0kUv
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.4, 2nd round:
- Get SNVS power key back to work for imx6-logicpd board. It was
accidentally disabled by commit 770856f0da ("ARM: dts: imx6qdl:
Enable SNVS power key according to board design").
- Fix sparse warnings in IMX GPC driver by making the initializers
in imx_gpc_domains C99 format.
- Fix an interrupt storm coming from accelerometer on imx6qdl-sabreauto
board. This is seen with upstream version U-Boot where pinctrl is not
configured for the device.
- Fix sdma device compatible string for i.MX8MM and i.MX8MN SoC.
- Fix compatible of PCA9547 i2c-mux on LS1028A QDS board to get the
device probed correctly.
* tag 'imx-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mn: fix compatible string for sdma
arm64: dts: imx8mm: fix compatible string for sdma
ARM: dts: imx6-logicpd: Re-enable SNVS power key
soc: imx: gpc: fix initialiser format
ARM: dts: imx6qdl-sabreauto: Fix storm of accelerometer interrupts
arm64: dts: ls1028a: fix a compatible issue
Link: https://lore.kernel.org/r/20191029110334.GA20928@dragon
Signed-off-by: Olof Johansson <olof@lixom.net>
This is an Allwinner H3 based board, with 512MB ram, a USB OTG port,
microsd slot, an onboard AP6212A wifi/bluetooth module, and a CSI
connector.
Full details and schematic available from vendor:
http://wiki.friendlyarm.com/wiki/index.php/NanoPi_Duo2
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Simplify the Yamp device tree by using the common dtsi.
In addition this enables the following the second firmware flash and the
eMMC device in slot #1.
Signed-off-by: Tao Ren <taoren@fb.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Simplify the Minipack device tree by using the common dtsi.
In addition this enables the enabling the second firmware flash, and
updates it's size from 32MB to 64MB. It also enables the eMMC device in
slot #1.
Signed-off-by: Tao Ren <taoren@fb.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Simplify the CMM device tree by using the common dtsi.
In addition this enables the second firmware flash and the emmc device
in slot #0.
Signed-off-by: Tao Ren <taoren@fb.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This common descirption is included by all Facebook AST2500 Network BMC
platforms to minimize duplicated device entries across Facebook Network
BMC device trees.
Signed-off-by: Tao Ren <taoren@fb.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add in a gpio-keys section to the Rainier device tree source, add in the
power supply presence GPIOs.
Signed-off-by: Brandon Wyman <bjwyman@gmail.com>
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Fix the size of the Proc VRM card's eeprom used for vpd storage. The
size is changed from 64Kbit to 128Kbit.
Signed-off-by: Jinu Joy Thomas <jinu.joy.thomas@in.ibm.com>
Reviewed-by: Santosh Puranik <santosh.puranik.ibm@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Requesting pinmux configuration is done at driver probe time. The LPC IP
is composed of many sub-devices, each with their own driver, and no
driver exists for the entire IP block. Avoid having each sub-device
request the LPC pinmux by just hogging it in the pinctrl node.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Like most OpenPower machines the VUART is expected to be at /dev/ttyS5
for communication with the host over LPC.
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Added eeproms for the below VPD devices
- BMC
- TPM
- System Planar
- DCM 0 VRM
- DCM 1 VRM
- Base Op panel
- Lcd Op panel
- DASD (All)
- PCIe Cards (All)
Signed-off-by: Jinu Joy Thomas <jinu.joy.thomas@in.ibm.com>
Reviewed-by: Santosh Puranik <santosh.puranik.ibm@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
OpenBMC requires a window the same size as the image being loaded.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The UART has an issue on A0 that can be worked around by using the
Synopsis driver.
Tested-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The UARTs on the AST2600 A0 have a known issue that can be worked around
by using the Synopsys driver.
Tested-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
We need to ungate RCLK on AST2500- and AST2600-based platforms for RMII
to function. RMII interfaces are commonly used for NCSI.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
uart1 and uart3 had existing pin definitions for the rts/cts pairs.
Add definitions for uart2 as well.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms.
It could be found on Allwinner SoC A80 and A83T
This patch adds it on the Allwinner A80 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms.
It could be found on Allwinner SoC A80 and A83T
This patch adds it on the Allwinner A83T SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Crypto Engine is a hardware cryptographic offloader that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Add fan controllers, regulators, temperature sensors, power supplies
and regulators.
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Keep the FMC controller chips at a safe 50 MHz rate and use 100 MHz
for the PNOR on the machines using a AST2500 SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Use the SoC-specific compatible strings instead.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Adds a new power_green led to show the host state.
Signed-off-by: Alexander Filippov <a.filippov@yadro.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add gpio-keys for various signals on Tacoma.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This way enabling the MDIO controllers automatically requests the right
pinmux configuration.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The binding was updated to better reflect the intended use of the
hardware and the existing function/groups for SD3 were dropped.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The AST2600 u-boot and kernel images have outgrown the OpenBMC layout.
While BMC machines use 128MB SPI NOR chips, we only have 64MB on the EVB
so use a layout that has a smaller region for the ro and rw filesystems.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add fan controllers, regulators, temperature sensors, power supplies
and regulators.
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Rainier contains two NCSI network devices.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Rainier is a new IBM server with POWER host processors and an AST2600
BMC.
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This is an alternate layout used by OpenBMC systems that require more
space on the BMC's flash. In addition to more space for the rootfs, it
supports a larger u-boot and Linux kernel FIT image.
The division of space is as follows:
u-boot + env: 1MB
kernel/FIT: 9MB
rwfs: 86MB
rofs: 32MB
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Change BMC init-ok from GPIO to LED, which needs to blink when BMC
initialization is complete.
Use TAB to align some lines.
Signed-off-by: Chicago Duan <duanzhijia01@inspur.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Enable all the I2C busses on Tacoma and add the I2C slave devices that
exist on the busses.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Everything is the same as G5, except the devices have their own
interrupt now.
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The AST2600 has two VUART devices.
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The AST2600 has 208 normal GPIO pins and 36 1.8V GPIOs.
Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Enable the eMMC controller and limit it to 52MHz to avoid the host
controller reporting bus error conditions.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The maximum divider value for DPLL4 M4 divider appears wrong. For most
OMAP3 family SoCs this is 16, but it is defined as 32, which is maybe
only valid for omap36xx. To avoid any overflows in trying to write this
register, set the max to 16 for all omap3 family, except omap36xx. For
omap36xx the maximum is set to 31, as it appears value 32 is not working
properly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
All boards using rk3288-veyron-analog-audio.dtsi have HDMI audio.
Specify the support of HDMI audio on machine driver using
rockchip,hdmi-codec property so machine driver creates HDMI audio device.
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Link: https://lore.kernel.org/r/20191028071930.145899-6-cychiang@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Looks like omap3 RNG is similar to the omap2 rng, let's get it working
by configring the dts node for it.
We must also add rng_ick to core_l4_clkdm as noted by Adam Ford.
And please note that the RNG is likely disabled on HS devices. At least
n900 does not have it accessible, and instead omap3-rom-rng driver must
be used. So let's tag RNG as disabled on n900 as noted by Pali Rohár
<pali.rohar@gmail.com>.
On am3517 at least the clocks need to be configured to get it working
as noted by Adam Ford, so let's tag it disabled for now.
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Adam Ford <aford173@gmail.com>
Cc: Pali Rohár <pali.rohar@gmail.com>
Cc: Sebastian Reichel <sre@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Adam Ford <aford173@gmail.com> #logicpd-torpedo-37xx-devkit
Signed-off-by: Tony Lindgren <tony@atomide.com>
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on
Cardhu A04.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Set minimum and maximum voltages, and couple CPU/CORE regulators.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available
now on TrimSlice.
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Utilize common Tegra20 CPU OPP table. CPU DVFS is available now on
AC100.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Set minimum and maximum voltages, and couple CPU/CORE/RTC regulators.
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary for them.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary, like for example
in a case of tegra20-trimslice which is outlet-powered device.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add timings for RAM codes 4 and 6 and a timing for 528mHz of RAM code 1,
which was missed due to the clock driver bug that is fixed now in all of
stable kernels.
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
