Commit Graph

5175 Commits

Author SHA1 Message Date
Lorenzo Pieralisi
f1e209b7f8 ARM64: Implement pci_remap_cfgspace() interface
The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and
Posting") defines rules for PCI configuration space transactions ordering
and posting, that state that configuration writes are non-posted
transactions.

This rule is reinforced by the ARM v8 architecture reference manual (issue
A.k, Early Write Acknowledgment) that explicitly recommends that No Early
Write Acknowledgment attribute should be used to map PCI configuration
(write) transactions.

Current ioremap interface on ARM64 implements mapping functions where the
Early Write Acknowledgment hint is enabled, so they cannot be used to map
PCI configuration space in a PCI specs compliant way.

Implement an ARM64 specific pci_remap_cfgspace() interface that allows to
map PCI config region with nGnRnE attributes, providing a remap function
that complies with PCI specifications and the ARMv8 architecture reference
manual recommendations.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
2017-04-24 13:53:13 -05:00
Viresh Kumar
684c581f10 arm64: dts: exynos: Use - instead of @ for DT OPP entries
Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property

Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.

Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[k.kozlowski: Split patch per ARM and ARM64]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-04-24 20:19:32 +02:00
Marc Zyngier
9842119a23 arm64: Add CNTFRQ_EL0 trap handler
We now trap accesses to CNTVCT_EL0 when the counter is broken
enough to require the kernel to mediate the access. But it
turns out that some existing userspace (such as OpenMPI) do
probe for the counter frequency, leading to an UNDEF exception
as CNTVCT_EL0 and CNTFRQ_EL0 share the same control bit.

The fix is to handle the exception the same way we do for CNTVCT_EL0.

Fixes: a86bd139f2 ("arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled")
Reported-by: Hanjun Guo <guohanjun@huawei.com>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-24 12:22:25 +01:00
Herbert Xu
899f35fabe Revert "crypto: arm64/sha - Add constant operand modifier to ASM_EXPORT"
This reverts commit 42ae2922a6.  It
causes a regression with older versions of gcc.  The consensus is
that this should instead be fixed in clang.

Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24 16:09:50 +08:00
Viresh Kumar
6a611d149a ARM: dts: exynos: Use - instead of @ for DT OPP entries
Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property

Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.

Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[k.kozlowski: Split patch per ARM and ARM64]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-04-20 18:06:03 +02:00
Hoegeun Kwon
019e7db8f3 arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
This patch adds the panel device tree node for s6e3hf2 display
controller to TM2e dts.

Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-04-20 18:00:55 +02:00
David S. Miller
7b9f6da175 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
A function in kernel/bpf/syscall.c which got a bug fix in 'net'
was moved to kernel/bpf/verifier.c in 'net-next'.

Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-20 10:35:33 -04:00
Sricharan R
b913efe78a arm64: dma-mapping: Remove the notifier trick to handle early setting of dma_ops
With arch_setup_dma_ops now being called late during device's probe after
the device's iommu is probed, the notifier trick required to handle the
early setup of dma_ops before the iommu group gets created is not
required. So removing the notifier's here.

Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
[rm: clean up even more]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-04-20 16:31:08 +02:00
David Woodhouse
f719582435 PCI: Add pci_mmap_resource_range() and use it for ARM64
Starting to leave behind the legacy of the pci_mmap_page_range() interface
which takes "user-visible" BAR addresses.  This takes just the resource and
offset.

For now, both APIs coexist and depending on the platform, one is
implemented as a wrapper around the other.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-20 08:47:47 -05:00
Fu Wei
5f1ae4ebe5 acpi/arm64: Add GTDT table parse driver
This patch adds support for parsing arch timer info in GTDT,
provides some kernel APIs to parse all the PPIs and
always-on info in GTDT and export them.

By this driver, we can simplify arm_arch_timer drivers, and
separate the ACPI GTDT knowledge from it.

Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
2017-04-19 16:11:49 +01:00
Olof Johansson
98e53cfaf7 mvebu defconfig64 for 4.12 (part 2)
Select two new drivers  for ARM64 mvebu SoCs:
  - Xenon SDHCI controller on Armada 37xx and Armada 7K/8K
  - Safexcel crypto engine on Armada 7K/8K
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWO+j/yMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71SnoAJ9r0d9MIBvq
 3TWmgUDmImgaucJ5HACggm9+Jqh/GgXTBlxFnszhN9/BuCM=
 =Le5K
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-defconfig64-4.12-2' of git://git.infradead.org/linux-mvebu into next/arm64

mvebu defconfig64 for 4.12 (part 2)

Select two new drivers  for ARM64 mvebu SoCs:
 - Xenon SDHCI controller on Armada 37xx and Armada 7K/8K
 - Safexcel crypto engine on Armada 7K/8K

* tag 'mvebu-defconfig64-4.12-2' of git://git.infradead.org/linux-mvebu:
  arm64: defconfig: enable the Safexcel crypto engine as a module
  arm64: configs: enable SDHCI driver for Xenon

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 07:07:50 -07:00
Olof Johansson
dd726fcb6b Samsung ARM64 update for v4.12:
1. Exynos power management drivers support now ARMv8 SoC - Exynos5433 - so
    select them in ARCH_EXYNOS.
 2. Enable few Exynos drivers for supported ARMv8 SoCs.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY6OrIAAoJEME3ZuaGi4PXqGEP/AketlP7sWJncRV8GU5ynsfL
 0hRfK1Nsiku9ngHn86PaRXKIEhxSo7zl3ruqNwWu8CIzfpVjZxsXe9qXxirEDtLq
 yoDb3TuNfhPJoLRhw+B1zPjl3MuI1OCX2lBE4xr4p5yMajEuzYoMDNob5z/Faxaa
 BQq/IOMtBxKhEe5LDU0Vzjl0cltgsx6issu5hVtdAgdPPC24WaNmV74rdDeUt6+y
 9gUwxcmIj08DjExvKXILBCNUmFIcvHPLcWzcAcquDPMwRP2u1sd4M/S2W+Zr3rad
 PpJ98VTbwvUOyzrLRXvgpq/DzQwdKAPnrucu5JjMY3GIzZaCffcC7MHrzTGGRePn
 W8LHkcpX/K2OYYBZZCRpUF9+PnNOdQp+SmS/bOe0kg6+Cv1NrOHi1hsverNcHCDs
 ZiS0Z6ag8SaRpbUW6xNPjWFexAvV4zecxh2N7ojy1AKxYnbEPojjsot/6moudiuF
 HahOG38/aiEmUUs3jBbgFfEtzrUTuAP1c2aeBNil5cwTQQ9v9ihZJ8jaDI9if6je
 iIk8A9VsB712bkFUfXm0lRB09keHOi662rSS0KvFANp4athxj6faFdLd4wsrkyWQ
 nA/jAB3nQ30mD+MJx3MSN+AZci+zx+pmh/Wo8ehXTQKkQS0DJaSW6OWqo/Gpv59G
 MuUj9PBf9IEArewadSWo
 =lXKo
 -----END PGP SIGNATURE-----

Merge tag 'samsung-soc64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64

Samsung ARM64 update for v4.12:
1. Exynos power management drivers support now ARMv8 SoC - Exynos5433 - so
   select them in ARCH_EXYNOS.
2. Enable few Exynos drivers for supported ARMv8 SoCs.

* tag 'samsung-soc64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: defconfig: Enable video, DRM and LPASS drivers for Exynos5433 and Exynos7
  arm64: exynos: Enable Exynos PMU and PM domains drivers

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:59:38 -07:00
Olof Johansson
d0815dfd91 mvebu dt64 for 4.12 (part 2)
- crypto engine description for the Armada 7k/8k SoCs and the boards
   using it
 - SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards
   using it
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWO+ljCMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71Q9dAJ4i+PBERM8X
 wh0AI0kekOBF33L4YQCcDr5wYXQdCYgwnTBVYadOHvce61A=
 =zSnq
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu dt64 for 4.12 (part 2)

- crypto engine description for the Armada 7k/8k SoCs and the boards
  using it
- SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards
  using it

* tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu:
  arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
  arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
  arm64: marvell: dts: add crypto engine description for 7k/8k
  arm64: dts: marvell: add sdhci support for Armada 7K/8K
  arm64: dts: marvell: add eMMC support for Armada 37xx

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:33:26 -07:00
Olof Johansson
08fd8c9567 ARM64: DT: Hisilicon SoC DT updates for 4.12
- Reset the hi6220 mmc hosts to avoid hang
 - Add the binding for the hi3798cv200 SoC and the poplar board
 - Add basic dts files to support the hi3798cv200 poplar board
 - Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
 - Add driver strength MACRO for the hi3660 SoC
 - Add the pinctrl dtsi file for hikey960 board to configure the pins
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJY66cBAAoJEAvIV27ZiWZcSAAP/3qvcWDNVwc7Rg5JIcbvBP09
 mBbcutrHmFVi5Swd3yuTyNErRFliVsdDV3dwanxlXOojqYgE4WpJQFKtXr8obQUa
 q3yk+gzMIS3+P18dJPU+SFsCwLDaUF4PkiRm3vd4Oc6fgPfqCbWfYcS6jOhbBdzD
 GWAMp6j/vn3Br3RSFe2NgH43kv2H4efEh0lrKj3wk2mCDF3s69PaMGPLgCfeV1F0
 pYwyO/2v4TWuJkO8U7g1XyvK6LRO49mWDKdqhP0hZpr3DJP7T5u9E4bxScBwG2GY
 ENURvZpl3Kd1thfR9+7FkwNg0Z7Y9hVNI5763JzLusd6pw1y2jDU9oEESpuVi1FH
 9dwqloiLuonYSPvAM9XS84CXnguFoqjndf7Z3d9yliS86GRn4g5B5t20rlLtSE+4
 o+IcLQy6z6CpDHugTzav3oBsscckEiWsmX0X6Jym23+buzFcHWOPOQldIUUSDDoq
 9oct1AxBrQA9F9KspaiWRy38Bwi8qRT5FT+BfBai3y45FeEKdRFUghIwdeqm4F2v
 1JulIiPelHUtELAcAEJFRVQzgfSVuGuXCAHVHpgXE018UnNvhfl3/VtUtvLI71wf
 jukY2JIJsG9r/NHR1uZU8LGN70bNUjHXwuF0R/zh2zwZT+mDgxEe5zOlCbQyYJbt
 uqVy7+asSKcbOLabW/Ae
 =5zO6
 -----END PGP SIGNATURE-----

Merge tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi into next/dt64

ARM64: DT: Hisilicon SoC DT updates for 4.12

- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins

* tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
  arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
  arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
  arm64: dts: hisi: add SAS nodes for the hip07 SoC
  arm64: dts: hisi: add RoCE nodes for the hip07 SoC
  arm64: dts: hisi: add network related nodes for the hip07 SoC
  arm64: dts: hisi: add mbigen nodes for the hip07 SoC
  arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
  dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
  arm64: dts: hi6220: Reset the mmc hosts

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:33:20 -07:00
Olof Johansson
b42f45558e ZTE arm64 device tree updates for 4.12:
- Add mmc devices for ZX296718 SoC and enable those available on
    zx296718-evb board.
  - Add VOU controller device, output devices HDMI and TVENC, and enable
    display support for zx296718-evb board.
  - Remove pll_vga clock from ZX296718 device tree, as it's not a fixed
    rate clock.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJY66HJAAoJEFBXWFqHsHzOUREH/RADjsUVP/5Jb1Dqs9FghOzK
 DxIsFEc6TaeeDEzBA8p2jnd4xUi0vBSuJJw77QS/tYLt0eB+ermqw5MFYHknMyOY
 OeDUx15fnC0n9WSkC4IFqlGXCnBuibcxjILSLwzsZ4jdVnvZtJ0nFAEckOpqeRDj
 N9byLnK8fDZhlMP1A/opZhL51WKRSL/ImkqguoC5+Mm+/Lq2OuTtQukobfVHlTjc
 lePX5uTPAujXoA9olHn0oliTPA/BDV9+ZWId4tqBSYxdJ06w0KqRiCk8xW04d1qF
 BXEVOv4jo5HdTDa0ikUBcvvn0vD4RqZR6Wo/1I88nHY4mNJKF4ibqlMguL1mueA=
 =d5as
 -----END PGP SIGNATURE-----

Merge tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

ZTE arm64 device tree updates for 4.12:
 - Add mmc devices for ZX296718 SoC and enable those available on
   zx296718-evb board.
 - Add VOU controller device, output devices HDMI and TVENC, and enable
   display support for zx296718-evb board.
 - Remove pll_vga clock from ZX296718 device tree, as it's not a fixed
   rate clock.

* tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: zte: add tvenc device for zx296718
  arm64: dts: zte: add vou and hdmi devices for zx296718
  arm64: dts: zte: add mmc devices for zx296718
  arm64: dts: zte: remove zx296718 pll_vga clock

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:33:14 -07:00
Olof Johansson
13ed63b6cb Freescale arm64 device tree updates for 4.12:
- Add support of LS2088A SoC, which is a derivative of existing
    LS2080A SoC, and the major difference is on ARM cores.
  - Add support of LS1088A SoC which includes eight Cortex-A53 cores
    with 32 KB L1 D-cache and I-cache respectively.
  - Add crypto and thermal device support for LS1012A platform.
  - Add ECC register region for SATA device on LS1012A, LS1043A and
    LS1046A platforms.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJY649rAAoJEFBXWFqHsHzO3O4H/Ry5BxyUsrIziFCMNv05chEw
 /C5AJVGGHyZTc2q/nGeR+wkDXhB7p7xX9D4Fzl+lAss58J20yB403dbrc5r2cmPk
 aataxt1q4wfH9KekGlEqkolkQrMPRb7i+j36xpjVUCeFww8C8rszFC3CJwcTLFX8
 pdhykfIpKz/Osy1hWH4Nt9Ss3L+8DhmQGh1bueriggQ5f/MPkhZUk7goK4j8mlC+
 i5oWcO6wWvTXg1HTW+PbtBFJWqQ7ztb0qHSikoJ8yWtIkzehlcgrO7qkdf8hI8pV
 gj48OMrvS4b/aYsAKmfVGCDpNqedoJDVbPRXkES8/z1avkKUmGLnhr9Ftdw7saA=
 =BYDv
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

Freescale arm64 device tree updates for 4.12:
 - Add support of LS2088A SoC, which is a derivative of existing
   LS2080A SoC, and the major difference is on ARM cores.
 - Add support of LS1088A SoC which includes eight Cortex-A53 cores
   with 32 KB L1 D-cache and I-cache respectively.
 - Add crypto and thermal device support for LS1012A platform.
 - Add ECC register region for SATA device on LS1012A, LS1043A and
   LS1046A platforms.

* tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards
  dt-bindings: clockgen: Add compatible string for LS1088A
  arm64: dts: Add support for FSL's LS1088A SoC
  arm64: dts: ls1012a: add crypto node
  arm64: dts: ls1012a: add thermal monitor node
  arm64: dts: updated sata node on ls1012a platform
  arm64: dts: added ecc register address to sata node on ls1046a
  arm64: dts: added ecc register address to sata node on ls1043a
  arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC
  arm64: dts: freescale: ls2080a: Split devicetree for code resuability
  dt-bindings: Add compatible for LS2088A QDS and RDB board

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:33:08 -07:00
Olof Johansson
ab719074fa Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the
default memory definition on the px5 eval board. While the bootloader
 should already override it with the actual amount, it's better to not
 carry around wrong values.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljpQgUQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgSriCACyesU9O1mz0CHWArxHY1O4UJ8SYdZqotOv
 Q8XVWA7H9wrLMazyauHDGxZ63PbSMuhkOzpbUwBl6BEgUtVtr2j0c8JgvLk7IAqS
 07ggX/7cYoqCLB8CKqkgdGKYjWIVwkGm0zL7lBwtlF6WnTl92B+gHEll8sv8R7ua
 EO1Biq+o/XZrmsBoBBWtnaJdZYAcIMEU3qRtI4mInvOHkDCEvW0kaKuPT9A2h75j
 7Asgpn0Na3sqX3UPAk5F1+YCEV40aZ10qPV1HurKL1E61HepDWs3rjymyXh0H12q
 B9yzOGPfxdoU21rCAu1HtMu4ujo5ppvKRajeE4nyag92TTuP2lu4
 =tcTl
 -----END PGP SIGNATURE-----

Merge tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the
default memory definition on the px5 eval board. While the bootloader
should already override it with the actual amount, it's better to not
carry around wrong values.

* tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
  arm64: dts: rockchip: add RK3328 eavluation board devicetree
  dt-bindings: document rockchip rk3328-evb board
  arm64: dts: rockchip: add core dtsi file for RK3328 SoCs
  dt-bindings: add binding for rk3328-grf

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:33:03 -07:00
Olof Johansson
eeef69c9eb Samsung DeviceTree ARM64 update for v4.12:
1. Add IR, touchscreen and panel to TM2/TM2E boards.
 2. Add proper clock frequency properties to DSI nodes.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY6OyZAAoJEME3ZuaGi4PXMTUP/RErX9qqM49S4ygyFqgMcDy7
 i7Zbkgxl9MfNOzzRLRUD9POsI7VjdCvOks1AWV6RMw1TOKHEjF/ChRsFoZBaneZu
 UKSybe50sB+Xqok4Wo1RN+FRo9tVaOtOlPdQguR1f9salR40/eg6XC4tTdbsjzSE
 m74+pnUdZuGTvXwkwrdXShKYgk0Z5fsBlM3QhOnG1XXfs+A/1yzpxDuDapB4WU/K
 s+z2dQ7VtA5SaoAhpAwuejdlu41W7NkYVSp3Ejoc4eZiIqPQuzv7djb0uT6K+SPh
 Wmq4m2UQX3UWU48aDHdFoEeS03mX0ILNZAuDOiW2ZrAmXUVIXwh94VVjp0j3pNGB
 fda1mRGk85jZBBenAi0BIhqVYmK1oBRTpOHQpgriGM6SOcJMUhLCeQBcL6fJ+/hu
 x1kI6+6bgC5s5lPeYGk/k+XFF6No1pbc6g4UAG/BlWQ8A9g5Uu5ZsvY9cIxHxEtx
 2AAXWJ7uLpztxuAryENRVHiiMY7w+FJBXuNbtSW9TYQx3lsVjmEsyiDHaMIVy6V8
 r/cuKPtcj0/pDNY1lg4N0DpjPZpISx66viFIzfM5Fg6fiLRtNurzuUCbDj75Xckl
 Nx9vrxpgBFfwU4q++HItB2n8HykewusCC3TCs8YNOeHs1yRUvhlEwVswGqtNoKuc
 5uGMtR4P0EqhwmU4AMXd
 =kk6u
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64

Samsung DeviceTree ARM64 update for v4.12:
1. Add IR, touchscreen and panel to TM2/TM2E boards.
2. Add proper clock frequency properties to DSI nodes.

* tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Add the burst and esc clock frequency properties to DSI node
  arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 board
  arm64: dts: exynos: Add stmfts touchscreen node for TM2 and TM2E
  arm64: dts: exynos: Enable ir-spi in the TM2 and TM2E boards

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:32:57 -07:00
Olof Johansson
c3acc32d6f Second Round of Renesas ARM64 Based SoC DT Updates for v4.12
Corrections:
 * r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC
 
 Cleanup:
 * Drop _clk suffix from X12 clock node name for r8a7795 SoC
 
 Enhancements:
 * Add reset control properties for r8a779[56]
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJY569jAAoJENfPZGlqN0++4kIP/isnugtJf5N1dRc82mxIDd3e
 8wAKOI3+gXK6dQPr5HP6nD7YgUWWgj+SKX8G8d/VRxWkBHKVdOBmSq6h/nkY2hg6
 XcnbRu+dIB2fthXW4vdvnj1j5gIz1b0Y8aXL5cZSX+5nxeZPfdiZt0n7YSKU2Bg5
 wlHXUWhkXYDZfz9wqRmqU2mjkbh5dwqHHYMLcrwazVhvS68XdJvAwUKzrtCfndKv
 n727ypPZP5QX569r4Ub1AtY3J3y4F4aMl7eWbh8ZxTJoMYrtLhmq7gms1thmTp77
 xVeHFHCDEThREY7NgubisI9oyVEssqkB/8cDbCo6IPvDNNuJ1M5FAfAHNcBQ+2Wg
 3PiKDoVXkBL7zuQIl0JjiWPEBKWZkEnictXX+1CsgHZPLnQFAKncYilpvX3jz+Gq
 2eETERdgNbx5pEej/mZsyLVFe6TQ5GoSz74YQQkS4KajfIGZmYAgUXL0sIlo3MKi
 X1jhQy4Ux41nG+arJPYyx8R+Db9qrDhs43npfe+y5i9D/JbIxASDE4J0RypU993x
 H6SEUMDoEG+1dcR4Ez7rCeWm8CG9eVDks0oMZlRaOXbqvPBsy43YvuiYdTEE3x+X
 HSJubtalb1pDqe4Fi0DmuOU/2kQf74/mBmD971sjBNupT61e4Q3rW8bwz5pO+45Y
 lgLStN9v8ptgyMr+hU4o
 =HWqJ
 -----END PGP SIGNATURE-----

Merge tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Second Round of Renesas ARM64 Based SoC DT Updates for v4.12

Corrections:
* r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC

Cleanup:
* Drop _clk suffix from X12 clock node name for r8a7795 SoC

Enhancements:
* Add reset control properties for r8a779[56]

* tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name
  arm64: dts: r8a7796: Add reset control properties
  arm64: dts: r8a7795: Add reset control properties
  arm64: dts: r8a7795: Correct SATA device size to 2MiB

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:32:49 -07:00
Olof Johansson
f6b71673e1 Qualcomm ARM64 Updates for v4.12
* Fixup MSM8996 SMP2P and add ADSP PIL / SLPI SMP2P node
 * Replace PMU compatible w/ A53 specific one
 * Add APQ8016 ramoops
 * Update MSM8916 hexagon node
 * Add PM8994 RTC
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJY5tYFAAoJEFKiBbHx2RXVmmcP/12qDv1XsywbDo0ib3Elnjbe
 lRRBG1WCK8II+ludg9eXgeADkzYlCWJ3lPxux95BHvwFpDmd1I6gD7E6a8d6NBRs
 FOmyf9+3QHGEI8jUqr/1oNDXQRhEj7UiHtN4Hrr3kZIjE7sjsfKr+ZvCXly38IIE
 vQTN3KdwnOSZm/KgyU13BdtphFfogRxtxzbiBKGN3sMRqHtfRndnqDOxWrpOYTZM
 IQjxf0xZdHhDOXGRgXNHa7ljdQ/gmhBYOdYBaj6KJV+pgWiF2i/zaxt8tejPXoxV
 +jl2uIF3iWjVDL7fg71q0wdoQ9p3mCXA0zcvB+rvFGWawDanh+Rgv5PqyYNv96gH
 6C6LBajKGDxBn72HJ/GjcxpZldLhz2x9gdG0IPVVgRLha2Sj49RQn5tjTKEzF7AW
 zkYBU+2LUmIe4Ns1PfFeDqtE0k+kyKvUoQhH6cHUt5ePmtVErJpRog52BRxdbRtd
 Xke3DYXjVdrS097qMmISxC6O1BDFMEhc18+exaFOhcuDhBxze7vx72b2n9K6Dcl9
 HuA3TmGH8RsFcB8rXhumHbgc3vtZ7ohIuRLMnFx5WoDIb+w8j2Q1qe5XuIFicxYF
 nr4+/bDKwmWwjqvoAm5cCTaCQFxUrisj39sCPWXihMaTUcIC7Vc5BO0TOiqyKdUo
 QrTpACwrFYStYzBbFHzj
 =3+wW
 -----END PGP SIGNATURE-----

Merge tag 'qcom-arm64-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64

Qualcomm ARM64 Updates for v4.12

* Fixup MSM8996 SMP2P and add ADSP PIL / SLPI SMP2P node
* Replace PMU compatible w/ A53 specific one
* Add APQ8016 ramoops
* Update MSM8916 hexagon node
* Add PM8994 RTC

* tag 'qcom-arm64-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  arm64: dts: msm8996: Add ADSP PIL node
  arm64: dts: qcom: pm8994: Add rtc node
  arm64: dts: apq8016-sbc: Add ramoops
  arm64: dts: qcom: msm8916: Update hexagon node
  arm64: dts: msm8996: Add SLPI SMP2P dt node.
  arm64: dts: qcom: Replace PMU compatible with a53 specific one
  arm64: dts: qcom: msm8996: Fixup smp2p node

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:32:42 -07:00
Olof Johansson
3d3949df4e arm64: tegra: Device tree changes for v4.12-rc1
This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
 SDHCI and GPIO. It also enables various features on the P2771 devkit.
 
 A small fix is made to the compatible string list for the flow
 controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljmyEETHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zof6+D/4q3/aatnXbrQ+nYvcXdSYq+ISOaCEA
 Ll23ePKJvTiPGE1+rIy64NyljAdiSFhul6PCFumCaX39J7QoOgY5AE3DvOgx/xEh
 RhAqRxlq04rYqTqlNovwgbV0XI8TDYAnuelGrRp6f6gC8J2EqReFIWG9P+11MYcD
 Zim6Xzyl42v0u//3oy/JOhE0iEK1/Mv35Wv8VTxHFsh+TMhhm2M+vAFDgFeVv6q0
 863ooxrw935FbAR6LRm6cIiyF1EknQ5z7LgDnJVHFke/nAggcItldkgRqijA4C8c
 ctJTvigOIZmhoCfF6Jh5fAuPCqhxsvZAoC5h8kWKmqw7tDS4Aysaf8cZDo034yrO
 y6HC632iqP3UvNj5WMTExBC4FFwHx6wp/ESdYsxih00F0/hOPsObeorUiQ2DJkjc
 0XMWKEXuBWzyRYYFSY1zgs9rq0nmqlX/TL6+Lrz1FPzgMWXFvt9B2cCnssDGa7U6
 uzKezAbU8eTg5muawYnStttJROdxbHBaDbRNVkvbtYUV2mYfmfAqVD5RjrssYerD
 cLoIU0jgjZa0wk1D0JUX6quT0rvRpmGo013G6Luk01D1jG2udTkNXIexyBtndJmr
 ZEuzfRLAAdDo7OpirgcWxpja4m/17Dp/LnLg1tzksHk3UxnrFD83Hrtpgif+ci8x
 +t8oScJqGFhgiQ==
 =yRy3
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64

arm64: tegra: Device tree changes for v4.12-rc1

This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
SDHCI and GPIO. It also enables various features on the P2771 devkit.

A small fix is made to the compatible string list for the flow
controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.

* tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Update the Tegra132 flowctrl compatible string
  arm64: tegra: Add GPU node for Tegra186
  arm64: tegra: Enable IOMMU for host1x on Tegra210
  arm64: tegra: Enable VIC on Tegra210
  arm64: tegra: Add GPIO expanders on P2771
  arm64: tegra: Add power monitors on P2771
  arm64: tegra: Add GPIO keys on P2771
  arm64: tegra: Enable current monitors on P3310
  arm64: tegra: Enable SD/MMC slot on P2771
  arm64: tegra: Enable SDHCI controllers on P3110
  arm64: tegra: Add initial power tree for P3310
  arm64: tegra: Enable ethernet on P3310
  arm64: tegra: Enable I2C controllers on P3310
  arm64: tegra: Invert the PMC interrupt on P3310
  arm64: tegra: Add ethernet support for Tegra186
  arm64: tegra: Add PMC controller on Tegra186

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 06:32:35 -07:00
Olof Johansson
2149ed8d6f Allwinner H5 DT changes for 4.12
H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
 be usable on the arm64 H5 DTSI, that shares almost everything with the H3
 but the CPU cores.
 
 We then have patches to support the H5 boards on top.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY5guIAAoJEBx+YmzsjxAgCOAP/izjrX7AD/lxwAQ1BtfIuNcK
 rSpQ4TjF7hO1r0pN1XoIs538U5uYWiBPhpoL+bxu9cdv33i1jojM6MFMAGfyWES4
 bjEHU/dI6zBGeJ/icwSEjP1Wl6N+h6eZwzJ01VQsdc91RZXXqgT2xCVXGIJDtuTw
 H/+iwvpF6ZqyTFXzhhx8YH7Aqn0X9+nuy6WALyr7d4awa7uLw0QL54Lr3gJWaGvm
 Si/o8SjZU6pLF3KyDlcOwlDem+YD6ghH+eZXa1323xoctPQRuFZTiinnolhxJWFc
 w+yhK6PtfR8CJ/WlfEEtMjjYQxeefr6MCQjaPjrY67YwE61PlcOZADAB77DujZ/2
 Na47Olqp7vJ1yg19X5W/GlxfWa9P0H0VuRE8ZPMfZXGIHFBTgjHuE+pGds38IDvd
 Zr0z/fX9WjTUDK9qFD9JHDL9FAJo7gjNGMMMiUvEjR8xpTJhhmAeAzpgZj+Aa78f
 ZOYzu8J1xYf2yT/Xj/lDz7FHcWJEc89go9fX+lc8ILaFcXYvokqjfGnD6+ODf0FW
 sO54p1OhjEt8yIEnH2js9C+YCIsuMeZ6e6fHjfp/uVVLPb94fhXKSQGYKRmXPJkK
 gEdd2OS+I+diM0BAd2mKRlr57mEoPtkl07yx2E2eqCjIG/8wBN0C76KM9p0yPWof
 YAaV+iAHOdsvT43alrXp
 =ilmt
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64

Allwinner H5 DT changes for 4.12

H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.

We then have patches to support the H5 boards on top.

* tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu
  arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
  arm64: allwinner: h5: add support for the Orange Pi PC 2 board
  arm64: allwinner: h5: add Allwinner H5 .dtsi
  ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
  arm: sun8i: h3: split Allwinner H3 .dtsi
  arm: sun8i: h3: correct the GIC compatible in H3 to gic-400
  arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
  arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 05:39:41 -07:00
Olof Johansson
6929f0f6a4 Allwinner arm64 DT changes for 4.12
Some patches to enable the PRCM block in the A64
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY5gSTAAoJEBx+YmzsjxAguFkQAJkdxquuse8N15nl3E4zbnNs
 SbuJt7eVluQgOs1EZUFxKCFfui0I90jzq0C5QDrmkld/+bF5aRU8YrQLetZc/xwg
 TovxA2NtpgHlXv32/PKQsMNqSx1mFQuZgLlN+O7yL4q1E6mH2qZCHj/xOz40rrBi
 kb3dRKGxJdRt9Hc5l2Sysy8kkQXnGDcn8lA4DuQvTvxDp/TanOKV86VdtMEw6LYR
 4TKqnveXgDe48+5a8RdycgevX35HyULTSMJYIlmWXPtc6YtlL1VgzevGMUCcnGt4
 EocPwh08ot+x2aQXOBVYgstMFG3RhdPq1VeYfZj32LXFDNCXvDXq0/iYE5u0UozM
 m3njtzaQg5FH961NoXbghPwgdsvl2KBR3pjNHMA0LhCDepfIC3I+lDE74o+93kcK
 DyKaA8k48pP1VS+K/vJkYwPuMGkJmfhgOrMRKV2ABFKczy6fCX6K5Hcbv2s7csPA
 /o7EmG5oLKTBc1cfH3EXSi9uqJB533dxWh0xlahZE0m9h0bjHvCdzwEKqVGHUGJ2
 Jz+tSMHNN89v11u6HnzCTJkAXXG5pRTP5khkh6JlI1+E3sOdF0rR0H77fsxjCKXt
 2E4i5jUy92fFU0Gd/Jcbfa6T4wYKzFeAaaNd4DjsvvBDeFUU7933VNWd92buc8A7
 im9JN0pRe+faD28BuJw9
 =5XFn
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-dt64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64

Allwinner arm64 DT changes for 4.12

Some patches to enable the PRCM block in the A64

* tag 'sunxi-dt64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: allwinner: a64: add R_PIO pinctrl node
  arm64: allwinner: a64: add r_ccu node

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 05:37:37 -07:00
Olof Johansson
309ed7e6e4 Allwinner arm64 config changes for 4.12
Two patches to change our Kconfig option and add new options in the
 defconfig.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY5flvAAoJEBx+YmzsjxAgcLsP/105kRbJPtbjll3gYoDHZj12
 OWBxQMW+bNHY0xGqblrpL5gyl5X7+35a+I1Q2R5TQAintS62YFvwJU0Jq5S7ZhPq
 3G2lDGpa2oArOJX63X5ZgY7B9tUuAEzBCLOWtDmS00IMdcH0W7ZzuiJTgpQ9jXQz
 bpvW/GvhooGvnzSmOihhqxLy6D1m6d/tV51+8ecZLULFrqPhKcJ6QuAra/fjiaaH
 yZh/a3i96EJQEJ7Ksn71Z7deBz0tUZpvASjUvpave/ubIOUkD0hEXVm8P7tp13xt
 VmcF+WY6yMmW64qJd/NqRcNBL7aFd8TKvv9siNmasIuLOg/r578mZcr4fKvySH6+
 rGe9yxeQHgx06YjvtM6HKnZjzxRccAlbG4OPD9bdFds5SDBfuO92fCrvzYwIoovs
 OBE6t5KfLd7gAZuQemlaOYyoGft7Iz0rdRYmwUEjzzHQ1ZvL64gXp7ZbBd84kRUr
 B/EDD2LkC9RSST2tshMFnthJy6a8U0dpDagcpsBpLvf2NNhaeibWhvNnn7c4gp4+
 UKtrTOSFAMLU0Sr+nwA5vYAlJgKMFce0NxeBD4f1/TA7NNzVkHv6MGh8ghdjsRDH
 xUH/8LKX6M9zWB13LUxmOlcpzSeWQ63yYxRB1KpDajs5oUvJ7a0j50FIT+s0CWua
 6/FsfcngS7J9uFnmScBh
 =twCP
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-config64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/arm64

Allwinner arm64 config changes for 4.12

Two patches to change our Kconfig option and add new options in the
defconfig.

* tag 'sunxi-config64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: defconfig: add Allwinner USB PHY
  arm64: only select PINCTRL for Allwinner platforms

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 05:32:46 -07:00
Olof Johansson
dd85108475 Amlogic 64-bit DT updates for v4.12
- pinctrl: new pins for audio
 - clocks: more clocks exposed for GFX, audio
 - new board: Khadas Vim (S905X)
 - new board: HwaCom AmazeTV (S905X)
 - ethernet phy: add GPIO resets
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJY5DPWAAoJEFk3GJrT+8ZlieEP/0bGQcMBnjgLIGh49pMDqiUz
 1RAmVBeo/1yeq2WjI8a3VsN5W4fuHysH7DWTxI1GA7f9wVblyMBQTqvg2R8tfEVe
 EAS444Fj6xUzEYmWoBNETHmxWT40o+80B7BYm7zGrRqeQ0QMo7yAWBKHmmJ0nmNv
 qb/dLqTLbldRwh+5gLvgaH1UK2PdsNE+UHWThP6CPXIBe1WIxggmwDt0ItBlO17S
 wnBHjh1jzAroS51WVRc2aL0xmBrHgi20BtVxCg7jbQk6I4zDafk59pu1+Xuwaoiv
 CMWySeQq1wj0uOZ4OtkeTIgd8VuBt8ovcHIB/kpJEmJy8C2d2dkjuBD2IC7Qo3d7
 9p3NfE6E1vZZdT4//8i0sVQMX2OEiVWJfM/2hBlV4OLEQ+RR2U5gvUHBxJcnuC1B
 RHbK/OqZ7GyQZOG5O7OWiF4hG4dOFCCsbkleMcbAlm5BUvLaI6QUTufuQrsNzzvb
 c3dAuLldsNwBvpSqxYr1mKQ2YNh2M47DSgdut8qDaaPYx6LU4HcCZEVTe2q9Hn1h
 46cERmJoVOW40WEjYK/Nv+TpUNKzwF7Bz6fA7dsqb0ehEaHPFWvjD2mpCij60hvc
 J5dxZDQT8Y1lIkOcLRBdXYFp/NOVQoIAwfGSHleoHzclshILvV/O8hevsZpKFTKh
 ywM7owJLUAkDDYLIbNxS
 =/FCW
 -----END PGP SIGNATURE-----

Merge tag 'amlogic-dt64-redo' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64

Amlogic 64-bit DT updates for v4.12
- pinctrl: new pins for audio
- clocks: more clocks exposed for GFX, audio
- new board: Khadas Vim (S905X)
- new board: HwaCom AmazeTV (S905X)
- ethernet phy: add GPIO resets

* tag 'amlogic-dt64-redo' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (41 commits)
  ARM64: dts: meson-gx: Add support for HDMI output
  ARM64: dts: meson-gx: Add shared CMA dma memory pool
  ARM64: dts: meson-gxbb-odroidc2: Enable SARADC node
  dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
  clk: meson-gxbb: Expose GP0 dt-bindings clock id
  clk: meson-gxbb: Add MALI clock IDS
  dt-bindings: clk: gxbb: expose i2s output clock gates
  ARM64: dts: meson-gxl: add spdif output pins
  ARM64: dts: meson-gxl: add i2s output pins
  ARM64: dts: meson-gxbb: add spdif output pins
  ARM64: dts: meson-gxbb: add i2s output pins
  ARM64: dts: meson-gxbb: Add USB Hub GPIO hog
  ARM: dts: meson8b: Add gpio-ranges properties
  ARM: dts: meson8: Add gpio-ranges properties
  ARM64: dts: meson-gxl: Add gpio-ranges properties
  ARM64: dts: meson-gxbb: Add gpio-ranges properties
  ARM64: dts: meson-gx: Add Mali nodes for GXBB and GXL
  ARM64: dts: meson-gxl: Add missing pinctrl pins groups
  ARM64: dts: meson-gx: Prepend GX generic compatible like other nodes
  ARM64: dts: meson-gx: empty line cleanup
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-19 05:29:37 -07:00
Sudeep Holla
f9936c4abf arm64: dts: juno: add information about L1 and L2 caches
Commit a8d4636f96 ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.

Commit 9a802431c5 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.

This patch adds the information about L1 and L2 caches on all variants
of Juno platform.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-04-19 12:16:51 +01:00
Sudeep Holla
72cc19938f arm64: dts: juno: fix few unit address format warnings
This patch fixes the following set of warnings on juno.

 smb@08000000 unit name should not have leading 0s
 sysctl@020000 simple-bus unit address format error, expected "20000"
 apbregs@010000 simple-bus unit address format error, expected "10000"
 mmci@050000 simple-bus unit address format error, expected "50000"
 kmi@060000 simple-bus unit address format error, expected "60000"
 kmi@070000 simple-bus unit address format error, expected "70000"
 wdt@0f0000 simple-bus unit address format error, expected "f0000"

Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-04-19 12:16:31 +01:00
David S. Miller
450cc8cce2 Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
Johan Hedberg says:

====================
pull request: bluetooth-next 2017-04-14

Here's the main batch of Bluetooth & 802.15.4 patches for the 4.12
kernel.

 - Many fixes to 6LoWPAN, in particular for BLE
 - New CA8210 IEEE 802.15.4 device driver (accounting for most of the
   lines of code added in this pull request)
 - Added Nokia Bluetooth (UART) HCI driver
 - Some serdev & TTY changes that are dependencies for the Nokia
   driver (with acks from relevant maintainers and an agreement that
   these come through the bluetooth tree)
 - Support for new Intel Bluetooth device
 - Various other minor cleanups/fixes here and there

Please let me know if there are any issues pulling. Thanks.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-17 15:00:57 -04:00
Al Viro
2611dc1939 Remove compat_sys_getdents64()
Unlike normal compat syscall variants, it is needed only for
biarch architectures that have different alignement requirements for
u64 in 32bit and 64bit ABI *and* have __put_user() that won't handle
a store of 64bit value at 32bit-aligned address.  We used to have one
such (ia64), but its biarch support has been gone since 2010 (after
being broken in 2008, which went unnoticed since nobody had been using
it).

It had escaped removal at the same time only because back in 2004
a patch that switched several syscalls on amd64 from private wrappers to
generic compat ones had switched to use of compat_sys_getdents64(), which
hadn't needed (or used) a compat wrapper on amd64.

Let's bury it - it's at least 7 years overdue.

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2017-04-17 12:52:22 -04:00
Linus Torvalds
7395ca0f91 ARM: SoC fixes
Again, a batch that's been sitting a couple of weeks, mostly because I
 anticipated a bit more material but it didn't show up -- which is good.
 
 These are all your garden variety fixes for ARM platforms. Most visible issue
 fixed here is probably the SMP reset issue on OMAP, the rest are minor stuff.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJY877PAAoJEIwa5zzehBx3TaUQAKtE8CSmvdWIk5grVb4MBDfF
 rXQ2R7WJF17LtVhIGwz9BPCQXMK+/XcSuXZ8bvUIoMsmOFXutDao7m7COD0z4aNo
 CPWk7ceQRzIWvsmturla6aYGmpAbWzdDgQj61LnaFbQrzmJOHVvcJN685+L5NGkZ
 8GBrzNmrvVkWz5N+msnrZRIcKpSqGCXrkjUU1EfHgUgNNdTf6BQRQSzVEYBtILEb
 9bC3WdS1fosmSdbsBjcxHsAtWMyO64KqhA691+gGTR93wyOuCRgqv+/ucoFB1oi+
 yjuhUVHW7Y5/8KOi67+97PwoKpZYpUFHge1/5iPbgEN6SqhOLzPAALGCKT4ONEQz
 KmLl//kX1IJZTD/87OegSLDbpS7h2sRYS7FpwgAa1kyYYOHdsZsECzKfhEvgZNHX
 Gtl2XLmtELM9quKQ2X8xWvjU5grfSLkng9OhDJ6ZCFhGddvjtHegq8J5diFyq281
 qf4n/Gp/OLC9IoPUyZefn5ya77K8UZPNppqtiWTBbT1IuXWbPUVPKmZoCpq3Qwu+
 2fdcFa3sIfpzDg9vkTszFAUCFkRqH5Jzy8BfNIQtfSq+pxwyIRWh88a5CV2RvYFB
 uHSt5B88YR2PwoyhV2oFpYNkx3vVu9g+A35ClzIRTLhSMi+Ngh2+DcppHY+LficP
 m9Hes98dZOv92JgiSaoQ
 =C+Hz
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "Again, a batch that's been sitting a couple of weeks, mostly because
  I anticipated a bit more material but it didn't show up -- which is
  good.

  These are all your garden variety fixes for ARM platforms.

  The most visible issue fixed here is probably the SMP reset issue on
  OMAP, the rest are minor stuff"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm64: allwinner: a64: add pmu0 regs for USB PHY
  ARM: OMAP2+: omap_device: Sync omap_device and pm_runtime after probe defer
  reset: add exported __reset_control_get, return NULL if optional
  ARM: orion5x: only call into phylib when available
  ARM: omap2+: Revert omap-smp.c changes resetting CPU1 during boot
  ARM: dts: am335x-evmsk: adjust mmc2 param to allow suspend
  ARM: dts: ti: fix PCI bus dtc warnings
  ARM: dts: am335x-baltos: disable EEE for Atheros 8035 PHY
  ARM: dts: OMAP3: Fix MFG ID EEPROM
  ARM: sun8i: a33: add operating-points-v2 property to all nodes
  ARM: sun8i: a33: remove highest OPP to fix CPU crashes
2017-04-16 12:38:17 -07:00
Rob Herring
019aa56b7d arm64: dts: hikey: add WL1835 Bluetooth device node
This adds the serial slave device for the WL1835 Bluetooth interface.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
2017-04-13 19:22:53 +02:00
Antoine Tenart
10ebb57ffc arm64: defconfig: enable the Safexcel crypto engine as a module
The Safexcel EIP197 cryptographic engine is used on some Marvell SoCs,
such as Armada 7040 and Armada 8040. Enable this driver as a module in
the ARM64 defconfig.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-12 15:35:16 +02:00
Gregory CLEMENT
a1485f5a91 arm64: configs: enable SDHCI driver for Xenon
This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-12 15:35:11 +02:00
Catalin Marinas
494bc3cd3d Merge branch 'will/for-next/perf' into for-next/core
* will/for-next/perf:
  arm64: pmuv3: use arm_pmu ACPI framework
  arm64: pmuv3: handle !PMUv3 when probing
  drivers/perf: arm_pmu: add ACPI framework
  arm64: add function to get a cpu's MADT GICC table
  drivers/perf: arm_pmu: split out platform device probe logic
  drivers/perf: arm_pmu: move irq request/free into probe
  drivers/perf: arm_pmu: split cpu-local irq request/free
  drivers/perf: arm_pmu: rename irq request/free functions
  drivers/perf: arm_pmu: handle no platform_device
  drivers/perf: arm_pmu: simplify cpu_pmu_request_irqs()
  drivers/perf: arm_pmu: factor out pmu registration
  drivers/perf: arm_pmu: fold init into alloc
  drivers/perf: arm_pmu: define armpmu_init_fn
  drivers/perf: arm_pmu: remove pointless PMU disabling
  perf: qcom: Add L3 cache PMU driver
  drivers/perf: arm_pmu: split irq request from enable
  drivers/perf: arm_pmu: manage interrupts per-cpu
  drivers/perf: arm_pmu: rework per-cpu allocation
  MAINTAINERS: Add file patterns for perf device tree bindings
2017-04-12 10:41:50 +01:00
Marc Zyngier
d91750f12c arm64: Silence spurious kbuild warning on menuconfig
Since bbb56c2722 ("arm64: Add detection code for broken .inst support
in binutils"), running any make target that doesn't involve the cross
compiler results in a spurious warning:

$ make ARCH=arm64 menuconfig
arch/arm64/Makefile:43: Detected assembler with broken .inst; disassembly will be unreliable

while

$ make ARCH=arm64 CROSS_COMPILE=aarch64-arm-linux- menuconfig

is silent (assuming your compiler is not affected). That's because
the code that tests for the workaround is always run, irrespective
of the current configuration being available or not.

An easy fix is to make the detection conditional on CONFIG_ARM64
being defined, which is only the case when actually building
something.

Fixes: bbb56c2722 ("arm64: Add detection code for broken .inst support in binutils")
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-12 09:48:03 +01:00
Antoine Tenart
7ba2ef7c72 arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
Enable the cryptographic engine available in the CP110 master on the
Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we
do not support multiple cryptographic engines yet.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-12 10:36:30 +02:00
Antoine Tenart
16a51e3485 arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
Enable the cryptographic engine available in the CP110 master on the
Armada 7040 DB.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-12 10:36:21 +02:00
Antoine Tenart
973020fd94 arm64: marvell: dts: add crypto engine description for 7k/8k
Add the description of the crypto engine hardware block for the Marvell
Armada 7k and Armada 8k processors; for both the CP110 slave and master.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-12 10:34:07 +02:00
Mark Rutland
f00fa5f416 arm64: pmuv3: use arm_pmu ACPI framework
Now that we have a framework to handle the ACPI bits, make the PMUv3
code use this. The framework is a little different to what was
originally envisaged, and we can drop some unused support code in the
process of moving over to it.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
[will: make armv8_pmu_driver_init static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-04-11 16:29:54 +01:00
Mark Rutland
f1b36dcb5c arm64: pmuv3: handle !PMUv3 when probing
When probing via ACPI, we won't know up-front whether a CPU has a PMUv3
compatible PMU. Thus we need to consult ID registers during probe time.

This patch updates our PMUv3 probing code to test for the presence of
PMUv3 functionality before touching an PMUv3-specific registers, and
before updating the struct arm_pmu with PMUv3 data.

When a PMUv3-compatible PMU is not present, probing will return -ENODEV.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-04-11 16:29:54 +01:00
Mark Rutland
e0013aed48 arm64: add function to get a cpu's MADT GICC table
Currently the ACPI parking protocol code needs to parse each CPU's MADT
GICC table to extract the mailbox address and so on. Each time we parse
a GICC table, we call back to the parking protocol code to parse it.

This has been fine so far, but we're about to have more code that needs
to extract data from the GICC tables, and adding a callback for each
user is going to get unwieldy.

Instead, this patch ensures that we stash a copy of each CPU's GICC
table at boot time, such that anything needing to parse it can later
request it. This will allow for other parsers of GICC, and for
simplification to the ACPI parking protocol code. Note that we must
store a copy, rather than a pointer, since the core ACPI code
temporarily maps/unmaps tables while iterating over them.

Since we parse the MADT before we know how many CPUs we have (and hence
before we setup the percpu areas), we must use an NR_CPUS sized array.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-04-11 16:29:54 +01:00
Gregory CLEMENT
910b4c5cb3 arm64: dts: marvell: add sdhci support for Armada 7K/8K
Also enable it on the Armada 7040 DB and Armada 8040 DB boards.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-11 09:56:27 +02:00
Gregory CLEMENT
53e747780a arm64: dts: marvell: add eMMC support for Armada 37xx
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-11 09:54:07 +02:00
Wang Xiaoyin
d4e1eaeee5 arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
Add pinctrl dtsi file for HiKey960 development board, enable
5 pinmux devices and 1 pinconf device, also include some nodes
of configurations for pins.

Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-10 23:34:26 +08:00
Wei Xu
519caba7a9 arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
Enable the NIC and SAS nodes for the hip07-d05 board
to support related functions.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-10 23:32:56 +08:00
Matthias Kaehlcke
42ae2922a6 crypto: arm64/sha - Add constant operand modifier to ASM_EXPORT
The operand is an integer constant, make the constness explicit by
adding the modifier. This is needed for clang to generate valid code
and also works with gcc.

Also change the constraint of the operand from 'I' ("Integer constant
that is valid as an immediate operand in an ADD instruction", AArch64)
to 'i' ("An immediate integer operand").

Based-on-patch-from: Greg Hackmann <ghackmann@google.com>
Signed-off-by: Greg Hackmann <ghackmann@google.com>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-10 19:17:23 +08:00
Christoffer Dall
5f6e00709c Merge remote-tracking branch 'rutland/kvm/common-sysreg' into next-fix 2017-04-09 07:50:34 -07:00
Alexander Graf
3fe17e6826 KVM: arm/arm64: Add ARM user space interrupt signaling ABI
We have 2 modes for dealing with interrupts in the ARM world. We can
either handle them all using hardware acceleration through the vgic or
we can emulate a gic in user space and only drive CPU IRQ pins from
there.

Unfortunately, when driving IRQs from user space, we never tell user
space about events from devices emulated inside the kernel, which may
result in interrupt line state changes, so we lose out on for example
timer and PMU events if we run with user space gic emulation.

Define an ABI to publish such device output levels to userspace.

Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-09 07:49:38 -07:00
Marc Zyngier
af42f20480 arm64: hyp-stub: Zero x0 on successful stub handling
We now return HVC_STUB_ERR when a stub hypercall fails, but we
leave whatever was in x0 on success. Zeroing it on return seems
like a good idea.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:35 -07:00
Marc Zyngier
0b51c547fd arm64: hyp-stub/KVM: Kill __hyp_get_vectors
Nobody is using __hyp_get_vectors anymore, so let's remove both
implementations (hyp-stub and KVM).

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:34 -07:00
Marc Zyngier
9e9ebd01a3 arm/arm64: KVM: Remove kvm_get_idmap_start
With __cpu_reset_hyp_mode having become fairly dumb, there is no
need for kvm_get_idmap_start anymore.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:32 -07:00
Marc Zyngier
0fb265930d arm/arm64: KVM: Use __hyp_reset_vectors() directly
__cpu_reset_hyp_mode doesn't need to be passed any argument now,
as the hyp-stub implementations are self-contained, and is now
reduced to just calling __hyp_reset_vectors(). Let's drop the
wrapper and use the stub hypercall directly.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:32 -07:00
Marc Zyngier
506c372ac4 arm64: KVM: Implement HVC_SOFT_RESTART in the init code
Another missing stub hypercall is HVC_SOFT_RESTART. It turns out
that it is pretty easy to implement in terms of HVC_RESET_VECTORS
(since it needs to turn the MMU off).

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:23 -07:00
Marc Zyngier
4adb1341c7 arm64: KVM: Convert __cpu_reset_hyp_mode to using __hyp_reset_vectors
We are now able to use the hyp stub to reset HYP mode. Time to
kiss __kvm_hyp_reset goodbye, and use __hyp_reset_vectors.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:22 -07:00
Marc Zyngier
5fbe9a599a arm64: KVM: Allow the main HYP code to use the init hyp stub implementation
We now have a full hyp-stub implementation in the KVM init code,
but the main KVM code only supports HVC_GET_VECTORS, which is not
enough.

Instead of reinventing the wheel, let's reuse the init implementation
by branching to the idmap page when called with a hyp-stub hypercall.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:22 -07:00
Marc Zyngier
82529d9bfd arm64: KVM: Implement HVC_GET_VECTORS in the init code
Now that we have an infrastructure to handle hypercalls in the KVM
init code, let's implement HVC_GET_VECTORS there.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:21 -07:00
Marc Zyngier
fb1b4e01d2 arm64: KVM: Implement HVC_RESET_VECTORS stub hypercall in the init code
In order to restore HYP mode to its original condition, KVM currently
implements __kvm_hyp_reset(). As we're moving towards a hyp-stub
defined API, it becomes necessary to implement HVC_RESET_VECTORS.

This patch adds the HVC_RESET_VECTORS hypercall to the KVM init
code, which so far lacked any form of hypercall support.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:20 -07:00
Marc Zyngier
fd0e0c6170 arm64: hyp-stub: Implement HVC_RESET_VECTORS stub hypercall
Let's define a new stub hypercall that resets the HYP configuration
to its default: hyp-stub vectors, and MMU disabled.

Of course, for the hyp-stub itself, this is a trivial no-op.
Hypervisors will have a bit more work to do.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:20 -07:00
Marc Zyngier
810c86ee4e arm64: hyp-stub: Update documentation in asm/virt.h
Comments in asm/virt.h are slightly out of date, so let's align
them with the new behaviour of the code.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:19 -07:00
Marc Zyngier
4993fdcf39 arm64: hyp-stub: Define a return value for failed stub calls
Define a standard return value to be returned when a hyp stub
call fails, and make KVM use it for ARM_EXCEPTION_HYP_GONE
(instead of using a KVM-specific value).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:19 -07:00
Marc Zyngier
9bae3ae513 arm64: hyp-stub: Don't save lr in the EL1 code
The EL2 code is not corrupting lr anymore, so don't bother preserving
it in the EL1 trampoline code.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:18 -07:00
Marc Zyngier
6c9ae25dfc arm64: KVM: Move lr save/restore to do_el2_call
At the moment, we only save/restore lr if on VHE, as we rely only
the EL1 code to have preserved it in the non-VHE case.

As we're about to get rid of the latter, let's move the save/restore
code to the do_el2_call macro, unifying both code paths.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:18 -07:00
Marc Zyngier
50d912cc3e arm64: hyp-stub: Stop pointlessly clobbering lr
When entering the kernel hyp stub, we check whether or not we've
made it here through an HVC instruction, clobbering lr (aka x30)
in the process.

This is completely pointless, as HVC is the only way to get here
(all traps to EL2 are disabled, no interrupt override is applied).

So let's remove this bit of code whose only point is to corrupt
a valuable register.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:17 -07:00
Marc Zyngier
b6b7a8069d arm64: KVM: Do not corrupt registers on failed 64bit CP read
If we fail to emulate a mrrc instruction, we:
1) deliver an exception,
2) spit a nastygram on the console,
3) write back some garbage to Rt/Rt2

While 1) and 2) are perfectly acceptable, 3) is out of the scope of
the architecture... Let's mimick the code in kvm_handle_cp_32 and
be more cautious.

Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:15 -07:00
Marc Zyngier
e70b952263 arm64: KVM: Treat sysreg accessors returning false as successful
Instead of considering that a sysreg accessor has failed when
returning false, let's consider that it is *always* successful
(after all, we won't stand for an incomplete emulation).

The return value now simply indicates whether we should skip
the instruction (because it has now been emulated), or if we
should leave the PC alone if the emulation has injected an
exception.

Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-09 07:49:15 -07:00
Marc Zyngier
e044323016 arm64: KVM: PMU: Inject UNDEF on read access to PMSWINC_EL0
PMSWINC_EL0 is a WO register, so let's UNDEF when reading from it
(in the highly hypothetical case where this doesn't UNDEF at EL1).

Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-09 07:49:14 -07:00
Marc Zyngier
7b5b4df1a7 arm64: KVM: Make unexpected reads from WO registers inject an undef
Reads from write-only system registers are generally confined to
EL1 and not propagated to EL2 (that's what the architecture
mantates). In order to be sure that we have a sane behaviour
even in the unlikely event that we have a broken system, we still
handle it in KVM.

In that case, let's inject an undef into the guest.

Let's also remove write_to_read_only which isn't used anywhere.

Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-09 07:49:14 -07:00
Marc Zyngier
9008c235cb arm64: KVM: PMU: Inject UNDEF on non-privileged accesses
access_pminten() and access_pmuserenr() can only be accessed when
the CPU is in a priviledged mode. If it is not, let's inject an
UNDEF exception.

Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-09 07:49:13 -07:00
Marc Zyngier
24d5950f6b arm64: KVM: PMU: Inject UNDEF exception on illegal register access
Both pmu_*_el0_disabled() and pmu_counter_idx_valid() perform checks
on the validity of an access, but only return a boolean indicating
if the access is valid or not.

Let's allow these functions to also inject an UNDEF exception if
the access was illegal.

Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-09 07:49:13 -07:00
Marc Zyngier
6c0070366d arm64: KVM: PMU: Refactor pmu_*_el0_disabled
There is a lot of duplication in the pmu_*_el0_disabled helpers,
and as we're going to modify them shortly, let's move all the
common stuff in a single function.

No functional change.

Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:49:12 -07:00
Christoffer Dall
328e566479 KVM: arm/arm64: vgic: Defer touching GICH_VMCR to vcpu_load/put
We don't have to save/restore the VMCR on every entry to/from the guest,
since on GICv2 we can access the control interface from EL1 and on VHE
systems with GICv3 we can access the control interface from KVM running
in EL2.

GICv3 systems without VHE becomes the rare case, which has to
save/restore the register on each round trip.

Note that userspace accesses may see out-of-date values if the VCPU is
running while accessing the VGIC state via the KVM device API, but this
is already the case and it is up to userspace to quiesce the CPUs before
reading the CPU registers from the GIC for an up-to-date view.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
2017-04-09 07:45:22 -07:00
Wei Xu
86d67897f9 arm64: dts: hisi: add SAS nodes for the hip07 SoC
Add 3 SAS host controller nodes and the dependent subctrl node
to enable the SAS and SATA function for the hip07 SoC.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-08 13:43:45 +08:00
Wei Xu
0f57c6c9cd arm64: dts: hisi: add RoCE nodes for the hip07 SoC
Add the infiniband node to support the RoCE function
on the hip07 SoC.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-08 11:07:26 +08:00
Wei Xu
38de5b56ef arm64: dts: hisi: add network related nodes for the hip07 SoC
Add MDIO, SerDes, Port and realted HNS nodes to support the
network on the hip07 SoC.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-08 11:07:25 +08:00
Wei Xu
bbeca45f41 arm64: dts: hisi: add mbigen nodes for the hip07 SoC
Add mbigen nodes for the hip07 SoC those will be used
for the SAS, XGE and PCIe host controllers.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-08 11:07:25 +08:00
Olof Johansson
12d28f94eb Allwinner fixes for 4.11, bis
Two fixes for the recent A33 cpufreq support, and one to fix a missing
 register in the A64 USB PHY node.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY5e/6AAoJEBx+YmzsjxAgzZcQALIDcB8ZnbHib3NjHJUFYqLI
 k2P32R93xCf1hiUhvhMB97dZNgOXqx4nyO2OabrUr9K++6ZNt7p+lIp1lnmNWnG1
 Ali6xu02UHLGHlBjqePYc5FbNbpIOa+0TkiOYvqo6CmLycsjvcbb5Ia3dAILyR/K
 NgkdGcsHV96EH4gPNzqchtaqBL/cTidHUZiIZv9Zg5zaSerRYG078VPSQ/qcA/sx
 ji/JWta/hAGHpignUzXM9dkaw2a11LEOh7YWU78WPAjRZbidgo7d3Tw7wuvE5+hd
 bUVG+T91Im3QEvOixaduw8gZ7R5345gQP2OFnm7eRRXnbQEx242z7lRnRwD/xor+
 IHYDj+Psbspeaw1oR3KrVk76neCAOHnb9O8pIXu5eHrMwB34kgUNkRx/0wuvRzu8
 fkwPtn403hzJdZa81OUGw3x8x1SndXgWPg2ez7z7Y2HjBF3U1585TvckWNrh+Xib
 2dT2PLY7GKwCehAR/dAr/RY4jT95nZC6nfDTRkCchv4HOnSOTLr5W2jlhuwhmuMi
 mcbIYhJrWRMZfe+3mg983g5DL4Z6k3lnn+Wv6AInk1TrP4TVsmgdmuCcyx116AsY
 ikCtk2SMG6QYUiy2XV5mKokaf+ex2ms0qvEJQestx3yXtU3IXOuI2qqdbTPb8XQS
 XsyqK7bEgpmLUe1y3W+z
 =lFNZ
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-fixes-for-4.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes

Allwinner fixes for 4.11, bis

Two fixes for the recent A33 cpufreq support, and one to fix a missing
register in the A64 USB PHY node.

* tag 'sunxi-fixes-for-4.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: allwinner: a64: add pmu0 regs for USB PHY
  ARM: sun8i: a33: add operating-points-v2 property to all nodes
  ARM: sun8i: a33: remove highest OPP to fix CPU crashes

Signed-off-by: Olof Johansson <olof@lixom.net>
2017-04-07 16:49:43 -07:00
Andy Yan
2f513bd9ea arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
Commit 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board")
sets the memory size to 2 GB, but this board only has 1 GB DRAM, so change
it to the correct value here.

Fixes: 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-04-07 22:29:11 +02:00
Catalin Marinas
a5a3237e50 Pre-requisites for the arch timer errata workarounds:
- Allow checking of a CPU-local erratum
 - Add CNTVCT_EL0 trap handler
 - Define Cortex-A73 MIDR
 - Allow an erratum to be match for all revisions of a core
 - Add capability to advertise Cortex-A73 erratum 858921
 -----BEGIN PGP SIGNATURE-----
 
 iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAljnlbgVHG1hcmMuenlu
 Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDx+YP/1OU8GnrVBR2cjEctaTz3s51sPRR
 +7j1BZ3pbKnwY3XpM6GJpxc//sSBSphqWZXN5GJZW1lSgw7hpl02mA9rh62G4Xmh
 wUqR2hmQ5UdenoR5tE39BZrzMFlef90bA7AZyatSqum6AEQcYPJZEgzOvEvfw/mY
 Bc4w73At9OTILRXeZjJZabdeJ4aJLs+6xMfsc9ApgxiZIZ5xhJ7CQzcJFdQ2tFeB
 9wYqxkt8i9aZfmj3IX14m3fXISQ4JlXoi8QTBqy7qunCMEFU6jtCwC5aZKj1U3Hh
 zebVWomcWMQpFaJw3qxZgjVXftv5r2UsHbMoLo4wFa98Qerr7t9/bGifbFqpKm7S
 hA0uzcftUHoQF+l/Qxt9rTlsPKrBMoXjY2XDkKiWP/hqXsXKDBnngKQb2ZFJFT5r
 UABMBhqlBQpI2l0/Qn0fL7aEC1xZCVnSgGpAXFvg/Ci7X2K+HH37brt5uNh3vDZI
 c5UaWUUycDa5GcCnmoK3QWVeitVW/ydJGaoIT06CKBDrktcpsoO4u4w6CI8xsIJL
 RbJwCb72JU5HV7XDpdbc/lLzi30kWceOEUSHrs3dCEnkr41kOunDGm/Xxk/Sm8VL
 SeYSx9UotuJvWWozZzVWpLiUSizjh6UB2XWnkSLkT++KA6YPX4L2/hYAw7E3bYVe
 FAFoLL7jUYdrjpCF
 =XSx4
 -----END PGP SIGNATURE-----

Merge tag 'arch-timer-errata-prereq' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into for-next/core

Pre-requisites for the arch timer errata workarounds:

- Allow checking of a CPU-local erratum
- Add CNTVCT_EL0 trap handler
- Define Cortex-A73 MIDR
- Allow an erratum to be match for all revisions of a core
- Add capability to advertise Cortex-A73 erratum 858921

* tag 'arch-timer-errata-prereq' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms:
  arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921
  arm64: cpu_errata: Allow an erratum to be match for all revisions of a core
  arm64: Define Cortex-A73 MIDR
  arm64: Add CNTVCT_EL0 trap handler
  arm64: Allow checking of a CPU-local erratum
2017-04-07 17:04:19 +01:00
Paolo Bonzini
4b4357e025 kvm: make KVM_COALESCED_MMIO_PAGE_OFFSET public
Its value has never changed; we might as well make it part of the ABI instead
of using the return value of KVM_CHECK_EXTENSION(KVM_CAP_COALESCED_MMIO).

Because PPC does not always make MMIO available, the code has to be made
dependent on CONFIG_KVM_MMIO rather than KVM_COALESCED_MMIO_PAGE_OFFSET.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2017-04-07 16:49:01 +02:00
Will Deacon
6ae979ab39 Revert "Revert "arm64: hugetlb: partial revert of 66b3923a1a0f""
The use of the contiguous bit by our hugetlb implementation violates
the break-before-make requirements of the architecture and can lead to
silent data corruption or TLB conflict aborts. Once again, disable these
hugetlb sizes whilst it gets worked out.

This reverts commit ab2e1b8923.

Conflicts:
	arch/arm64/mm/hugetlbpage.c

Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-04-07 12:27:29 +01:00
Marc Zyngier
5a38bcac1f arm64: arch_timer: Allow erratum matching with ACPI OEM information
Just as we're able to identify a broken platform using some DT
information, let's enable a way to spot the offenders with ACPI.

The difference is that we can only match on some OEM info instead
of implementation-specific properties. So in order to avoid the
insane multiplication of errata structures, we allow an array
of OEM descriptions to be attached to an erratum structure.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: dann frazier <dann.frazier@canonical.com>
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:10 +01:00
Marc Zyngier
6acc71ccac arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs
Instead of applying a CPU-specific workaround to all CPUs in the system,
allow it to only affect a subset of them (typical big-little case).

This is done by turning the erratum pointer into a per-CPU variable.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:09 +01:00
Marc Zyngier
8c64621bf9 arm64: arch_timer: Make workaround methods optional
Not all errata need to workaround all access types. Allow them to
be optional.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:09 +01:00
Marc Zyngier
01d3e3ff26 arm64: arch_timer: Rework the set_next_event workarounds
The way we work around errata affecting set_next_event is not very
nice, at it imposes this workaround on errata that do not need it.

Add new workaround hooks and let the existing workarounds use them.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:09 +01:00
Marc Zyngier
eeb1efbcb8 arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921
In order to work around Cortex-A73 erratum 858921 in a subsequent
patch, add the required capability that advertise the erratum.

As the configuration option it depends on is not present yet,
this has no immediate effect.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:08 +01:00
Marc Zyngier
06f1494f83 arm64: cpu_errata: Allow an erratum to be match for all revisions of a core
Some minor erratum may not be fixed in further revisions of a core,
leading to a situation where the workaround needs to be updated each
time an updated core is released.

Introduce a MIDR_ALL_VERSIONS match helper that will work for all
versions of that MIDR, once and for all.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:08 +01:00
Marc Zyngier
0064030c6f arm64: arch_timer: Add erratum handler for CPU-specific capability
Should we ever have a workaround for an erratum that is detected using
a capability and affecting a particular CPU, it'd be nice to have
a way to probe them directly.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:08 +01:00
Marc Zyngier
199fd2bff4 arm64: Define Cortex-A73 MIDR
As we're about to introduce a new workaround that is specific to
Cortex-A73, let's define the coresponding MIDR.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:08 +01:00
Marc Zyngier
651bb2e9dc arm64: arch_timer: Add infrastructure for multiple erratum detection methods
We're currently stuck with DT when it comes to handling errata, which
is pretty restrictive. In order to make things more flexible, let's
introduce an infrastructure that could support alternative discovery
methods. No change in functionality.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:08 +01:00
Marc Zyngier
6126ce0588 arm64: Add CNTVCT_EL0 trap handler
Since people seem to make a point in breaking the userspace visible
counter, we have no choice but to trap the access. Add the required
handler.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:08 +01:00
Marc Zyngier
8f41375882 arm64: Allow checking of a CPU-local erratum
this_cpu_has_cap() only checks the feature array, and not the errata
one. In order to be able to check for a CPU-local erratum, allow it
to inspect the latter as well.

This is consistent with cpus_have_cap()'s behaviour, which includes
errata already.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-04-07 11:22:08 +01:00
Stephen Boyd
b824b93068 arm64: print a fault message when attempting to write RO memory
If a page is marked read only we should print out that fact,
instead of printing out that there was a page fault. Right now we
get a cryptic error message that something went wrong with an
unhandled fault, but we don't evaluate the esr to figure out that
it was a read/write permission fault.

Instead of seeing:

  Unable to handle kernel paging request at virtual address ffff000008e460d8
  pgd = ffff800003504000
  [ffff000008e460d8] *pgd=0000000083473003, *pud=0000000083503003, *pmd=0000000000000000
  Internal error: Oops: 9600004f [#1] PREEMPT SMP

we'll see:

  Unable to handle kernel write to read-only memory at virtual address ffff000008e760d8
  pgd = ffff80003d3de000
  [ffff000008e760d8] *pgd=0000000083472003, *pud=0000000083435003, *pmd=0000000000000000
  Internal error: Oops: 9600004f [#1] PREEMPT SMP

We also add a userspace address check into is_permission_fault()
so that the function doesn't return true for ttbr0 PAN faults
when it shouldn't.

Reviewed-by: James Morse <james.morse@arm.com>
Tested-by: James Morse <james.morse@arm.com>
Acked-by: Laura Abbott <labbott@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-06 17:36:09 +01:00
Icenowy Zheng
0d98479738 arm64: allwinner: a64: add pmu0 regs for USB PHY
The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
controller pair that can be connected to the PHY0.

Add the MMIO region for PHY node.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-06 09:13:10 +02:00
Jiancheng Xue
2f20182ed6 arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
Add basic dts files for hi3798cv200-poplar board. Poplar is the
first development board compliant with the 96Boards Enterprise
Edition TV Platform specification. The board features the
Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53
processor and high performance Mali T720 GPU.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-06 14:03:05 +08:00
Daniel Lezcano
0fbdf9953b arm64: dts: hi6220: Reset the mmc hosts
The MMC hosts could be left in an unconsistent or uninitialized state from
the firmware. Instead of assuming, the firmware did the right things, let's
reset the host controllers.

This change fixes a bug when the mmc2/sdio is initialized leading to a hung
task:

[  242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds.
[  242.711129]       Not tainted 4.9.0-rc8-00017-gcf0251f #3
[  242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[  242.724435] kworker/7:1     D    0   675      2 0x00000000
[  242.729973] Workqueue: events_freezable mmc_rescan
[  242.734796] Call trace:
[  242.737269] [<ffff00000808611c>] __switch_to+0xa8/0xb4
[  242.742437] [<ffff000008d07c04>] __schedule+0x1c0/0x67c
[  242.747689] [<ffff000008d08254>] schedule+0x40/0xa0
[  242.752594] [<ffff000008d0b284>] schedule_timeout+0x1c4/0x35c
[  242.758366] [<ffff000008d08e38>] wait_for_common+0xd0/0x15c
[  242.763964] [<ffff000008d09008>] wait_for_completion+0x28/0x34
[  242.769825] [<ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124
[  242.775949] [<ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8
[  242.781549] [<ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84
[  242.787149] [<ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114
[  242.793270] [<ffff000008a26aa0>] sdio_reset+0x34/0x7c
[  242.798347] [<ffff000008a1d46c>] mmc_rescan+0x2fc/0x360

[ ... ]

Cc: stable@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-06 11:37:21 +08:00
Geert Uytterhoeven
6922bd71ad arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-05 14:17:19 -04:00
AKASHI Takahiro
3f5c1e1e76 arm64: kdump: enable kdump in defconfig
Kdump is enabled by default as kexec is.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:32:25 +01:00
AKASHI Takahiro
e62aaeac42 arm64: kdump: provide /proc/vmcore file
Arch-specific functions are added to allow for implementing a crash dump
file interface, /proc/vmcore, which can be viewed as a ELF file.

A user space tool, like kexec-tools, is responsible for allocating
a separate region for the core's ELF header within crash kdump kernel
memory and filling it in when executing kexec_load().

Then, its location will be advertised to crash dump kernel via a new
device-tree property, "linux,elfcorehdr", and crash dump kernel preserves
the region for later use with reserve_elfcorehdr() at boot time.

On crash dump kernel, /proc/vmcore will access the primary kernel's memory
with copy_oldmem_page(), which feeds the data page-by-page by ioremap'ing
it since it does not reside in linear mapping on crash dump kernel.

Meanwhile, elfcorehdr_read() is simple as the region is always mapped.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: James Morse <james.morse@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:31:38 +01:00
AKASHI Takahiro
20a1662433 arm64: kdump: add VMCOREINFO's for user-space tools
In addition to common VMCOREINFO's defined in
crash_save_vmcoreinfo_init(), we need to know, for crash utility,
  - kimage_voffset
  - PHYS_OFFSET
to examine the contents of a dump file (/proc/vmcore) correctly
due to the introduction of KASLR (CONFIG_RANDOMIZE_BASE) in v4.6.

  - VA_BITS
is also required for makedumpfile command.

arch_crash_save_vmcoreinfo() appends them to the dump file.
More VMCOREINFO's may be added later.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: James Morse <james.morse@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:29:47 +01:00
AKASHI Takahiro
78fd584cde arm64: kdump: implement machine_crash_shutdown()
Primary kernel calls machine_crash_shutdown() to shut down non-boot cpus
and save registers' status in per-cpu ELF notes before starting crash
dump kernel. See kernel_kexec().
Even if not all secondary cpus have shut down, we do kdump anyway.

As we don't have to make non-boot(crashed) cpus offline (to preserve
correct status of cpus at crash dump) before shutting down, this patch
also adds a variant of smp_send_stop().

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: James Morse <james.morse@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:29:15 +01:00
AKASHI Takahiro
254a41c0ba arm64: hibernate: preserve kdump image around hibernation
Since arch_kexec_protect_crashkres() removes a mapping for crash dump
kernel image, the loaded data won't be preserved around hibernation.

In this patch, helper functions, crash_prepare_suspend()/
crash_post_resume(), are additionally called before/after hibernation so
that the relevant memory segments will be mapped again and preserved just
as the others are.

In addition, to minimize the size of hibernation image, crash_is_nosave()
is added to pfn_is_nosave() in order to recognize only the pages that hold
loaded crash dump kernel image as saveable. Hibernation excludes any pages
that are marked as Reserved and yet "nosave."

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:28:50 +01:00
Takahiro Akashi
98d2e1539b arm64: kdump: protect crash dump kernel memory
arch_kexec_protect_crashkres() and arch_kexec_unprotect_crashkres()
are meant to be called by kexec_load() in order to protect the memory
allocated for crash dump kernel once the image is loaded.

The protection is implemented by unmapping the relevant segments in crash
dump kernel memory, rather than making it read-only as other archs do,
to prevent coherency issues due to potential cache aliasing (with
mismatched attributes).

Page-level mappings are consistently used here so that we can change
the attributes of segments in page granularity as well as shrink the region
also in page granularity through /sys/kernel/kexec_crash_size, putting
the freed memory back to buddy system.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:28:35 +01:00
AKASHI Takahiro
9b0aa14e31 arm64: mm: add set_memory_valid()
This function validates and invalidates PTE entries, and will be utilized
in kdump to protect loaded crash dump kernel image.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:27:53 +01:00
AKASHI Takahiro
764b51ead1 arm64: kdump: reserve memory for crash dump kernel
"crashkernel=" kernel parameter specifies the size (and optionally
the start address) of the system ram to be used by crash dump kernel.
reserve_crashkernel() will allocate and reserve that memory at boot time
of primary kernel.

The memory range will be exposed to userspace as a resource named
"Crash kernel" in /proc/iomem.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Pratyush Anand <panand@redhat.com>
Reviewed-by: James Morse <james.morse@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:26:57 +01:00
AKASHI Takahiro
8f579b1c4e arm64: limit memory regions based on DT property, usable-memory-range
Crash dump kernel uses only a limited range of available memory as System
RAM. On arm64 kdump, This memory range is advertised to crash dump kernel
via a device-tree property under /chosen,
   linux,usable-memory-range = <BASE SIZE>

Crash dump kernel reads this property at boot time and calls
memblock_cap_memory_range() to limit usable memory which are listed either
in UEFI memory map table or "memory" nodes of a device tree blob.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Geoff Levand <geoff@infradead.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-05 18:26:54 +01:00
Bhupesh Sharma
6e7300cff1 efi/bgrt: Enable ACPI BGRT handling on arm64
Now that the ACPI BGRT handling code has been made generic, we can
enable it for arm64.

Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
[ Updated commit log to reflect that BGRT is only enabled for arm64, and added
  missing 'return' statement to the dummy acpi_parse_bgrt() function. ]
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Matt Fleming <matt@codeblueprint.co.uk>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/20170404160245.27812-8-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-04-05 12:27:25 +02:00
Ard Biesheuvel
24d7c494ce efi/arm-stub: Round up FDT allocation to mapping size
The FDT is mapped via a fixmap entry that is at least 2 MB in size and
2 MB aligned on 4 KB page size kernels.

On UEFI systems, the FDT allocation may share this 2 MB mapping with a
reserved region (or another memory region that we should never map),
unless we account for this in the size of the allocation (the alignment
is already 2 MB)

So instead of taking guesses at the needed space, simply allocate 2 MB
immediately. The allocation will be recorded as EFI_LOADER_DATA, and the
kernel only memblock_reserve()'s the actual size of the FDT, so the
unused space will be released back to the kernel.

Reviewed-By: Jeffrey Hugo <jhugo@codeaurora.org>
Tested-by: Richard Ruigrok <rruigrok@codeaurora.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Matt Fleming <matt@codeblueprint.co.uk>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/20170404160245.27812-6-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-04-05 12:27:24 +02:00
Ard Biesheuvel
138728dd4e efi/arm-stub: Correct FDT and initrd allocation rules for arm64
On arm64, we have made some changes over the past year to the way the
kernel itself is allocated and to how it deals with the initrd and FDT.
This patch brings the allocation logic in the EFI stub in line with that,
which is necessary because the introduction of KASLR has created the
possibility for the initrd to be allocated in a place where the kernel
may not be able to map it. (This is mostly a theoretical scenario, since
it only affects systems where the physical memory footprint exceeds the
size of the linear mapping.)

Since we know the kernel itself will be covered by the linear mapping,
choose a suitably sized window (i.e., based on the size of the linear
region) covering the kernel when allocating memory for the initrd.

The FDT may be anywhere in memory on arm64 now that we map it via the
fixmap, so we can lift the address restriction there completely.

Tested-by: Richard Ruigrok <rruigrok@codeaurora.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Matt Fleming <matt@codeblueprint.co.uk>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/20170404160245.27812-4-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-04-05 12:27:23 +02:00
Neil Armstrong
6939db7e0d ARM64: dts: meson-gx: Add support for HDMI output
Add HDMI output and connector nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-04 11:04:17 -07:00
Neil Armstrong
e9da72821f ARM64: dts: meson-gx: Add shared CMA dma memory pool
The HDMI modes needs more CMA memory to be reserved at boot-time.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-04 11:04:17 -07:00
Heiner Kallweit
62158c6a9c ARM64: dts: meson-gxbb-odroidc2: Enable SARADC node
Now that 3adbf34273 "iio: adc: add a driver for the SAR ADC found in
Amlogic Meson SoCs" has added support for the ADC, let's enable it
on Odroid C2.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-04 11:04:17 -07:00
Catalin Marinas
dffb0113d5 Merge branch 'arm64/common-sysreg' of git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux into for-next/core
* 'arm64/common-sysreg' of git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux:
  arm64: sysreg: add Set/Way sys encodings
  arm64: sysreg: add register encodings used by KVM
  arm64: sysreg: add physical timer registers
  arm64: sysreg: subsume GICv3 sysreg definitions
  arm64: sysreg: add performance monitor registers
  arm64: sysreg: add debug system registers
  arm64: sysreg: sort by encoding
2017-04-04 18:08:47 +01:00
Ard Biesheuvel
cad27ef27e arm64: efi: split Image code and data into separate PE/COFF sections
To prevent unintended modifications to the kernel text (malicious or
otherwise) while running the EFI stub, describe the kernel image as
two separate sections: a .text section with read-execute permissions,
covering .text, .rodata and .init.text, and a .data section with
read-write permissions, covering .init.data, .data and .bss.

This relies on the firmware to actually take the section permission
flags into account, but this is something that is currently being
implemented in EDK2, which means we will likely start seeing it in
the wild between one and two years from now.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-04 17:50:59 +01:00
Ard Biesheuvel
f1eb542f39 arm64: efi: replace open coded constants with symbolic ones
Replace open coded constants with symbolic ones throughout the
Image and the EFI headers. No binary level changes are intended.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-04 17:50:50 +01:00
Ard Biesheuvel
effc7b027a arm64: efi: remove pointless dummy .reloc section
The kernel's EFI PE/COFF header contains a dummy .reloc section, and
an explanatory comment that claims that this is required for the EFI
application loader to accept the Image as a relocatable image (i.e.,
one that can be loaded at any offset and fixed up in place)

This was inherited from the x86 implementation, which has elaborate host
tooling to mangle the PE/COFF header post-link time, and which populates
the .reloc section with a single dummy base relocation. On ARM, no such
tooling exists, and the .reloc section remains empty, and is never even
exposed via the BaseRelocationTable directory entry, which is where the
PE/COFF loader looks for it.

The PE/COFF spec is unclear about relocatable images that do not require
any fixups, but the EDK2 implementation, which is the de facto reference
for PE/COFF in the UEFI space, clearly does not care, and explicitly
mentions (in a comment) that relocatable images with no base relocations
are perfectly fine, as long as they don't have the RELOCS_STRIPPED
attribute set (which is not the case for our PE/COFF image)

So simply remove the .reloc section altogether.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Peter Jones <pjones@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-04 17:50:41 +01:00
Ard Biesheuvel
f328ba470c arm64: efi: remove forbidden values from the PE/COFF header
Bring the PE/COFF header in line with the PE/COFF spec, by setting
NumberOfSymbols to 0, and removing the section alignment flags.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-04 17:50:34 +01:00
Ard Biesheuvel
99922257cf arm64: efi: clean up Image header after PE header has been split off
After having split off the PE header, clean up the bits that remain:
use .long consistently, merge two adjacent #ifdef CONFIG_EFI blocks,
fix the offset of the PE header pointer and remove the redundant .align
that follows it.

Also, since we will be eliminating all open coded constants from the
EFI header in subsequent patches, let's replace the open coded "ARM\x64"
magic number with its .ascii equivalent.

No changes to the resulting binary image are intended.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-04 17:50:28 +01:00
Ard Biesheuvel
b5f4a214b8 arm64: efi: move EFI header and related data to a separate .S file
In preparation of yet another round of modifications to the PE/COFF
header, macroize it and move the definition into a separate source
file.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-04 17:50:09 +01:00
Liang Chen
0c1f854675 arm64: dts: rockchip: add RK3328 eavluation board devicetree
This patch add rk3328-evb.dts for RK3328 evaluation board.
Tested on RK3328 evb.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-04-04 18:12:25 +02:00
Ard Biesheuvel
214fad5507 arm64: relocation testing module
This module tests the module loader's ELF relocation processing
routines. When loaded, it logs output like below.

    Relocation test:
    -------------------------------------------------------
    R_AARCH64_ABS64                 0xffff880000cccccc pass
    R_AARCH64_ABS32                 0x00000000f800cccc pass
    R_AARCH64_ABS16                 0x000000000000f8cc pass
    R_AARCH64_MOVW_SABS_Gn          0xffff880000cccccc pass
    R_AARCH64_MOVW_UABS_Gn          0xffff880000cccccc pass
    R_AARCH64_ADR_PREL_LO21         0xffffff9cf4d1a400 pass
    R_AARCH64_PREL64                0xffffff9cf4d1a400 pass
    R_AARCH64_PREL32                0xffffff9cf4d1a400 pass
    R_AARCH64_PREL16                0xffffff9cf4d1a400 pass

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-04 17:03:32 +01:00
Liang Chen
52e02d377a arm64: dts: rockchip: add core dtsi file for RK3328 SoCs
This patch adds core dtsi file for Rockchip RK3328 SoCs.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-04-04 18:03:01 +02:00
Dave Martin
46823dd17c arm64: cpufeature: Make ID reg accessor naming less counterintuitive
read_system_reg() can readily be confused with read_sysreg(),
whereas these are really quite different in their meaning.

This patches attempts to reduce the ambiguity be reserving "sysreg"
for the actual system register accessors.

read_system_reg() is instead renamed to read_sanitised_ftr_reg(),
to make it more obvious that the Linux-defined sanitised feature
register cache is being accessed here, not the underlying
architectural system registers.

cpufeature.c's internal __raw_read_system_reg() function is renamed
in line with its actual purpose: a form of read_sysreg() that
indexes on (non-compiletime-constant) encoding rather than symbolic
register name.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-04 16:55:41 +01:00
Icenowy Zheng
ec4279053a arm64: allwinner: a64: add R_PIO pinctrl node
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04 17:45:09 +02:00
Icenowy Zheng
791a9e001d arm64: allwinner: a64: add r_ccu node
A64 SoC have a CCU (r_ccu) in PRCM block.

Add the device node for it.

The mux 3 of R_CCU is an internal oscillator, which is 16MHz according
to the user manual, and has only 30% accuracy based on our experience
on older SoCs. The real mesaured value of it on two Pine64 boards is
around 11MHz, which is around 70% of 16MHz.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04 17:44:57 +02:00
Jon Hunter
18236a1488 arm64: tegra: Update the Tegra132 flowctrl compatible string
Update the Tegra132 flowctrl compatible string to include
"nvidia,tegra132-flowctrl" so it is aligned with the flowctrl binding
documentation.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04 17:15:05 +02:00
Alexandre Courbot
dfd7a3845a arm64: tegra: Add GPU node for Tegra186
Add the DT node for the GP10B GPU on Tegra186.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04 17:15:05 +02:00
Victor Kamensky
09a6adf53d arm64: mm: unaligned access by user-land should be received as SIGBUS
After 52d7523 (arm64: mm: allow the kernel to handle alignment faults on
user accesses) commit user-land accesses that produce unaligned exceptions
like in case of aarch32 ldm/stm/ldrd/strd instructions operating on
unaligned memory received by user-land as SIGSEGV. It is wrong, it should
be reported as SIGBUS as it was before 52d7523 commit.

Changed do_bad_area function to take signal and code parameters out of esr
value using fault_info table, so in case of do_alignment_fault fault
user-land will receive SIGBUS. Wrapped access to fault_info table into
esr_to_fault_info function.

Cc: <stable@vger.kernel.org>
Fixes: 52d7523 (arm64: mm: allow the kernel to handle alignment faults on user accesses)
Signed-off-by: Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-04-04 12:13:36 +01:00
Greg Kroah-Hartman
cb2e3d461b Merge 4.11-rc5 into usb-next
We want the usb fixes in here as well.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-03 14:16:25 +02:00
Al Viro
bee3f412d6 Merge branch 'parisc-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux into uaccess.parisc 2017-04-02 10:33:48 -04:00
Rob Herring
dc10ef2dfd arm64: dts: juno: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2017-03-31 11:03:15 +01:00
Arnd Bergmann
9720a9a31d Rockchip dts changes based on the newly created arm/arm64 symlinks.
The core addition is the support for the rk3399-based Gru family of
 ChromeOS devices, like the Kevin board which is the recently released
 Samsung Chromebook Plus. Additionally the usb3 controllers are added
 to rk3399 as they're used on Gru devices and even without full type-c
 support they can at least drive usb2 devices already.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljY62IQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgYkKCACdlgqbhUPiGj/xGqSlBRdWzX20nMAmFMLh
 jPDSX3wjOTtmxCUoyGB4eac/823fVydVzf0OeLGTyJc7zx3IS+7p6dPMdV0ulLio
 UAKyhJk6HbAOWdQXRZFQbSGeWfcaRB12gu5uNbUiwaDsD7Pguk2z/H/z9pS03ydB
 OIXB3UrIKl0YW0CYhqH6Rt09af/8q3IaTDVwJpAXvAUNVcYogUK797fTXsxH8CD2
 e92qmtbEEdI6FGsACP6OTQx2mBDZCd+weABaacxKhIJ9IPce8QHVtcZj2VjH43L7
 TzIZkQ4b5MMG176mpofNzv2+O3i9BAzAkoX87czz7Y9fwuf7pFfy
 =rqs0
 -----END PGP SIGNATURE-----

Merge tag 'v4.12-rockchip-dts64-symlinks-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Pull "Rockchip dts64 updates (using arm/arm64 symlinks) for 4.12 part1" from Heiko Stübner

Rockchip dts changes based on the newly created arm/arm64 symlinks.
The core addition is the support for the rk3399-based Gru family of
ChromeOS devices, like the Kevin board which is the recently released
Samsung Chromebook Plus. Additionally the usb3 controllers are added
to rk3399 as they're used on Gru devices and even without full type-c
support they can at least drive usb2 devices already.

* tag 'v4.12-rockchip-dts64-symlinks-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: add regulator info for Kevin digitizer
  arm64: dts: rockchip: describe Gru/Kevin OPPs + CPU regulators
  arm64: dts: rockchip: add Gru/Kevin DTS
  dt-bindings: Document rk3399 Gru/Kevin
  arm64: dts: rockchip: support dwc3 USB for rk3399
2017-03-31 11:54:40 +02:00
Arnd Bergmann
a5cd01ff18 Contains various changes for the rk3368 (dma, i2s, disable mailbox per
default, mmc-resets) and also removes the wrongly added idle states, that
 do not match the hardware's capabilities, as well as some general rk3399
 pcie fixes as well as also the mmc resets.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljY6c0QHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgdIYB/wKt/kONmWhi3RsXCXFUv/PBM0NToKvUq5e
 5LvprMvIb/dyEBpA1bSaxOmktYDmEzqQFfxBOT7gfWX8/N+oFLWsfLsMNGkReev0
 QPxQaITA1sOVSqDPWb5Pw4jDJ58CKUH1Cvj9GU1NuU3qp5ioggMTr/RFk2FsQ2wi
 AJTDmyRHIp2Hfr7C//H85U7qd0NB0xQJz4GpZ98HnuZoSzpeQs7SRikOr4PZAaEA
 mqsFizsELiAee/BmsTsppjzEIM5MpCIe91fx4S5NBNbnbmy2pFvXsmL5QazTWyao
 FiWPPcIWuEVnuVLWXAGn4vLlKJG7DH+aJSOtN482J/fRnaTZABU6
 =/nLm
 -----END PGP SIGNATURE-----

Merge tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Pull "Rockchip dts64 updates for 4.12 part1" from Heiko Stübner:

Contains various changes for the rk3368 (dma, i2s, disable mailbox per
default, mmc-resets) and also removes the wrongly added idle states, that
do not match the hardware's capabilities, as well as some general rk3399
pcie fixes as well as also the mmc resets.

* tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: fix PCIe domain number for rk3399
  arm64: dts: rockchip: add rk3399 dw-mmc resets
  arm64: dts: rockchip: add rk3368 dw-mmc resets
  arm64: dts: rockchip: disable mailbox of RK3368 SoCs per default
  arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs
  arm64: dts: rockchip: add dmac nodes for rk3368 SoCs
  arm64: dts: rockchip: remove wrongly added idle states on rk3368
  arm64: dts: rockchip: sort rk3399-pcie by unit address
2017-03-31 11:53:40 +02:00
Arnd Bergmann
bda484e76e This pull request contains Broadcom ARM64-based SoCs Device Tree updates for
4.12, please pull the following:
 
 - Rob enables the cryptographic block on Northstar 2 (SPU) by adding the proper
   Device Tree nodes
 
 - Jon replaces all occurences of: status = "ok" with status = "okay" to better
   conform to the Device Tree specification
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY1VaOAAoJEIfQlpxEBwcEcV4P/3jbaahcHY8RQgzUEV2IOHL6
 r82SI54BGNzrLRZQCeOQopUzTSiVtpSuFkjaZZr3zsKg0rFOQL5krQQiqXFq4m4G
 uzzBRCFXJb4ePE/czylE6YyNZFjAiQmpvWltNJwRQ8vbEml5M3B/PEfWaW9OTFxx
 5FulbvF1RG4zU0BG3DS1YggejQqNmNiT/CvwVBg1qLq2m9yGXd8XVsIRKMVxKGTx
 YZnxAEKueE/DqY5N9WvwKcTPP7JzBPPSPLqbSlPFI5+uRKn/EQ6pHBbSzCQXGEjb
 hpfKkMK2gFhnNw0Uvb9k5cT/sbst3evsaYGTE6q2DplKchCF1D1OQbUK5Dqn2ork
 MvitS7zkOavHrx+QPP0QkwPjWJrcCNnlIGwjFR/L8xl1Cz0WvSg9npyLVJr5kjmH
 uLDnx1RxKzDDaf/K42ZmuABRC7OURf2w7ARoAD4Z8Y4hRe+in7A9YTP8pHMjOcgG
 BR1aSr6zgLnqvMJDT+p0WrCTiEnd4rOJKL2zM/mmYdlYzkLe+HQ1YTi3mkCkEaTR
 Ao6TH8uAGJnc5ve7xY50ChNDlbKOUL6Nip/RMiayqr6JfG5OkMoqkrhF9gLYcnNo
 c4zLRT7sKBXJrYHqgo3xZuk41mYaiqoSsYiuXS283T1miOK1BWZ0ZzqIP+MH53yz
 yA1EmWP1XdHuU6hvKrZ8
 =yeV5
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-4.12/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64

Pull "Broadcom devicetree-arm64 changes for 4.12" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoCs Device Tree updates for
4.12, please pull the following:

- Rob enables the cryptographic block on Northstar 2 (SPU) by adding the proper
  Device Tree nodes

- Jon replaces all occurences of: status = "ok" with status = "okay" to better
  conform to the Device Tree specification

* tag 'arm-soc/for-4.12/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2: convert "ok" to "okay"
  arm64: dts: NS2: Add Broadcom SPU driver DT entry
2017-03-31 11:52:16 +02:00
Arnd Bergmann
8e8c72535d mvebu dt64 for 4.12 (part 1)
- Add RTC support on Armada 7k/8k
 - Improve i2c support on Armada 37xx
 - Add gpio expander and RTC on Armada 3720 board
 - Improve USB3 support on Armada 37xx
 - Add network support on Armada 7k/8k
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWNVViCMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71b/NAJ9Y60FsHOFK
 08mr2r3h/4+ydzlxWQCfQeR509BowT9/i92+Rl1ZhqS7SS0=
 =kbjv
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-dt64-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt64

Pull "mvebu dt64 for 4.12 (part 1)" from Gregory CLEMENT:

- Add RTC support on Armada 7k/8k
- Improve i2c support on Armada 37xx
- Add gpio expander and RTC on Armada 3720 board
- Improve USB3 support on Armada 37xx
- Add network support on Armada 7k/8k

* tag 'mvebu-dt64-4.12-1' of git://git.infradead.org/linux-mvebu:
  arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K
  ARM64: dts: marvell: armada-3720 add RTC support
  ARM64: dts: marvell: armada-3720-db: Add phy for USB3
  ARM64: dts: marvell: armada-37xx: Add clock resource for USB3
  ARM64: dts: marvell: armada-37xx: Fix interrupt mapping for USB3
  ARM64: dts: marvell: armada-3720-db: add gpio expander
  ARM64: dts: marvell: armada37xx: add address and size property for i2c cells
  arm64: dts: marvell: add RTC description for Armada 7K/8K
2017-03-31 11:51:03 +02:00
Arnd Bergmann
6cd8eaacb8 UniPhier ARM64 SoC DT updates for v4.12
- Fix W=* build warnings
 - Add pinctrl properties to eMMC nodes
 - Fix resets properties of USB nodes
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJY0byiAAoJED2LAQed4NsGG/0P/34WlG/kvjVxm2XRNUNz/+Mv
 zT1d5t+4yG0vD2m2RhaB0FhJPLX3h8U1ZgulZgALzDyi2R/1IDvZBjXzzgYUTz14
 LZPD/XOFfbrD//KHXPvbreOr6qcOgqIZq7P03oBYcyg2AmkfUNdfNSRLtF+YFKIf
 tjNJOUHewBr6mtMzWdp+PO8ARUSWFw9x7fro6B5eW1vh9CRZxfXGiNp8yJIxHu8i
 3hq3QFlCFO5pspY6OCpap+hf1O/duvT2W4vp/ZO+4BSjxaPTMdWxmNLehxlSkYi0
 tQbLPN9nnqVd/Z7dODCokcPaSM5QJLOP7k9yoSgldu/J92XF42CARkaC4jK07KAJ
 gGZN5MtCHTsZAkHUnbNiZRWgmiMBZhECSainEVMtDORCngyUGdP2Mi+Uriyqqy2j
 vK8MBDbI1BcQQP29JAE7cuBAE0n1r9SyUyTE5iBiFXnatExKJzqnc6fmk3+CO2l5
 Q5EYhlFeYXvEYXHhB1Zu5wa9OguTjqsNqLLm6FLqX6yUAOG/ZCSsQ0ijza3m8swj
 lnTik+F3ePbMDQ45zsSo6e+mlEOizWw7p7bpJBQ8Cgkbqivyk2qME1/sCUwuw+Bq
 WyuIsOGpkverPfI1g+EnOLkK3GTzQWlM/LIvrlvZsqhsqYlxuUX9UeIzN9ss31sG
 AW6piCyxUyfN6fli1nHd
 =X39C
 -----END PGP SIGNATURE-----

Merge tag 'uniphier-dt64-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64

Pull "UniPhier ARM64 SoC DT updates for v4.12" from Masahiro Yamada:

- Fix W=* build warnings
- Add pinctrl properties to eMMC nodes
- Fix resets properties of USB nodes

* tag 'uniphier-dt64-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  arm64: dts: uniphier: re-order reset deassertion of USB of LD11
  arm64: dts: uniphier: add pinctrl property to eMMC node for LD11/LD20
  arm64: dts: uniphier: move memory node below aliases node
  arm64: dts: uniphier: fix no unit name warnings
2017-03-31 11:45:14 +02:00
Jayachandran C
517b311eae arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2
Move and update device tree files as part of transition from Broadcom
Vulcan to Cavium ThunderX2.

The changes are to:
 * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi,
   update cpu cores to be "cavium,thunder2", and update SoC to be
   "cavium,thunderx2-cn9900"
 * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi
   and update board name string
 * Update dts/broadcom/Makefile not to build vulcan dtbs
 * Update dts/cavium/Makefile to build thunder2 dtbs

No changes to the dts contents except the updated "compatible" and
"model" properties.

Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-03-31 11:42:30 +02:00
Arnd Bergmann
e1c98a2720 This pull request contains Broadcom ARM64-based SoCs defconfig updates for
4.12, please pull the following:
 
 - Gerd enables the BCM2835 MMC driver which yields better performance than the
   default one (iProc)
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY1VXOAAoJEIfQlpxEBwcE8UwP/3Q6JuaHapjsJw2f8wQL4pMd
 tSpVmXYaYTJ7zMjgwJECpgxNfA2F475TRhCPI7p+0KkGCzgL5ZmrOIt8cA98LGWW
 hFVYJsPLzDaMrUwC1ujCJ573wmYiCJNW8tO9g8KRThbqoRwTxZmFerwPUJV5AO23
 ni1WgUgncDML9iaQvxI0k5QEmXt2+QA7zhUUS7nwkeiHedsV7AZfZLyBv2rlavQQ
 W58P8lFfW9Cqzh9ZHxodPcSTzeW96GrDHJncXQE6ngUXXdgOWNQOpEFGJ3hA0TRK
 VSrmT8UyfVv+PtZp2m4XG5jZSEZ8xO2HMuLI/Gi5UkrvcPMYlxm/AbtRM/8rSftP
 UyAt7bfUM7XNAGMMtETIy3/bCHpqbRBQxP2uDcXDuk4LyHdB8VOvqSMA92oPHPem
 Wr8r9hwwVuKQfjh+8jFKHKURU9escrnSyLcYaYB4lK97JF5ZC6XJG/aN2cT23Kof
 koDjVzrmIzS1QWkvl/bw/9Tvsz8UeuoDJJkaaoTFNOqv9S7SZfHtSlgKzS2c9U19
 jxavEY7ByRNgUQPJQYOR4LuQxiPl+vW37ZqXuUau+oOOCWEXrnw/ql/Ouxs8/6ne
 XhuCqqUP5/jcDTxCDmzwpJsSGVWEUbdA1d4uILFQn/1GSmUa4JmzKcnHUiBiQwNu
 gRn9dyGDhvGLehQfDwo+
 =KRAt
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-4.12/defconfig-arm64' of http://github.com/Broadcom/stblinux into next/arm64

Pull "Broadcom defconfig-arm64 changes for 4.12" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoCs defconfig updates for
4.12, please pull the following:

- Gerd enables the BCM2835 MMC driver which yields better performance than the
  default one (iProc)

* tag 'arm-soc/for-4.12/defconfig-arm64' of http://github.com/Broadcom/stblinux:
  arm64: set CONFIG_MMC_BCM2835=y in defconfig
2017-03-31 11:03:41 +02:00
Masahiro Yamada
9b3403ae56 arm64: drop non-existing vdso-offsets.h from .gitignore
Since commit a66649dab3 ("arm64: fix vdso-offsets.h dependency"),
include/generated/vdso-offsets.h is directly generated without
arch/arm64/kernel/vdso/vdso-offsets.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-30 19:29:30 +01:00
Shaokun Zhang
34d04f25a9 arm64: remove redundant header file in current.h
Commint 9d84fb27fa ("arm64: restore get_current() optimisation") has
removed read_sysreg() and asm/sysreg.h is redundant.

This patch removes asm/sysreg.h header file.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-30 19:15:37 +01:00
Mark Salter
335d2c2d19 arm64: fix NULL dereference in have_cpu_die()
Commit 5c492c3f52 ("arm64: smp: Add function to determine if cpus are
stuck in the kernel") added a helper function to determine if die() is
supported in cpu_ops. This function assumes a cpu will have a valid
cpu_ops entry, but that may not be the case for cpu0 is spin-table or
parking protocol is used to boot secondary cpus. In that case, there
is a NULL dereference if have_cpu_die() is called by cpu0. So add a
check for a valid cpu_ops before dereferencing it.

Fixes: 5c492c3f52 ("arm64: smp: Add function to determine if cpus are stuck in the kernel")
Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-03-30 17:14:32 +01:00
Arnd Bergmann
06d2157196 mvebu defconfig64 for 4.12 (part 1)
Update arm64 defconfig by adding MVPP2 for Marvell Armada 7K/8K and
 MVNETA and I2C_PXA for Armada 37xx.
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWNVU1SMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71fVYAJ9Yp1KsFB7n
 e2/64YGab3J5nQMFKwCeNQFTo4tZeU1Bnew1V83xfFpLXPQ=
 =pCdd
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-defconfig64-4.12-1' of git://git.infradead.org/linux-mvebu into next/arm64

Pull "mvebu defconfig64 for 4.12 (part 1)" from Gregory CLEMENT:

Update arm64 defconfig by adding MVPP2 for Marvell Armada 7K/8K and
MVNETA and I2C_PXA for Armada 37xx.

* tag 'mvebu-defconfig64-4.12-1' of git://git.infradead.org/linux-mvebu:
  arm64: defconfig: enable MVPP2
  arm64: defconfig: enable I2C_PXA
  arm64: defconfig: enable MVNETA
2017-03-30 17:45:35 +02:00
Arnd Bergmann
6b0eb18493 Amlogic: defconfig changes for v4.12
- enable PWM LEDs and LEDs default-on trigger
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJY3CX3AAoJEFk3GJrT+8ZlepMP+wZbCnO5F/UmxSWFVTmIkH8o
 Y+2VKAFQeHTWRLmOMWIRz3y34v1cbjm5NQ2AEZJTmPQ75Fm1Yl3OgFYh17EJOSiM
 L0iWSnFT1eDz+0uS/R2dySH7DSV4zaPoLSBUZArf559G1qmxoCRsAMJsvLVhRSp/
 jhmwsvSyGuY4ZqBy5+KXQe0keGzMyiGa972EPzjNURZIYwehvP8gj+Zmap6WY8EP
 Az9Us6v4DJEkYe6cT93ag57NPYm0R3H5ciZGhNvukM8nYvNm0+yobHKeWWMwTvlU
 DOwWqqmXVve3QM5LidEMn02vO+R+TYjNSyyUBfRLZ9oVxd83RcNA2pKJZg+lU5ba
 jgr4JPMHmq44lrx+SdFgd474/4L6mGWwEmVBW6Rie/aR306wGnxYKYDHeQTZSSjf
 KgjwyeZombLnXZcCJbC12cee+qFnqRbBSFEOohVl8ejsfZVmIjjrgo2Q2oBDwhXB
 y27iwV5yNL1bmm6sedvc1hwJcTPZyH+aoMxfz+cNxY6oqEtRvht+ZINTHfEL74vB
 2vCO9wgVpQj8tJIL6eMWyYX5QHOJUnpd7uokdDD6ZwlaTLO4Kz8+3aQxeQoMUAQ1
 ls9E8ROBytIZJULCHg5ZVX00fG0IbmT4C+PRbGVU2XwkOzUUXAcMYtCmfSxAK4NM
 aYOxdTYlS35/zX7K92oX
 =C+pZ
 -----END PGP SIGNATURE-----

Merge tag 'amlogic-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/arm64

Pull "Amlogic: defconfig changes for v4.12" from Kevin Hilman:

- enable PWM LEDs and LEDs default-on trigger

* tag 'amlogic-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: defconfig: enable the leds-pwm driver and default-on trigger
2017-03-30 17:44:46 +02:00
Arnd Bergmann
414d06ace9 Introduce generic TEE subsystem:
- the TEE subsystem itself
 - an OP-TEE driver using the subsystem
 - optee bindings
 - optee node for hi6220-hikey.dts
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCgAGBQJYx7QcAAoJELWwuEGXj+zT9P0P/Avy7nOnN8cupGz9nnjn8pwU
 ngG2MgIHN1wNQkqnQfAszdklXwDb3gdF42HnZsRtklOyzXHdsxttlm6lzun2nqbe
 XG8UM/lCSQDgnt0dZJuQw0XR4nd+j5E+8RZZPiKpOiYK3ObfpZNL8EbrlfFkQ6WF
 8uOnYr2WW0tOrwLlyjs8ITLdwcOtzyVafByop6Cetoez4xgY+7CkEs48VI775t+V
 wNOyQ0lwdSQSeBaUB0QmR/xo1070RUkaK1gkbAHNEy2pNHgira+qKMZZNrreoEp+
 hvVKeY1iLhj5AD8Oh6zdkCNC24Oz2rP1wGiNPjP1NhFKTGnnIUj1R9Q77GpP0AV3
 HoajAz0Z68auYerI0VB7EtB4UvnoFDXqvPxYaFiBi0U30O5lK4okj5MjSLHMzV8X
 gmMrm5IKesuNQ8J8Ixor9zyn9Lr1VYV34yoKFqxj5W8s8j7rTKKybHR58eL5fzOR
 y1uqYD4hPggb4QgDIb3I2d+Xg+yYNtlkOi5FLCVe+cXQTBnL58hLoqDbBD2kNLfr
 YPco0a/Ht8Q2l6gcWcCG5eLXKFsqNKhKA9BbuUDvIHIB9z+ZbYohQBQp7cH24Q3B
 TIDXBBVrypSqnhAXQ+UY3pPdK/IVWh2X3RRvFzV1eokIiK/cKg9epRidNUewkKGA
 8TSEvwKV7CHgb2PkvkO2
 =O5tZ
 -----END PGP SIGNATURE-----

Merge tag 'tee-drv-for-4.12' of git://git.linaro.org:/people/jens.wiklander/linux-tee into next/tee

Pull "generic TEE subsystem for v4.12"

Introduce generic TEE subsystem:
- the TEE subsystem itself
- an OP-TEE driver using the subsystem
- optee bindings
- optee node for hi6220-hikey.dts

* tag 'tee-drv-for-4.12' of git://git.linaro.org:/people/jens.wiklander/linux-tee:
  arm64: dt: hikey: Add optee node
  Documentation: tee subsystem and op-tee driver
  tee: add OP-TEE driver
  tee: generic TEE subsystem
  dt/bindings: add bindings for optee
2017-03-30 16:16:28 +02:00
Peter Zijlstra
19d436268d debug: Add _ONCE() logic to report_bug()
Josh suggested moving the _ONCE logic inside the trap handler, using a
bit in the bug_entry::flags field, avoiding the need for the extra
variable.

Sadly this only works for WARN_ON_ONCE(), since the others have
printk() statements prior to triggering the trap.

Still, this saves a fair amount of text and some data:

  text         data       filename
  10682460     4530992    defconfig-build/vmlinux.orig
  10665111     4530096    defconfig-build/vmlinux.patched

Suggested-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-03-30 09:37:20 +02:00
spjoshi@codeaurora.org
6c8583d6fe arm64: dts: msm8996: Add ADSP PIL node
Add ADSP node required for Qualcomm ADSP Peripheral Image Loader.

Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-03-29 13:43:52 -05:00
Bjorn Andersson
27414e41ba arm64: dts: qcom: pm8994: Add rtc node
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-03-29 13:43:52 -05:00
Bjorn Andersson
1b0c105b7f arm64: dts: apq8016-sbc: Add ramoops
Declare a ramoops memory segment to aid debugging for those without UART
access. Verified to carry console log when holding volume down for 15
seconds.

No memory region for ramoops-like support was found downstream, so the
arbitrarily picked region is the last MB of System RAM.

Cc: John Stultz <john.stultz@linaro.org>
Cc: Mart Raudsepp <leio@gentoo.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-03-29 13:41:47 -05:00
Harninder Rai
7a5d73479f arm64: dts: Add support for FSL's LS1088A SoC
LS1088A contains eight ARM v8 CortexA53 processor cores
with 32 KB L1-D cache and 32 KB L1-I cache

Features summary
 Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
  - Arranged as two clusters of four cores sharing a 1 MB L2 cache
  - Speed Up to 1.5 GHz
  - Support for cluster power-gating.
 Cache coherent interconnect (CCI-400)
  - Hardware-managed data coherency
  - Up to 700 MHz
 One 64-bit DDR4 SDRAM memory controller with ECC
 Data path acceleration architecture 2.0 (DPAA2)
 Three PCIe 3.0 controllers
 One serial ATA (SATA 3.0) controller
 Three high-speed USB 3.0 controllers with integrated PHY

 Following levels of DTSI/DTS files have been created for the LS1088A
  SoC family:

         - fsl-ls1088a.dtsi:
                 DTS-Include file for NXP LS1088A SoC.

         - fsl-ls1088a-qds.dts:
                 DTS file for NXP LS1088A QDS board.

         - fsl-ls1088a-rdb.dts:
                 DTS file for NXP LS1088A RDB board

Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>`
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-29 11:53:19 +08:00
Horia Geantă
85b85c5695 arm64: dts: ls1012a: add crypto node
LS1012A has a SEC v5.4 security engine.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-29 11:02:32 +08:00
Al Viro
92430dab36 arm64: switch to RAW_COPY_USER
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2017-03-28 18:23:24 -04:00
Al Viro
46583939b9 arm64: add extable.h
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2017-03-28 18:23:23 -04:00
Bjorn Andersson
90621b8044 arm64: dts: qcom: msm8916: Update hexagon node
It's necessary to reference the xo clock and cx supply, so specify these
in the node. Also move the Hexagon smd-edge into the hexagon node, to
enable SSR.

As cxo is not yet available we reference the fixed version of cxo for
now, which will work until proper power management is implemented.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-03-28 15:46:19 -05:00
avaneesh dwivedi
3f1802f888 arm64: dts: msm8996: Add SLPI SMP2P dt node.
Add smp2p support to communicate with slpi processor.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-03-28 15:46:18 -05:00
Stephen Boyd
8bfa6eae5a arm64: dts: qcom: Replace PMU compatible with a53 specific one
The PMU on msm8916 is for the cortex-a53 type CPU. Update the
compatible to the more specific one so we can get the a53
specific events out of the PMU.

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-03-28 15:46:08 -05:00
Bjorn Andersson
a2940f36a8 arm64: dts: qcom: msm8996: Fixup smp2p node
The SMEM state property name changes between the integration branch and
mainline, update to use the correct one.

Fixes: 2f45d9fcd5 ("arm64: dts: msm8996: Add SMP2P and APCS nodes")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-03-28 15:46:05 -05:00
jbrunet
9503062d65 ARM64: dts: meson-gxl: add spdif output pins
Add EE and AO domains pins for the spdif output to the gxl device tree.

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28 08:00:02 -07:00
jbrunet
c16fe9a1c7 ARM64: dts: meson-gxl: add i2s output pins
Add EE and AO domains pins for the i2s output clocks and data the gxl
device tree

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28 07:59:53 -07:00
jbrunet
07a4652f0e ARM64: dts: meson-gxbb: add spdif output pins
Add EE and AO domains pins for the spdif output to the gxbb device tree.

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28 07:59:43 -07:00
jbrunet
552b1e56d9 ARM64: dts: meson-gxbb: add i2s output pins
Add EE and AO domains pins for the i2s output clocks and data to the gxbb
device tree.

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28 07:59:27 -07:00
Neil Armstrong
1db3b92cb2 ARM64: dts: meson-gxbb: Add USB Hub GPIO hog
The ODroid-C2 on-board USB Hub needs to to have it's reset signal set to
high level in order to be enumerated by the USB Host Controller.

But this management must be part of the currently in-development Generic
Power Sequence patch that will allow a USB Controller driver to start and stop
a power sequence associated to the USB Bus.

In the meantime, a simple USB Hog will work to enable the USB Hub.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28 07:56:22 -07:00
Neil Armstrong
84412e4e85 ARM64: dts: meson-gxl: Add gpio-ranges properties
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28 07:56:00 -07:00
Neil Armstrong
18ae17bc51 ARM64: dts: meson-gxbb: Add gpio-ranges properties
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28 07:55:53 -07:00
Neil Armstrong
57ef579878 ARM64: dts: meson-gx: Add Mali nodes for GXBB and GXL
The same Mali-450 MP3 GPU is present in the GXBB and GXL SoCs.

The node is simply added in the meson-gxbb.dtsi file.

For GXL, since a lot is shared with the GXM that has a Mali-T820 IP, this
patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific
dtsi files.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[khilman: s/MALI/Mali in changelog]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28 07:48:27 -07:00
Icenowy Zheng
5313ea66a4 arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
Orange Pi PC 2 board features a OTG port like the one on older H3 Orange
Pi's, with PG12 pin being the id det pin and PL2 being the vbus driver
pin.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-27 13:44:52 +02:00
Andre Przywara
9d41bbb6e1 arm64: allwinner: h5: add support for the Orange Pi PC 2 board
The Orange Pi PC 2 is a typical single board computer using the
Allwinner H5 SoC. Apart from the usual suspects it features three
separately driven USB ports and a Gigabit Ethernet port.
Also it has a SPI NOR flash soldered, from which the board can boot
from. This enables the SBC to behave like a "real computer" with
built-in firmware.

Add the board specific .dts file, which includes the H5 .dtsi and
enables the peripherals that we support so far.

Reviewed-by: Rask Ingemann Lambertsen <rask@formelder.dk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: dropped all GPIO pinctrl nodes, change red LED gpio,
 change MMC cd to active-low, rename some node names to prevent
 underscores]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-27 13:44:40 +02:00
Andre Przywara
4e36de179f arm64: allwinner: h5: add Allwinner H5 .dtsi
The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses
Cortex-A53 cores instead.
Based on the now shared base .dtsi describing the common peripherals
describe the H5 specific nodes on top of that.
That symlinks in the sunxi-h3-h5.dtsi from the arch/arm tree.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: add H5 pinctrl compatible, and changes for my h3-h5 dtsi
 refactor, commit message changed to meet new arm64 naming scheme,
 drop H3 pinctrl compatible because of interrupt bank change, drop
 H3 ccu compatible because of clock change, drop ccu node as it come
 into h3-h5 dtsi]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-27 13:44:39 +02:00
Greg Kroah-Hartman
e47ff590cc Merge 4.11-rc4 into usb-next
This resolves a merge issue in the gadget code, and we want the USB
fixes in here as well.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-03-27 09:19:32 +02:00
Linus Torvalds
2056b7c7df ARM: SoC fixes for v4.11
- A couple of OMAP 4.11 regression fixes, including a boot regression for
   SmartReflex, hypervisor mode in thumb2 mode, and reference counting of
   device nodes
 
 - A fix for cpu_idle on at91
 
 - Minor DT fixes on across several platforms:
   sunxi, bcm53xx, at91, nsp, ns2, ux500, omap
 
 - A fix to correct an API change in the reset controllers
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIVAwUAWNWBrGCrR//JCVInAQJE/xAArSDx+6i7On53k3QfxkR1mONHrEOlXhlP
 VbTeBfkYtYB08Pgq99QVJE5qYK2N5w2664UNbgs+KKYnYJTNl0G6EW1l7oj+21M+
 xg3e6ctdfeztYeU34q7D2TxzP/EBRHdbpEuT+JHuQOWFYNfGAj2vSt2cdPUael/Q
 D4s4BgeM1dIOzN3z3AvuQpqIhLedVRFAGYAaalKXiwREYUVDgnqhHCPWChVnSQMR
 gnNDYcb5ZxCaELH9gkdVqyfdlScw9juKMg5v7e7KizhBUqOGBT0bguLC9Kfh3mDO
 tIJGwkuqWvc5tAKuAcGklIVOzP8Wtcq0ObrFzLczy6Waf+6aaQl5J8Uw85UR/zg4
 44AHzk++apXTCDlrRzQZIkvaN9TmOBr65qrW1rnqVN72FRS3arDuMV1rEFRdZy2x
 riXmJmENWo+sakst4fTS0QY+/GlPDB8Md4X++Vkl3DgWFgiiBTcPbJCEazsFVip+
 QQzWfXTSB98bCVUuYr5eZgMlPYHrd1ZQIbgzlzIkdUuZ4XCe4MGw88km6TqviBwf
 dduNKnFctkrLAgM3V8rXZBQsZqJHRDmpOfSZ+9XtGYggy83g5FLbkp9h6Ws66SbI
 KCgLzV0THCs/gKLMeDqFerO1xQzxN84pd+YKetnD1RU+5bo98DMUkqgFn+cZyCFA
 dlImlZcN7Pc=
 =zKIg
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:

 - a couple of OMAP 4.11 regression fixes, including a boot regression
   for SmartReflex, hypervisor mode in thumb2 mode, and reference
   counting of device nodes

 - a fix for cpu_idle on at91

 - minor DT fixes on across several platforms: sunxi, bcm53xx, at91,
   nsp, ns2, ux500, omap

 - a fix to correct an API change in the reset controllers

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
  arm64: dts: NS2: Add dma-coherent to relevant DT entries
  reset: fix optional reset_control_get stubs to return NULL
  ARM: sun8i: a23/a33: drop bl_en_pin GPIO pinmux in reference design DTSI
  ARM: dts: sun7i: lamobo-r1: Fix CPU port RGMII settings
  ARM: dts: NSP: GPIO reboot open-source
  ARM: at91: pm: cpu_idle: switch DDR to power-down mode
  ARM: dts: add the AB8500 clocks to the device tree
  ARM: dts: imx6sx-udoo-neo: Fix reboot hang
  ARM: sun8i: Fix the mali clock rate
  ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags
  ARM: dts: BCM5301X: Fix memory start address
  ARM: dts: BCM5301X: Fix UARTs on bcm953012k
  Revert "ARM: at91/dt: sama5d2: Use new compatible for ohci node"
  ARM: OMAP2+: Release device node after it is no longer needed.
  ARM: OMAP2+: Fix device node reference counts
  ARM: OMAP2+: Remove legacy gpmc-nand.c
  ARM: OMAP2+: gpmc-onenand: propagate error on initialization failure
  ARM: dts: am335x-pcm953: Fix legacy wakeup source binding
  ARM: omap2plus_defconfig: Enable INPUT_MOUSEDEV as loadable modules
  ARM: dts: am57xx-idk: tpic2810 is on I2C bus, not SPI
  ...
2017-03-24 14:32:21 -07:00
Neil Armstrong
ca02e3f9b1 ARM64: dts: meson-gxl: Add missing pinctrl pins groups
Add pinctrl pins nodes following the additions of missing pins in the pinctrl
driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-24 12:25:20 -07:00
Arnd Bergmann
0fa974b8b6 This pull request contains Broadcom ARM64-based SoCs Device Tree fixes for 4.11,
please pull the following:
 
 - Jon adds missing "dma-coherent" property to the Northstar 2 DTS include file
   in order to fix both performance and cache problems for: PCIe, Ethernet,
   PDC/mailbox, SATA3 and SDHCI
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJY0rXOAAoJEIfQlpxEBwcEcCwQAI6nyawZL32CW5cRKcDqHeVG
 l7bZJEdfcYA6TojvIGhdWh4VGSb2sLJsB7cU+eAtdHxI55sp1YR1HMEv5GBNthiq
 JKtwnVKWpaM6lbJGJnQwvGCzrGWSIXJH7KjPHh+Krb8ZV7GWQiJ3neEe3jh7Pp5u
 KEWIin22AowWo/5Hk8reEOoei9E+zer6Bo8YI2SVQ426epXnCocHzfaVIMq28310
 xzlhR8xFACoJTPJBJ8keyjL/9UYoge4Q1PM4VH89ti3juF4ELNGJP2yZyTbXWjOg
 gHDbQ13KWxE6xvCZbRLkiyBkIL5MZ8xKsP6ePqFtNU4STnPvnenWoEpBuY+8+lmz
 YOCoWf+TzyfvFV6BsnbnvBPE09tzeqtY43+kLOAsizqPY1+MzflDNW1MLBKRzQBV
 yGI6NhNB8wgKtCrYAGAd4O+Mb1GkGigw/C7l+/L68aBNqwy3pfPEM1zkobX7sBUi
 T+CjYQoF5ZUNx+p6cQfZFnr7ygC/iUyo7jODY9fTbCQ51PiTw1uMcOUmaV2DbQ2T
 Fq4jZRTVRubzBlCTNG1hRPqycGoXzjRS/uGKOLX5+XqRNKUBfFzy+XNoGqRlSO9n
 E6ef1ZbCO5GwxG6otgmlARHgCigSusKvfccQ9WWcB+1CegeCFSbyG1YzYkhQZ281
 te/nPRCmU/Uq0YvUoogd
 =5KXs
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-4.11/devicetree-arm64-fixes' of http://github.com/Broadcom/stblinux into fixes

Pull "Broadcom arm64 Device Tree fixes for 4.11" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoCs Device Tree fixes for 4.11,
please pull the following:

- Jon adds missing "dma-coherent" property to the Northstar 2 DTS include file
  in order to fix both performance and cache problems for: PCIe, Ethernet,
  PDC/mailbox, SATA3 and SDHCI

* tag 'arm-soc/for-4.11/devicetree-arm64-fixes' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2: Add dma-coherent to relevant DT entries
2017-03-24 17:51:50 +01:00
Andre Przywara
565fbac18e arm64: defconfig: add Allwinner USB PHY
The arm64 defconfig covers the Allwinner A64 SoC boards quite well,
but USB support is not enabled.
Add the PHY config symbol to allow defconfig kernels to use USB.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-24 16:43:02 +01:00
Herbert Xu
2e6d603e51 Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
Merging 4.11-rc3 to pick up md5 removal from /dev/random.
2017-03-24 21:58:58 +08:00
Shawn Guo
f006aaf7b1 arm64: dts: zte: add tvenc device for zx296718
It adds VOU tvenc device in zx296718.dtsi, so that boards with TV
connector can enable the support by changing 'status' in board DTS file.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2017-03-24 16:25:19 +08:00
Shawn Guo
25bd9d5e28 arm64: dts: zte: add vou and hdmi devices for zx296718
It adds VOU DPC device and enables HDMI support, which includes both
display and audio through SPDIF interface.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2017-03-24 16:25:12 +08:00
Jun Nie
25798d52b8 arm64: dts: zte: add mmc devices for zx296718
Add three mmc devices for zx296718 SoC, and enable the SD and eMMMC on
zx296718-evb board.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2017-03-24 16:16:50 +08:00
Shawn Guo
6d7e05ab8f arm64: dts: zte: remove zx296718 pll_vga clock
Rather than a fixed rate clock, pll_vga is a PLL can be programmed into
different freqencies.  Let's drop it from device tree and get it
registered from clock driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2017-03-24 16:16:50 +08:00
Neil Armstrong
e19e64aaf4 ARM64: dts: meson-gx: Prepend GX generic compatible like other nodes
Prepend the compatible strings with a GX generic name in nodes compatible with
the GXBB HW and keep the same scheme as other nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-23 12:25:26 -07:00
Neil Armstrong
932b3363c0 ARM64: dts: meson-gx: empty line cleanup
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-23 12:25:25 -07:00
Neil Armstrong
04b36df406 ARM64: dts: meson-gx: Finally move common nodes to GX dtsi
Since we know the GXBB and GXL/GXM share more hardware, we can safely move
the remaining peripheral nodes present in the GXBB dtsi to the common GX dtsi.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-23 12:25:25 -07:00
Martin Blumenstingl
e15d2774b8 ARM64: dts: meson-gxl: add support for the Khadas VIM board
The Khadas VIM series consists of two boards which are almost
identical:
They are both using the same GXL S905X SoC, 100Mbit/s ethernet
(through the SoC-internal PHY), 2GB DDR3 memory, a micro-SD card slot,
onboard eMMC, Broadcom based SDIO WIFI, 2x USB A and 1x USB Type-C (the
latter with OTG support). The red LED is driven by PWM_AO_B (which
allows dimming), while the blue LED is managed by the firmware.
The differences are:
- the VIM Pro has a 16GB eMMC module, while the VIM only has 8GB
- the VIM Pro uses an AP6255 a/b/g/n/ac WIFI module, while the VIM comes
  with an AP6212 b/g/n SDIO WIFI module
 (the Vim uses an 8GB eMMC module, while

The boards are based on Amlogic's GXL S905X P212 reference design, which
is why most of the functionality (all MMC controllers and power
sequences, IR remote input, the main UART, ADC and ethernet) is simply
inherited from meson-gxl-s905x-p212.dtsi.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-23 11:54:35 -07:00
Martin Blumenstingl
e98fd13413 ARM64: dts: amlogic: meson-gxl: add the missing PWM pins
This adds the new DT nodes for the missing PWM pins in the EE and AO
domain.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-23 11:54:14 -07:00
Thomas Petazzoni
66e5630284 arm64: defconfig: enable MVPP2
The MVPP2 network driver is used for the ARM64 Marvell Armada 7K and 8K
platforms, so enable it in the arm64 defconfig.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-23 17:50:13 +01:00
Thomas Petazzoni
6089471924 arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K
This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-23 17:46:23 +01:00
Gregory CLEMENT
85bee2af8a ARM64: dts: marvell: armada-3720 add RTC support
The Armada 3720 DB board has an RTC on the I2C bus. It's a PT7C4337A from
Pericom but which claims to be fully compatible with the ds1337.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-23 17:43:51 +01:00
Gregory CLEMENT
a12af1c207 ARM64: dts: marvell: armada-3720-db: Add phy for USB3
Now that the gpio expander is present in the dts, use it to add an USB3
PHY using one of these gpio as a regulator.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-23 17:43:06 +01:00
Gregory CLEMENT
e4afb4804d ARM64: dts: marvell: armada-37xx: Add clock resource for USB3
Now that clocks are available provide a clock resource for xhci node.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-23 17:43:02 +01:00
Gregory CLEMENT
86fcb2bca0 ARM64: dts: marvell: armada-37xx: Fix interrupt mapping for USB3
IRQ number for xhci controller was wrong, fix it.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-03-23 17:42:58 +01:00
Kefeng Wang
29d981217a arm64: drop unnecessary newlines in show_regs()
There are two unnecessary newlines, one is in show_regs, another
is in __show_regs(), drop them.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 14:20:41 +00:00
Ard Biesheuvel
d27cfa1fc8 arm64: mm: set the contiguous bit for kernel mappings where appropriate
This is the third attempt at enabling the use of contiguous hints for
kernel mappings. The most recent attempt 0bfc445dec was reverted after
it turned out that updating permission attributes on live contiguous ranges
may result in TLB conflicts. So this time, the contiguous hint is not set
for .rodata or for the linear alias of .text/.rodata, both of which are
mapped read-write initially, and remapped read-only at a later stage.
(Note that the latter region could also be unmapped and remapped again
with updated permission attributes, given that the region, while live, is
only mapped for the convenience of the hibernation code, but that also
means the TLB footprint is negligible anyway, so why bother)

This enables the following contiguous range sizes for the virtual mapping
of the kernel image, and for the linear mapping:

          granule size |  cont PTE  |  cont PMD  |
          -------------+------------+------------+
               4 KB    |    64 KB   |   32 MB    |
              16 KB    |     2 MB   |    1 GB*   |
              64 KB    |     2 MB   |   16 GB*   |

* Only when built for 3 or more levels of translation. This is due to the
  fact that a 2 level configuration only consists of PGDs and PTEs, and the
  added complexity of dealing with folded PMDs is not justified considering
  that 16 GB contiguous ranges are likely to be ignored by the hardware (and
  16k/2 levels is a niche configuration)

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 14:09:23 +00:00
Ard Biesheuvel
5bd4669471 arm64/mm: remove pointless map/unmap sequences when creating page tables
The routines __pud_populate and __pmd_populate only create a table
entry at their respective level which refers to the next level page
by its physical address, so there is no reason to map this page and
then unmap it immediately after.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 14:09:12 +00:00
Ard Biesheuvel
c0951366d4 arm64/mmu: replace 'page_mappings_only' parameter with flags argument
In preparation of extending the policy for manipulating kernel mappings
with whether or not contiguous hints may be used in the page tables,
replace the bool 'page_mappings_only' with a flags field and a flag
NO_BLOCK_MAPPINGS.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:55:51 +00:00
Ard Biesheuvel
141d1497aa arm64/mmu: add contiguous bit to sanity bug check
A mapping with the contiguous bit cannot be safely manipulated while
live, regardless of whether the bit changes between the old and new
mapping. So take this into account when deciding whether the change
is safe.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:55:35 +00:00
Ard Biesheuvel
eccc1bff1b arm64/mmu: ignore debug_pagealloc for kernel segments
The debug_pagealloc facility manipulates kernel mappings in the linear
region at page granularity to detect out of bounds or use-after-free
accesses. Since the kernel segments are not allocated dynamically,
there is no point in taking the debug_pagealloc_enabled flag into
account for them, and we can use block mappings unconditionally.

Note that this applies equally to the linear alias of text/rodata:
we will never have dynamic allocations there given that the same
memory is statically in use by the kernel image.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:55:21 +00:00
Ard Biesheuvel
e393cf40ae arm64/mmu: align alloc_init_pte prototype with pmd/pud versions
Align the function prototype of alloc_init_pte() with its pmd and pud
counterparts by replacing the pfn parameter with the equivalent physical
address.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:55:09 +00:00
Ard Biesheuvel
2ebe088b73 arm64: mmu: apply strict permissions to .init.text and .init.data
To avoid having mappings that are writable and executable at the same
time, split the init region into a .init.text region that is mapped
read-only, and a .init.data region that is mapped non-executable.

This is possible now that the alternative patching occurs via the linear
mapping, and the linear alias of the init region is always mapped writable
(but never executable).

Since the alternatives descriptions themselves are read-only data, move
those into the .init.text region.

Reviewed-by: Laura Abbott <labbott@redhat.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:54:50 +00:00
Ard Biesheuvel
28b066da69 arm64: mmu: map .text as read-only from the outset
Now that alternatives patching code no longer relies on the primary
mapping of .text being writable, we can remove the code that removes
the writable permissions post-init time, and map it read-only from
the outset.

To preserve the existing behavior under rodata=off, which is relied
upon by external debuggers to manage software breakpoints (as pointed
out by Mark), add an early_param() check for rodata=, and use RWX
permissions if it set to 'off'.

Reviewed-by: Laura Abbott <labbott@redhat.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:54:33 +00:00
Ard Biesheuvel
5ea5306c32 arm64: alternatives: apply boot time fixups via the linear mapping
One important rule of thumb when desiging a secure software system is
that memory should never be writable and executable at the same time.
We mostly adhere to this rule in the kernel, except at boot time, when
regions may be mapped RWX until after we are done applying alternatives
or making other one-off changes.

For the alternative patching, we can improve the situation by applying
the fixups via the linear mapping, which is never mapped with executable
permissions. So map the linear alias of .text with RW- permissions
initially, and remove the write permissions as soon as alternative
patching has completed.

Reviewed-by: Laura Abbott <labbott@redhat.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:54:19 +00:00
Ard Biesheuvel
aa8c09be7a arm64: mmu: move TLB maintenance from callers to create_mapping_late()
In preparation of refactoring the kernel mapping logic so that text regions
are never mapped writable, which would require adding explicit TLB
maintenance to new call sites of create_mapping_late() (which is currently
invoked twice from the same function), move the TLB maintenance from the
call site into create_mapping_late() itself, and change it from a full
TLB flush into a flush by VA, which is more appropriate here.

Also, given that create_mapping_late() has evolved into a routine that only
updates protection bits on existing mappings, rename it to
update_mapping_prot()

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:54:13 +00:00
Ard Biesheuvel
3b3c6c24de arm64: Revert "arm64: kaslr: fix breakage with CONFIG_MODVERSIONS=y"
This reverts commit 9c0e83c371, which
is no longer needed now that the modversions code plays nice with
relocatable PIE kernels.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-03-23 13:15:20 +00:00
Neil Armstrong
c34cd35ed9 ARM64: dts: meson-gxbb-odroidc2: Fix TFLASH VDD regulator GPIO line
The wrong GPIO line was provided here.

Fixes: ef8d2ffedf ("ARM64: dts: meson-gxbb: add MMC support")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-22 20:46:52 -07:00