Workaround for 60x1-B2 errata PCI#7.
Write-combining may be unreliable when chip operates in PCI-X mode,
so disable write-combining when in PCI-X mode.
Also, update the errata comments at the top of sata_mv,
and include a note about errata PCI#11.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Cosmetic change: replace .pio_mask=0x1f with .pio_mask=ATA_PIO4 everywhere.
Originally from Erik Inge Bolsø, now reworked for latest sata_mv.
Signed-off-by: Erik Inge Bolsø <knan-lkml@anduin.net>
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Prevent racing on the main interrupt mask during port_start and port_stop.
Otherwise, we end up with IRQs masked on inactive ports,
and hotplug insertions then get missed later on.
Found while debugging (out of tree) target mode operations,
but the bug is present and impacting mainline as well.
This patch should also be considered for -stable.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Revert most of commit 6be96ac1d5e4d913e1f48299db083ada5321803b2,
originally from Lennert Buijtenheck (Marvell) and Saeed Bishara (Marvell),
since that commit causes sata_mv to oops at startup on SOC "Kirkwood".
The SOC variants do not have the hpriv->irq_{cause,mask}_ofs registers,
so don't try to write to them!
This patch should also be considered for -stable.
Reported-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
On a timeout call a device specific handler early in the recovery so that
we can complete and process successful commands which timed out due to IRQ
loss or the like rather more elegantly.
[Revised to exclude the timeout handling on a few devices that inherit from
SFF but are not SFF enough to use the default timeout handler]
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
For Marvell SoC chips, the HDD LED does not blink when there is
disk I/O if NCQ is enabled. Add a quirk that enables blink mode for
the LED while NCQ is enabled on any port of a SoC host controller.
Normal LED function is restored when NCQ is not enabled on any port.
The code to enable the blink mode is based on earlier code
and suggestions from Frans Pop, Saeed Bishara, and possibly others.
Signed-off-by: Mark Lord <mlord@pobox.com>
Tested-by: Frans Pop <elendil@planet.nl>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Enable use of the "all ports" IRQ coalescing optimization
for GEN_II / GEN_IIE chips that have dual host-controllers (8-ports).
Currently only the 6081 chip qualifies, but other chips may come along someday.
Rather than each half of the chip having to satisfy a local set of coalescing thresholds,
use of this feature groups all ports together under a single set of thresholds.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Add IRQ coalescing to sata_mv (off by default).
This feature can reduce total interrupt overhead for RAID setups
in some situations, by deferring the interrupt signal until one or both of:
a) a specified io_count (completed SATA commands) is achieved, or
b) a specified time interval elapses after an IO completion.
For now, module parameters are used to set the irq_coalescing_io_count
and irq_coalescing_usecs (timeout) globally. These may eventually
be supplemented with sysfs attributes, so that thresholds can be set
on-the-fly and on a per-chip (or even per-host_controller) basis.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Various cosmetic changes in preparation for the IRQ coalescing feature.
Note that the various MV_IRQ_COAL_* definitions are restored/renamed
in the folloup patch which adds IRQ coalescing to the driver.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This is initially needed to work around NCQ errata,
whereby the READ_LOG_EXT command sometimes fails
when issued in the traditional (sff) fashion.
Portions of this code will likely be reused for
implementation of the target mode feature later on.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This is necessary for use with the upcoming "mv_qc_issue_fis()" patch,
but is being added separately here for easier code review.
When using command issue via the "mv_qc_issue_fis()" mechanism,
the initial ATA_BUSY bit does not show in the ATA status (shadow) register.
This can confuse libata! So here we add a hook to fake ATA_BUSY
for that situation, until the first time a BUSY, DRQ, or ERR bit is seen.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
so that it doesn't miss any protocols. Handle future cases where a
qc is specially marked for polled issue or where a particular chip
version prefers interrupts over polling for PIO.
This mimics the polling decision logic from ata_sff_qc_issue().
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This also gets rid of any need for mv_mode_filter().
Using basic DMA on GEN_IIE requires setting an undocumented
bit in an undocumented register. For safety, we clear that
bit again when switching back to EDMA mode.
To avoid a performance penalty when switching modes,
we cache the register in port_priv, as already done for other regs.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Maintain a local (mv_port_priv) cache of frequently accessed registers,
to avoid having to re-read them (very slow) on every transistion
between EDMA and non-EDMA modes. This speeds up things like
flushing the drive write cache, and anything using basic DMA transfers.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Remove redundant code left over from the earlier patch 04/07.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Try and avoid unnecessary reconfiguration of the EDMA config register
on every single non-EDMA I/O operation, by moving the call to
mv_edma_cfg() into mv_stop_edma(). It must then also be invoked
from mv_hardreset() and from mv_port_start().
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Add ATAPI support to sata_mv, using sff DMA for GEN_II chipsets,
and plain old PIO for GEN_IIE.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Fix mv_fill_sg() to zero out the reserved word (required for ATAPI),
and to include a memory barrier. This may also help with problems
reported by Jens on the PPC platform.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Update the logic in ata_qc_from_tag() to match that used
in similar places elsewhere in libata.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Rearrange logic in mv_qc_issue() to handle protocols
other than ATA_PROT_DMA, ATA_PROT_NCQ, and ATA_PROT_PIO.
This is in preparation for later enabling ATAPI support.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Rearrange mv_start_dma() and friends, in preparation for adding
non-EDMA DMA modes, and non-EDMA interrupts, to the driver.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Clean up the chipset GENeration FLAGS, and rename them
for consistency with other uses of GEN_XX within sata_mv.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Fix a (rare) race condition in mv_interrupt() when using MSI.
The value of hpriv->main_irq_mask_addr can change on on the fly,
and without this patch we could end up writing back a stale copy
to the hardware.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
For some reason, sata_mv doesn't clear interrupt status during init
when it's running on an SoC host adapter. If the bootloader has
touched the SATA controller before starting Linux, Linux can end up
enabling the SATA interrupt with events pending, which will cause the
interrupt to be marked as spurious and then be disabled, which then
breaks all further accesses to the controller.
This patch makes the SoC path clear interrupt status on init like in
the non-SoC case.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Fix chip type for the Highpoint RocketRAID 1740 and 1742 PCI cards.
These really do have Marvell 6042 chips on them, rather than the 5081 chip.
Confirmed by multiple (two) users (for the 1740), and by examining
the product photographs from Highpoint's web site.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Enable reliable use of Message-Signaled Interrupts (MSI) in sata_mv
by masking further chip interrupts within the main interrupt handler.
Based upon a suggestion by Grant Grundler.
MSI is working reliably in all of my test systems here now.
Signed-off-by: Mark Lord <mlord@pobox.com>
Reviewed-by: Grant Grundler <grundler@google.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
I noticed that during initialization sata_mv.c assumes that the main
interrupt mask has its default value of 0. The function
mv_platform_probe(..) initializes a shadow irq mask with 0 assuming
that's the value of the controller's register. Now
mv_set_main_irq_mask(..) only writes the controller's register if the
new value differs from the "shadowed" value. This is fatal when trying
to disable all interrupts in mv_init_host(..), i.e. the following
function call does not write anything to the main irq mask register:
mv_set_main_irq_mask(host, ~0, 0);
The effect I see on my machine (QNAP TS-109 II) with booting via kexec
(with Linux as a 2nd-stage boot loader) is that if the sata_mv module
was still loaded when performing kexec, then the new kernel's sata_mv
module starts up with interrupts enabled. This results in an unhandled
IRQ and breaks the boot process.
The unhandled interrupt itself might also be fixed by Lennert's patch
proposed at http://markmail.org/message/kwvzxstnlsa3s26w which I did not
try yet.
However I still propose to additionally initialize the shadow variable
with the current contents of the main irq mask register to get both in
sync and allow proper disabling the main irq mask. This fixes the
unhandled irq on my machine.
Signed-off-by: Thomas Reitmayr <treitmayr@devbase.at>
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Remove unneeded nsect restriction from GenII NCQ path,
and improve comments to explain why this is not a problem.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Remove silly read-modify-write sequences when clearing interrupts
in hc_irq_cause. This gets rid of unneeded MMIO reads, resulting in
a slight performance boost when switching between EDMA and non-EDMA
modes (eg. for cache flushes).
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Fix a longstanding bug for the 8-port Marvell Sata controllers (508x/6081),
where accesses to the upper 4 ports would cause lost-interrupts / timeouts
for the lower 4-ports. With this patch, the 6081 boards should finally be
reliable enough for mainstream use with Linux.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Logically, SCR access ops should take @link; however, there was no
compelling reason to convert all SCR access ops when adding @link
abstraction as there's one-to-one mapping between a port and a non-PMP
link. However, that assumption won't hold anymore with the scheduled
addition of slave link.
Make SCR access ops per-link.
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
The SoC sata port is based on the 7042/6042 devices (Gen IIE). This patch
will fix various issues when working with PMP and/or NCQ.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
sata_mv allowed issuing two DMA commands concurrently which the
hardware allows. Unfortunately, libata core layer isn't ready for
this yet and spews ugly warning message and malfunctions on this.
Don't allow concurrent DMA commands for now.
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
There is a miniscule chance that two separate host controllers
might be in sata_mv at the same time and manage to decrement
the static limit_warnings variable below zero.
Fix the comparison to deal with it.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Chip errata sometimes prevents reliable use of PIO commands which involve
more than a single DRQ (data request). In normal operation, libata should
not generate such PIO commands (uses DMA instead), but they could be sent
in via SG_IO from userspace.
A full workaround might be to break up such commands into sequences
of single DRQ ones, but that's just way too complex for something
that doesn't normally happen in real life.
So, allow the attempt (it often works, despite the errata),
but log the event for reference when somebody screams.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
The early chipsets cannot safely handle Async Notification (AN),
but 6041/6081 chip revision "C0" (and newer) can handle it.
So allow AN for "C0" and higher.
This enables use of hotplug on PMP ports for the 6041/6081 PCI Rev.9 chips.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
The handling for PHY_MODE4 was originally just cloned from the
Marvell proprietary driver (with their blessing).
But we can do better than that.
Tidy things up with some judicious mask definitions, to improve maintainability.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
The 5182 System-On-Chip (SOC) variant wants certain lower
bits to be cleared on any write to the PHY_MODE3 register.
If/when support is added for other SOC variants, we'll need
some way to uniquely identify the 5182, and not perform this
workaround for the others.
But for now, it is the only SOC variant we support here.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
The "B2" variant of the 6041/6081 (genII) chips requires
that the PHY_MODE3 register be rewritten after any write
to PHY_MODE4.
This fixes a regression introduced by an earlier patch.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
The only public release of the 6042/7042 chips was/is revision "B0".
Remove code that attempted to deal with earlier, non-released revs.
This matches the logic of the current Marvell "proprietary" driver.
Also, bump up the sata_mv version number, to reflect this batch of erratas.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Fix and update the errata handling for the PHY_MODEx registers.
This improves receiver noise tolerance, among other things.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Convert the System-on-Chip flag from a host flag to an hpriv flag,
for better consistency with other chip-rev flags, and for easier use
in errata fixes etc.
Also change the related "HAS_PCI()" into "!IS_SOC()" for better consistency
of naming/use (everything else SOC-related already uses "SOC").
There are no functionality changes in this patch.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Check for an empty request queue before stopping EDMA after a FBS-NCQ error,
as per recommendation from the Marvell datasheet.
This ensures that the EDMA won't suddenly become active again
just after our subsequent check of the empty/idle bits.
Also bump DRV_VERSION.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Part five of simplifying/fixing handling of the main_irq_mask register
to resolve unexpected interrupt issues observed in 2.6.26-rc*.
Keep a cached copy of the main_irq_mask so that we don't have
to stall the CPU to read it on every pass through mv_interrupt.
This significantly speeds up interrupt handling, both for sata_mv,
and for any other driver/device sharing the same PCI IRQ line.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Part four of simplifying/fixing handling of the main_irq_mask register
to resolve unexpected interrupt issues observed in 2.6.26-rc*.
Ignore masked IRQs in mv_interrupt().
This prevents "unexpected device interrupt while idle" messages.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Part three of simplifying/fixing handling of the main_irq_mask register
to resolve unexpected interrupt issues observed in 2.6.26-rc*.
Partially fix a reported bug whereby we sometimes miss seeing drives on
a port-multiplier, as reported by Gwendal Grignou <gwendal@google.com>.
The problem was that we were receiving unexpected interrupts
during EH from POLLed commands while accessing port-multiplier registers.
These unexpected interrupts can be prevented by masking the DONE_IRQ bit
for the port whenever not operating in EDMA mode.
Also fix port_stop() to mask all port interrupts.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Part two of simplifying/fixing handling of the main_irq_mask register
to resolve unexpected interrupt issues observed in 2.6.26-rc*.
Consolidate all updates of the host main_irq_mask register
into a single function. This simplifies maintenance,
and also prepares the way for caching it (later).
No functionality changes in this update.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Part one of simplifying/fixing handling of the main_irq_mask register
to resolve unexpected interrupt issues observed in 2.6.26-rc*.
Don't blindly enable port IRQs at host init time.
Instead, enable only the bits that we want,
which in this case is simply the PCI_ERR bit.
The per-port bits can wait until the ports are reset/probed for devices.
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
