Commit Graph

17 Commits

Author SHA1 Message Date
Paul Walmsley
b7edabfe84 riscv: defconfig: align RV64 defconfig to the output of "make savedefconfig"
Align the RV64 defconfig to the output of "make savedefconfig" to
avoid unnecessary deltas for future defconfig patches.  This patch
should have no runtime functional impact.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-31 12:26:10 -07:00
Loys Ollivier
bbc5dc5155 riscv: defconfig: enable SOC_SIFIVE
Enable SOC_SIFIVE so the default upstream config is bootable on the SiFive
Unleashed Board.
And have basic support for future boards based on the same SoC.

Signed-off-by: Loys Ollivier <lollivier@baylibre.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
[paul.walmsley@sifive.com: updated to apply]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-07-01 13:20:05 -07:00
Anup Patel
6dd91e0eac RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS
This patch enables NO_HZ_IDLE (idle dynamic ticks) and HIGH_RES_TIMERS
(hrtimers) in RV32 and RV64 defconfigs.

Both of the above options are enabled by default for architectures
such as x86, ARM, and ARM64.

The idle dynamic ticks helps use save power by stopping timer ticks
when the system is idle whereas hrtimers is a much improved timer
subsystem compared to the old "timer wheel" based system.

This patch is tested on SiFive Unleashed board and QEMU Virt machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-07-01 13:04:54 -07:00
Atish Patra
ff8391e1b7 RISC-V: defconfig: enable MMC & SPI for RISC-V
Currently, riscv upstream defconfig doesn't let you boot
through userspace if rootfs is on the SD card.

Let's enable MMC & SPI drivers as well so that one can boot
to the user space using default config in upstream kernel.

While here, enable automatic mounting of devtmpfs to simplify
kernel testing with minimal root filesystems. (pjw)

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
[paul.walmsley@sifive.com: mention the DEVTMPFS_MOUNT change in the
 patch description]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-06-26 10:27:49 -07:00
Kevin Hilman
3b025f2bc9 RISC-V: defconfig: enable clocks, serial console
Enable PRCI clock driver and serial console by default, so the default
upstream defconfig is bootable to a serial console.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-06-11 08:00:20 -07:00
Anup Patel
1b937e8faa
RISC-V: Add separate defconfig for 32bit systems
This patch adds rv32_defconfig for 32bit systems. The only
difference between rv32_defconfig and defconfig is that
rv32_defconfig has  CONFIG_ARCH_RV32I=y.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-04-09 09:42:49 -07:00
Palmer Dabbelt
2a200fb9fb
RISC-V: defconfig: Add CRYPTO_DEV_VIRTIO=y
This allows acceleration of cryptography inside QEMU.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-23 14:09:01 -08:00
Alistair Francis
e4cf9e47ab
RISC-V: defconfig: Enable Generic PCIE by default
Enable generic PCIe by default in the RISC-V defconfig, this allows us
to use QEMU's PCIe support out of the box.  CONFIG_RAS=y is
automatically selected by generic PCIe, so it has been dropped from
the defconfig.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
[Palmer: Split out PCIE_XILINX and CRYPTO_DEV_VIRTIO]
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-23 14:07:46 -08:00
Palmer Dabbelt
a37ead8f2e
RISC-V: defconfig: Move CONFIG_PCI{,E_XILINX}
eb01d42a77 ("PCI: consolidate PCI config entry in drivers/pci")
reorganized the PCI-related Kconfig entries and resulted in a diff in
our defconfig.  This simply removes the diff.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-23 12:59:17 -08:00
Anup Patel
2b3f786408
RISC-V: defconfig: Enable RISC-V SBI earlycon support
This patch enables RISC-V SBI earlycon support in default defconfig
so that we can use "earlycon=sbi" in kernel parameters for early
debug prints.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-17 10:23:46 -08:00
Anup Patel
4ab49461d9
RISC-V: defconfig: Enable printk timestamps
The printk timestamps are very useful information to visually see
where kernel is spending time during boot. It also helps us see
the timing of hotplug events at runtime.

This patch enables printk timestamps in RISC-V defconfig so that
we have it enabled by default (similar to other architectures
such as x86_64, arm64, etc).

Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-11-12 17:16:10 -08:00
Anup Patel
ba1f0d9557
RISC-V: refresh defconfig
This patch updates defconfig using savedefconfig on Linux-4.19.  It is
intended to have no functional change.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-11-01 17:04:07 -07:00
Christoph Hellwig
8237f8bc4f
irqchip: add a SiFive PLIC driver
Add a driver for the SiFive implementation of the RISC-V Platform Level
Interrupt Controller (PLIC).  The PLIC connects global interrupt sources
to the local interrupt controller on each hart.

This driver is based on the driver in the RISC-V tree from Palmer Dabbelt,
but has been almost entirely rewritten since, and includes many fixes
from Atish Patra.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
[Binding update by Palmer]
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-13 08:31:32 -07:00
Palmer Dabbelt
24a130ccfe
RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig
The SBI exists on all RISC-V systems, so there's no reason not to
compile this driver in.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-06-11 09:16:24 -07:00
Zong Li
4a632cec88
RISC-V: Enable module support in defconfig
Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-04-02 20:00:56 -07:00
Karsten Merker
33c57c0d3c
RISC-V: Add a basic defconfig
This patch provides a basic defconfig for the RISC-V
architecture that enables enough kernel features to run a
basic Linux distribution on qemu's "virt" board for native
software development. Features include:

- serial console
- virtio block and network device support
- VFAT and ext2/3/4 filesystem support
- NFS client and NFS rootfs support
- an assortment of other kernel features required for
  running systemd

It also enables a number of drivers for physical hardware
that target the "SiFive U500" SoC and the corresponding
development platform.  These include:

- PCIe host controller support for the FPGA-based U500
  development platform (PCIE_XILINX)
- USB host controller support (OHCI/EHCI/XHCI)
- USB HID (keyboard/mouse) support
- USB mass storage support (bulk and UAS)
- SATA support (AHCI)
- ethernet drivers (MACB for a SoC-internal MAC block, microsemi
  ethernet phy, E1000E and R8169 for PCIe-connected external devices)
- DRM and framebuffer console support for PCIe-connected
  Radeon graphics chips

Signed-off-by: Karsten Merker <merker@debian.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-07 15:14:36 -08:00
Palmer Dabbelt
fbe934d69e RISC-V: Build Infrastructure
This patch contains all the build infrastructure that actually enables
the RISC-V port.  This includes Makefiles, linker scripts, and Kconfig
files.  It also contains the only top-level change, which adds RISC-V to
the list of architectures that need a sed run to produce the ARCH
variable when building locally.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:49 -07:00