Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
nvc0_graph_ctor() would only let the graphics engine be enabled if its
oclass has a proper microcode linked to it. This prevents GR from being
enabled at all on chips that rely exclusively on external firmware, even
though such a use-case is valid.
Relax the conditions enabling the GR engine to also include the case
where an external firmware has also been loaded.
Also switch to external firmware if the graph class has no microcode
linked to it.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add a simple FB device for GK20A, as well as a RAM implementation
suitable for chips that use system memory as video RAM.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This set of commits contains a couple of fixes to existing panel drivers
and support for some new panels.
One commit touches the DRM core in that in modifies the MIPI DSI support
to hook up the shutdown function so that drivers can provide code that's
run on shutdown. This is used by a subsequent commit to make the simple
panel driver power off the backlight on shutdown.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJTlYqjAAoJEN0jrNd/PrOhnWUQAKbNwzzfIaUXVwZwWSSJFeGT
91x2ZDbI51tJKvGG8tIXKaRfkw2bngvdx+rGiPncgBtw75R4/S2MPypKU3osxKUf
QSf8PptHNJ+wGyIZJDlpP91t6gZ89U/qWEvcMCX8b6me9LR228kaEd4rQ/wChHso
D99h7Zlhb3UeUPd63BTCyPEbXyEVrgUQn1P2b72hYCS2lpR+2SpLcpSvqwIz5ZlW
iRBkXr2ME/aDI0+vGMlIQm7zCijVbaWRF/N3v+/uu5IxhCQhwNlkcWGVuIzABl7P
BDaXbnsZSXsFopdB/S2zgpRRJcRfccVpwCCHQqAuOSej522LxfL7sz7vD48PqDHi
vzyNk46YFe5n1Ov35m1aE/VTi/mtU7vcwKkUQX8EfS9dDe0eF6mIugng7CmOaKCf
Krd/wDFVSsbRhCDzogQVwylPQtOQ76oqFhSCQwTvl4PM0SOu+KtmUyO2xOcSv34/
uP/5rVaSww3qkn6hnW53IRJcEdwFV3IwbdkV9dwKLA5WWtHLiHiZd8F9viW7tKRl
UEA38UIWivkfhbSIwHMzmUlUEcBAHitlZg3N5fb1OHQT/rJGD3wNmvJNQC3vG3ej
1os7D8V7nBID6ml/oYkUZSmcgqN7ywz5ZtSn4hJm9+uwie10wn36Wv4iYbT7SAsm
nUFDBceAAN7QplgTx33m
=PWCS
-----END PGP SIGNATURE-----
Merge tag 'drm/panel/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/panel: Changes for v3.16-rc1
This set of commits contains a couple of fixes to existing panel drivers
and support for some new panels.
One commit touches the DRM core in that in modifies the MIPI DSI support
to hook up the shutdown function so that drivers can provide code that's
run on shutdown. This is used by a subsequent commit to make the simple
panel driver power off the backlight on shutdown.
* tag 'drm/panel/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/panel: simple - Add AUO B133XTN01 panel support
drm/panel: simple - Disable panel on shutdown
drm/panel: add support for EDT ET057090DHU panel
drm/panel: Add support for EDT ETM0700G0DH6 and ET070080DH6 panels
drm/panel: ld9040: add power control sequence
drm/panel: s6e8aa0: silence array overflow warning
drm/dsi: Support device shutdown
The majority of these changes are a slew of cleanups across the board.
A more noteworthy change is the addition of drm_dev_set_unique() and the
conversion of the Tegra DRM driver to use it. This allows us to get rid
of the host1x drm_bus implementation. Other USB and platform drivers can
be changed in a similar way. Unfortunately for most PCI devices there is
some userspace that relies on the old functionality and cannot be as
easily converted.
HDMI and hardware cursor support is added for Tegra124. The SOR output
gains support for exposing CRCs via debugfs, which can be used for
automated testing. Many values that were hardcoded in the SOR/eDP code
are now computed at runtime to increase compatibility with more devices.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJTlYhCAAoJEN0jrNd/PrOhsFkP/0KvTZsxeRloi/qmYjDqvYkO
SIL37i4AW/Wg5fLZ6WurQsZKT+LkE2E8a0xAaXtTbr8eyRTiXU39aY1OeYCSeaQ3
C50fEnIeGkMR/n4ijwR1ZcGVpCAcpREE2yePIshGfOeHmJ4CB6QewQ52H/BjH97r
BFq+8ZNtoiVrRpygD5PLfq+8UwikplIdSh+GjuAW/bp4YHXUPBDUlMUlfRUP+eEZ
7vLknX5zCugvXLMO6OQqyLkZKTpoxV+iV1chY3W3O7qNHHhKTbjQcpL3OleUH+Pc
v8AqfXmidZK5h9IMlWU9eWWB2SWCbsxkBGOQfurv8rwNio/P8XePzhJD/xuWFIIn
c/0yqFTAitqmynwzwzxamfzOITgN1D88C2ae3Z/DF14hPN1ZZg0rWFlDRax45Wx/
bxcZKsPRRP5gANyEXzvl5B51d1yT8V9KSKOHJKp7OAujoKJ3H5i3+3c0OeR/BZd6
IRt1NrdtpL7B4sPBkWxAyDYNYlsj35c6757kGgXSjMxaPkQQL+ORcOCsCRal3UAp
B1FdWk9CuTEiQmpYOwA5S+sFaUtReux2DC6CyVYc5KGmojTHrAg2T+c3WfNEaZGI
NeYL5kPK70/c1du0IBwPPq/9L4LcUAz7e9Nd3i8nCvA0osPbj8p/C76LvMrYopxI
cX8uqOVCmmpZ5vheqMhd
=OwgD
-----END PGP SIGNATURE-----
Merge tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.16-rc1
The majority of these changes are a slew of cleanups across the board.
A more noteworthy change is the addition of drm_dev_set_unique() and the
conversion of the Tegra DRM driver to use it. This allows us to get rid
of the host1x drm_bus implementation. Other USB and platform drivers can
be changed in a similar way. Unfortunately for most PCI devices there is
some userspace that relies on the old functionality and cannot be as
easily converted.
HDMI and hardware cursor support is added for Tegra124. The SOR output
gains support for exposing CRCs via debugfs, which can be used for
automated testing. Many values that were hardcoded in the SOR/eDP code
are now computed at runtime to increase compatibility with more devices.
* tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux: (47 commits)
drm/tegra: sor - Remove obsolete comment
drm/tegra: sor - Enable only the necessary number of lanes
drm/tegra: sor - Power on only the necessary lanes
drm/tegra: sor - Do not program interlaced mode registers
drm/tegra: sor - Do not hardcode link speed
drm/tegra: sor - Do not hardcode number of blank symbols
drm/tegra: sor - Don't hardcode link parameters
drm/tegra: sor - Change power down ordering
drm/tegra: sor - Fix copy/paste error
drm/tegra: sor - Remove pixel clock rounding
drm/tegra: sor - Make debugfs setup consistent
drm/tegra: sor - Recursively remove debugfs tree
drm/tegra: dp - Mark the connector as hotplug capable
drm/tegra: dp - Implement hotplug detection in work queue
drm/tegra: Add hardware cursor support
drm/tegra: Remove host1x drm_bus implementation
drm: Document how to register devices without struct drm_bus
drm: Add device registration documentation
drm: Introduce drm_dev_set_unique()
gpu: host1x: Rename internal functions for clarity
...
This panel is used by nyan-big and can be supported by the simple-panel
driver.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
[treding@nvidia.com: add device tree binding document]
Signed-off-by: Thierry Reding <treding@nvidia.com>
According to the DP specification the disparity of the first symbol
should always be negative. It is therefore safe to assume that panels
will conform to that and therefore parameterizing this field should
never be necessary.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The number of HBLANK and VBLANK symbols can be computed at runtime so
that they can be set appropriately depending on the video mode and DP
link.
These values are used by the packet generation logic to determine how
many audio samples can be transferred during the blanking intervals.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The currently hardcoded link parameters don't work on all eDP panels, so
compute the parameters at runtime depending on the mode and panel type
to allow the driver to cope with a wider variety of panels.
Note that the number of bits per pixel of the panel is still hardcoded,
but this can be addressed in a separate patch.
This is largely based on a patch by Stéphane Marchesin but the algorithm
was largely rewritten to be more readable and concise.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Lanes are powered up in decreasing order. Power them down in increasing
order for consistency.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The comment above mentions link A/B but this isn't what the code does,
so let's fix that.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The code currently rounds up the clock to the next MHZ, which is
rounding up a 69.5MHz clock to 70MHz on my machine. This in turn
prevents the display from syncing. Removing this rounding fixes eDP
for me.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
> Bunch of stuff for 3.16 still:
> - Mipi dsi panel support for byt. Finally! From Shobhit&others. I've
> squeezed this in since it's a regression compared to vbios and we've
> been ridiculed about it a bit too often ...
> - connection_mutex deadlock fix in get_connector (only affects i915).
> - Core patches from Matt's primary plane from Matt Roper, I've pushed the
> i915 stuff to 3.17.
> - vlv power well sequencing fixes from Jesse.
> - Fix for cursor size changes from Chris.
> - agpbusy fixes from Ville.
> - A few smaller things.
>
* tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel: (32 commits)
drm/i915: BDW: Adding missing cursor offsets.
drm: Fix getconnector connection_mutex locking
drm/i915/bdw: Only use 2g GGTT for 32b platforms
drm/i915: Nuke pipe A quirk on i830M
drm/i915: fix display power sw state reporting
drm/i915: Always apply cursor width changes
drm/i915: tell the user if both KMS and UMS are disabled
drm/plane-helper: Add drm_plane_helper_check_update() (v3)
drm: Check CRTC compatibility in setplane
drm/i915: use VBT to determine whether to enumerate the VGA port
drm/i915: Don't WARN about ring idle bit on gen2
drm/i915: Silence the WARN if the user tries to GTT mmap an incoherent object
drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS
drm/i915: Enable interrupt-based AGPBUSY# enable on 85x
drm/i915: Flip the sense of AGPBUSY_DIS bit
drm/i915: Set AGPBUSY# bit in init_clock_gating
drm/i915/vlv: add pll assertion when disabling DPIO common well
drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_well
drm/i915/vlv: re-order power wells so DPIO common comes after TX
drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well
...
Other output drivers set up debugfs slightly differently. Bring the SOR
driver in line with those for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Removing only the root directory will fail when there are still files in
it. Instead of manually removing all files, remove the whole directory
recursively.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Doing so allows the hotplug events generated by the connector to be
properly handled by the DRM poll helpers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Calling the drm_helper_hpd_irq_event() helper can sleep, so instead of
invoking it directly from the interrupt handler, schedule a work queue
and run it from there.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable hardware cursor support on Tegra124. Earlier generations support
the hardware cursor to some degree as well, but not in a way that can be
generically exposed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DRM core can now cope with drivers that don't have an associated
struct drm_bus, so the host1x implementation is no longer useful.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Describe how devices are registered using the drm_*_init() functions.
Adding this to docbook requires a largish set of changes to the comments
in drm_{pci,usb,platform}.c since they are doxygen-style rather than
proper kernel-doc and therefore mess with the docbook generation.
While at it, mark usage of drm_put_dev() as discouraged in favour of
calling drm_dev_unregister() and drm_dev_unref() directly.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a helper function that allows drivers to statically set the unique
name of the device. This will allow platform and USB drivers to get rid
of their DRM bus implementations and directly use drm_dev_alloc() and
drm_dev_register().
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra124 is mostly backwards-compatible with Tegra114. However, Tegra124
supports a few more features (e.g. interlacing, ...). Introduce a new
compatible string and TMDS tables to cope with these differences.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Accessing the CRC debugfs file will hang the system if the SOR is not
enabled, so make sure that it is stays enabled until the CRC has been
read.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In some cases the pixel clock used to not be correct, which is why it
had to be recomputed. It turns out that the reason why it wasn't correct
is that it was used wrongly. If used correctly there's not need for the
recomputation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The shift clock divider is highly dependent on the type of output, so
push computation of it down into the output drivers. The old code used
to work merely by accident.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Program the shift clock divider in tegra_crtc_setup_clk() since that's
where the divider is computed, so passing it around can be avoided.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Assert the DSI controller's reset when the driver is unloaded to reduce
power consumption and to put the controller into a known state for
subsequent driver reloads.
Signed-off-by: Thierry Reding <treding@nvidia.com>
To prevent the enable or disable operations to potentially be run
multiple times, add guards to return early when the output is already
in the targetted state.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The packet sequencer needs to be programmed depending on the video mode
of the attached peripheral. Add support for non-burst video modes with
sync events (as opposed to sync pulses) and select either sequence
depending on the video mode.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DSI controllers are powered by a (typically 1.2V) regulator. Usually
this is always on, so there was no need to support enabling or disabling
it thus far. But in order not to consume any power when DSI is inactive,
give the driver a chance to enable or disable the supply as needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
A bunch of registers are initialized to 0 upon during driver probe. It
turns out that none of these are actually needed, so they can simply be
dropped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The pixel format enumeration values used by the Tegra DSI controller
don't match those defined by the DSI framework. Make sure to convert
them to the internal format before writing it to the register.
Signed-off-by: Thierry Reding <treding@nvidia.com>
For some reason when the PW*_ENABLE and PM*_ENABLE fields are cleared
during disable, the HDMI output stops working properly. Resetting and
initializing doesn't help.
Comment out those accesses for now until it has been determined what to
do about them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Disable LVDS mode according to register documentation. It seems like
this has no effect on the operation of HDMI, but it's probably a good
idea to do this anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This reflects the power-up sequence as described in the documentation,
but it doesn't seem to be strictly necessary to get HDMI to work.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Clocks are never enabled or disabled in atomic context, so we can use
the clk_prepare_enable() and clk_disable_unprepare() helpers instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
