GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The usb is very much like on am33xx, we just put the some of the
componends under scm where they belong.
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The edma is the same as on am33xx, except it has four tptc
instances. And we need the edma_xbar for at least mmc3, so
let's use the edma_xbar and the new binding as suggested by
Peter Ujfalusi <peter.ujfalusi@ti.com>.
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for ti,edma-memcpy-channels binding]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Let's add the DM814X_IOPAD macro the same way as we have for dm816x and
am33xx as this allows comparing the registers with the documentation easily.
The pinctrl bits are yet again different on dm814x.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Otherwise pinctrl won't work. Because of silicon errata for some dm814x
versions, let's also keep bit 18 out of the function-mask and rely on
the bootloader configuration for bit 18 as suggested by
Matthijs van Duin <matthijsvanduin@gmail.com>.
Devices with that need to use bit 18 can override the function-mask in
the board specific dts file if really needed.
Signed-off-by: Tony Lindgren <tony@atomide.com>
The control module is at offset 0x14000 with size 0x20000, not 0x16000.
This causes the pinctrl driver to not work.
Let's also fix the comments related to the TRM "L4LS Instance Summary"
table as that's what's causing the bad entries.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Looks like I made a typo on the control base, all the 81xx
SoCs have it at 0x48140000 base. We've just gotten away with
the typo as the Ethernet phy was configured by the bootloader
on my test system and we're not yet using the pinctrl.
In addition to fixing the contol base, we need to also use the
right Ethernet phy flags to initialize it. And we are still
missing the PLL driver for dm814x and only relying on the
divider and mux clocks.
Fixes: f3d953ea37 ("ARM: dts: Add minimal dm814x support")
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use fixed clocks until we have a clock driver for the PLL.
The mux and divider composite clocks work the same way
as on dm816x and am335x.
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
