Commit Graph

9 Commits

Author SHA1 Message Date
Vasily Khoruzhick
cff6d1d6f8 arm64: dts: rockchip: enable HS200 for eMMC on rock64
eMMC that's sold by Pine64 can do HS200, rk3328 can do it
as well, so update DTS to enable it.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-05 08:40:51 +01:00
Heiko Stuebner
e78d53c7b2 arm64: dts: rockchip: enable display nodes on rk3328-rock64
Enable necessary nodes to get output on the hdmi port of the board.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-28 13:18:37 +02:00
Chen-Yu Tsai
cd7ab133db arm64: dts: rockchip: Enable SPI NOR flash on Rock64
The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.

This patch enables the SPI controller and adds a device node
for the flash chip using the generic "jedec,spi-nor" comaptible.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-26 13:37:52 +02:00
Katsuhiro Suzuki
e007e4e0d8 arm64: dts: rockchip: add spdif sound node for rock64
This patch adds sound card node for rock64. Currently we can support
S/PDIF only. It seems the lack of codec driver of rk3328 to enable
analog audio out.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-22 22:51:15 +02:00
Katsuhiro Suzuki
ef05bcb60c arm64: dts: rockchip: fix vcc_host1_5v pin assign on rk3328-rock64
This patch fixes pin assign of vcc_host1_5v. This regulator is
controlled by USB20_HOST_DRV signal.

ROCK64 schematic says that GPIO0_A2 pin is used as USB20_HOST_DRV.
GPIO0_D3 pin is for SPDIF_TX_M0.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-10 15:06:42 +02:00
Klaus Goger
4ee99cebd4 arm64: dts: rockchip: use SPDX-License-Identifier
Update all 64bit rockchip devicetree files to use SPDX-License-Identifiers.

All devicetrees claim to be either GPL or X11 while the actual license
text is MIT. Therefore we use MIT for the SPDX tag as X11 is clearly
wrong.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Brian Norris <briannorris@chromium.org>
Acked-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-06-17 09:31:57 +02:00
Kamil Trzciński
73e42e1866 arm64: dts: rockchip: fix rock64 gmac2io stability issues
This commit enables thresh dma mode as this forces to disable checksuming,
and chooses delay values which make the interface stable.

These changes are needed, because ROCK64 is faced with two problems:
1. tx checksuming does not work with packets larger than 1498,
2. the default delays for tx/rx are not stable when using 1Gbps connection.

Delays were found out with:
https://github.com/ayufan-rock64/linux-build/tree/master/recipes/gmac-delays-test

Signed-off-by: Kamil Trzciński <ayufan@ayufan.eu>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-02-12 09:39:01 +01:00
Heiko Stuebner
bc631943fa arm64: dts: rockchip: limit rk3328-rock64 gmac speed to 100MBit for now
It looks like either the current kernel or the hardware has reliability
issues when the gmac is actually running at 1GBit. In my test-case
it is not able to boot on a nfsroot at this speed, as the system
will always lose the connection to the nfs-server during boot, before
reaching any login prompt and not recover from this.

So until this is solved, limit the speed to 100MBit as with this the
nfsroot survives stress tests like an apt-get upgrade without problems.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-12-06 01:14:20 +01:00
Heiko Stuebner
955bebde05 arm64: dts: rockchip: add rk3328-rock64 board
The ROCK64 is a credit card size 4K60P HDR Media Board Computer using the
Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor and supporting
up to 4GB 1600MHz LPDDR3 memory. It provides eMMC module socket, MicroSD
Card slot, Pi-2 Bus, Pi-P5+ Bus, USB 3.0 and many others peripheral
devices interface for makers to integrate with sensors and devices.

The devicetree currently supports basic peripherals, with more to be
added later on.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-23 01:27:46 +02:00