3 Commits

Author	SHA1	Message	Date
Eric Auger	100e62983e	KVM: arm/arm64: Add GICV3 pending table save API documentation ... Add description for how to save GICV3 LPI pending bit into guest RAM pending tables. Signed-off-by: Eric Auger <eric.auger@redhat.com> Acked-by: Christoffer Dall <cdall@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com>	2017-05-08 14:31:22 +02:00
Vijaya Kumar K	e363e05e12	KVM: arm/arm64: Documentation: Update arm-vgic-v3.txt ... Update error code returned for Invalid CPU interface register value and access in AArch32 mode. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>	2017-01-30 13:47:33 +00:00
Christoffer Dall	7148480265	KVM: arm/arm64: Add VGICv3 save/restore API documentation ... Factor out the GICv3 and ITS-specific documentation into a separate documentation file. Add description for how to access distributor, redistributor, and CPU interface registers for GICv3 in this new file, and add a group for accessing level triggered IRQ information for GICv3 as well. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>	2016-09-08 12:53:00 +02:00