Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In multi-master environment, this driver's master cannot know
exactly when a peer master sends data to this driver's slave so
cases can be happened that this master tries sending data through
the master_xfer function but slave data from a peer master is still
being processed or slave xfer is started by a peer immediately
after it queues a master command. To support multi-master use cases
properly, this H/W provides arbitration in physical level and it
provides priority based command handling too to avoid conflicts in
multi-master environment, means that if a master and a slave events
happen at the same time, H/W will handle a higher priority event
first and a pending event will be handled when bus comes back to
the idle state.
To support this H/W feature properly, this patch adds the 'pending'
state of master and its handling code so that the pending master
xfer can be continued after slave operation properly.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit removes hard-coded bus timeout value setting so that
it can be set by i2c-core-base.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
The function that computes clock parameters from divisors did not
respect the maximum size of the bitfields that the parameters were
written to. This fixes the bug.
This bug can be reproduced with (and this fix verified with) the test
at: https://kunit-review.googlesource.com/c/linux/+/1035/
Discovered-by-KUnit: https://kunit-review.googlesource.com/c/linux/+/1035/
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Use a better annotation, so GCC won't complain anymore:
drivers/i2c/busses/i2c-aspeed.c:458:15: warning: this statement may fall through [-Wimplicit-fallthrough=]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Commit 3e9efc3299 ("i2c: aspeed: Handle master/slave combined irq events
properly") moved interrupt acknowledgment to the end of the interrupt
handler. In part this was done because the AST2500 datasheet says:
I2CD10 Interrupt Status Register
bit 2 Receive Done Interrupt status
S/W needs to clear this status bit to allow next data receiving.
Acknowledging Receive Done before receive data was handled resulted in
receive errors on high speed I2C busses.
However, interrupt acknowledgment was not only moved to the end of the
interrupt handler for Receive Done Interrupt status, but for all interrupt
status bits. This could result in race conditions if a second interrupt was
received during interrupt handling and not handled but still acknowledged
at the end of the interrupt handler.
Acknowledge only "Receive Done Interrupt status" late in the interrupt
handler to solve the problem.
Fixes: 3e9efc3299 ("i2c: aspeed: Handle master/slave combined irq events properly")
Cc: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Cc: Joel Stanley <joel@jms.id.au>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Tested-by: Joel Stanley <joel@jms.id.au>
Acked-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events using a
single interrupt call. It happens much more in multi-master
environment than single-master. For an example, when master is
waiting for a NORMAL_STOP interrupt in its MASTER_STOP state,
SLAVE_MATCH and RX_DONE interrupts could come along with the
NORMAL_STOP in case of an another master immediately sends data
just after acquiring the bus. In this case, the NORMAL_STOP
interrupt should be handled by master_irq and the SLAVE_MATCH and
RX_DONE interrupts should be handled by slave_irq. This commit
modifies irq hadling logic to handle the master/slave combined
events properly.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This patch adjusts spinlock scope to make it wrap the whole irq
handler using a single lock/unlock which covers both master and
slave handlers.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This patch changes the order of enum aspeed_i2c_master_state and
enum aspeed_i2c_slave_state defines to make their initial value to
ASPEED_I2C_MASTER_INACTIVE and ASPEED_I2C_SLAVE_STOP respectively.
In case of multi-master use, if a slave data comes ahead of the
first master xfer, master_state starts from an invalid state so
this change fixes the issue.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
There are some log printing without a newline character. This
patch adds the missing newline characters.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Because it looks neater.
For diolan, this allows factoring out some code that is now common
between if and else.
For eg20t, pch_i2c_writebytes is always called with a write in
msgs->flags, and pch_i2c_readbytes with a read.
For imx, i2c_imx_dma_write and i2c_imx_write are always called with a
write in msgs->flags, and i2c_imx_read with a read.
For qup, qup_i2c_write_tx_fifo_v1 is always called with a write in
qup->msg->flags.
For stu300, also restructure debug output for resends, since that
code as a result is only handling debug output.
Reviewed-by: Guenter Roeck <linux@roeck-us.net> [diolan]
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> [efm32 and imx]
Acked-by: Linus Walleij <linus.walleij@linaro.org> [stu300]
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
In order to use i2c from a cold boot, the i2c peripheral must be taken
out of reset. We request a shared reset controller each time a bus
driver is loaded, as the reset is shared between the 14 i2c buses.
On remove the reset is asserted, which only touches the hardware once
the last i2c bus is removed.
The reset is required as the I2C buses will not work without releasing
the reset. Previously the driver only worked with out of tree hacks
that released this reset before the driver was loaded. Update the
device tree bindings to reflect this.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Pull i2c updates from Wolfram Sang:
- new drivers for Spreadtrum I2C, Intel Cherry Trail Whiskey Cove SMBUS
- quite some driver updates
- cleanups for the i2c-mux subsystem
- some subsystem-wide constification
- further cleanup of include/linux/i2c
* 'i2c/for-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (50 commits)
i2c: sprd: Fix undefined reference errors
i2c: nomadik: constify amba_id
i2c: versatile: Make i2c_algo_bit_data const
i2c: busses: make i2c_adapter_quirks const
i2c: busses: make i2c_adapter const
i2c: busses: make i2c_algorithm const
i2c: Add Spreadtrum I2C controller driver
dt-bindings: i2c: Add Spreadtrum I2C controller documentation
i2c-cht-wc: make cht_wc_i2c_adap_driver static
MAINTAINERS: Add entry for drivers/i2c/busses/i2c-cht-wc.c
i2c: aspeed: Retain delay/setup/hold values when configuring bus frequency
dt-bindings: i2c: eeprom: Document vendor to be used and deprecated ones
i2c: i801: Restore the presence state of P2SB PCI device after reading BAR
MAINTAINERS: drop entry for Blackfin I2C and Sonic's email
blackfin: merge the two TWI header files
i2c: davinci: Preserve return value of devm_clk_get
i2c: mediatek: Add i2c compatible for MediaTek MT7622
dt-bindings: i2c: Add MediaTek MT7622 i2c binding
dt-bindings: i2c: modify information formats
i2c: mux: i2c-arb-gpio-challenge: allow compiling w/o OF support
...
In addition to the base, low and high clock configuration, the AC timing
register #1 on the AST2400 houses fields controlling:
1. tBUF: Minimum delay between Stop and Start conditions
2. tHDSTA: Hold time for the Start condition
3. tACST: Setup time for Start and Stop conditions, and hold time for the
Repeated Start condition
These values are defined in hardware on the AST2500 and therefore don't
need to be set.
aspeed_i2c_init_clk() was performing a direct write of the generated
clock values rather than a read/mask/modify/update sequence to retain
tBUF, tHDSTA and tACST, and therefore cleared the tBUF, tHDSTA and tACST
fields on the AST2400. This resulted in a delay/setup/hold time of 1
base clock, which in some configurations is not enough for some devices
(e.g. the MAX31785 fan controller, with an APB of 48MHz and a desired
bus speed of 100kHz).
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Tested-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Before I skipped null checks when the master is in the STOP state; this
fixes that.
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Acked-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Fixes: f327c686d3 ("i2c: aspeed: added driver for Aspeed I2C")
24xx BMCs have larger clock divider granularity which can cause problems
when trying to set them as 25xx clock dividers; this adds clock setting
code specific to 24xx.
This also fixes a potential issue where clock dividers were rounded down
instead of up.
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Added slave support for Aspeed I2C controller. Supports fourteen busses
present in AST24XX and AST25XX BMC SoCs by Aspeed.
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Added initial master support for Aspeed I2C controller. Supports
fourteen busses present in AST24XX and AST25XX BMC SoCs by Aspeed.
Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
