Commit Graph

5282 Commits

Author SHA1 Message Date
Jani Nikula
58c68779e4 drm/i915: make backlight info per-connector
Move from dev_priv to connector->panel. We still don't allow multiple
sysfs interfaces, though.

There should be no functional changes, except for a slight reordering of
connector backlight and sysfs destroy calls. (This change happens now
that the backlight device is actually per-connector, even though the
destroy calls became per-connector earlier.)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-13 00:07:43 +01:00
Jani Nikula
db31af1d4e drm/i915: clean up backlight conditional build
I've always felt the backlight device conditional build has been all
backwards. Make it feel right.

Gently move things towards connector based stuff while at it.

There should be no functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-13 00:07:06 +01:00
Dave Airlie
ab0169bb5c Merge tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
So here's the Broadwell pull request. From a kernel driver pov there's
two areas with big changes in Broadwell:
- Completely new enumerated interrupt bits. On the plus side it now looks
  fairly unform and sane.
- Completely new pagetable layout.

To ensure minimal impact on existing platforms we've refactored both the
irq and low-level gtt handling code a lot in anticipation of the bdw push.
So now bdw enabling in these areas just plugs in a bunch of vfuncs.

Otherwise it's all fairly harmless adjusting of switch cases and
if-ladders to shovel bdw into the right blocks. So minimized impact on
existing platforms. I've also merged the bdw-stage1 branch into our
-nightly integration branch for the past week to make sure we don't break
anything.

Note that there's still quite a flurry or patches floating around, but
I've figured I'll push this out. I plan to keep the bdw fixes separate
from my usual -fixes stream so that you can reject them easily in case it
still looks like too much churn. Also, bdw is for now hidden behind the
preliminary hw enabling module option. So there's no real pressure to get
follow-up patches all into 3.13.

* tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel: (75 commits)
  drm/i915: Mask the vblank interrupt on bdw by default
  drm/i915: Wire up cpu fifo underrun reporting support for bdw
  drm/i915: Optimize gen8_enable|disable_vblank functions
  drm/i915: Wire up pipe CRC support for bdw
  drm/i915: Wire up PCH interrupts for bdw
  drm/i915: Wire up port A aux channel
  drm/i915: Fix up the bdw pipe interrupt enable lists
  drm/i915: Optimize pipe irq handling on bdw
  drm/i915/bdw: Take render error interrupt out of the mask
  drm/i915/bdw: Add BDW PCH check first
  drm/i915: Use hsw_crt_get_config on BDW
  drm/i915/bdw: Change dp aux timeout to 600us on DDIA
  drm/i915/bdw: Enable trickle feed on Broadwell
  drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints
  drm/i915/bdw: conservative SBE VUE cache mode
  drm/i915/bdw: Limit SDE poly depth FIFO to 2
  drm/i915/bdw: Sampler power bypass disable
  ddrm/i915/bdw: Disable centroid pixel perf optimization
  drm/i915/bdw: BWGTLB clock gate disable
  drm/i915/bdw: Implement edp PSR workarounds
  ...
2013-11-10 18:35:33 +10:00
Daniel Vetter
13b3a0a776 drm/i915: Mask the vblank interrupt on bdw by default
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:14 +01:00
Daniel Vetter
38d83c96a3 drm/i915: Wire up cpu fifo underrun reporting support for bdw
HW engineers have listened and given us again a real interrupt with
masking and status regs. Yay!

For consistency with other platforms call the #define FIFO_UNDERRUN.
Eventually we also might need to have some enable/disable functions
for bdw display interrupts, but for now open-coding seems to be good
enough.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:13 +01:00
Daniel Vetter
7167d7c677 drm/i915: Optimize gen8_enable|disable_vblank functions
Let's cache the IMR value like on other platforms. This is needed to
implement the underrun reporting since then we'll have two places that
change the same register at runtime.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:13 +01:00
Daniel Vetter
0fbe7870d7 drm/i915: Wire up pipe CRC support for bdw
The layout of the CRC registers is the same as on hsw, only the
interrupt handling has changed a bit. So trivial to wire up, yay!

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:12 +01:00
Daniel Vetter
92d03a8048 drm/i915: Wire up PCH interrupts for bdw
Gives us hotplug, gmbus, dp aux and south errors (underrun
reporting!).

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:12 +01:00
Daniel Vetter
6d766f022a drm/i915: Wire up port A aux channel
Useful for dp aux to work better. Also stop enabling the port A
hotplug event - eDP panels are expected to fire that interupt and
we're not really ready to deal with them. This is consistent with how
we handle port A on ilk-hsw.

The more important bit is that we must delay the enabling of hotplug
interrupts until all the encoders are fully set up. But we need irq
support earlier than that, hence hotplug interrupts can only be
enabled in the ->hpd_irq_setup callback.

v2: Drop the _HOTPLUG, it isn't (Ville).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:11 +01:00
Daniel Vetter
30100f2bea drm/i915: Fix up the bdw pipe interrupt enable lists
- Pipe underrun can't just be enabled, we need some support code like
  on ilk-hsw to make this happen. So drop it for now.
- CRC error is a special mode of the CRC hardware that we don't use,
  so again drop it. Real CRC support for bdw will be added later.
- All the other error bits are about faults, so rename the #define and
  adjust the output.

v2: Use pipe_name as pointed out by Ville. Ville's comment was on a
previous patch, but it was easier to squash in here.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:11 +01:00
Daniel Vetter
c42664cceb drm/i915: Optimize pipe irq handling on bdw
We have a per-pipe bit in the master irq control register, so use it.
This allows us to drop the masks for aggregate interrupt bits and be a
bit more explicit in the code. It also removes one indentation level.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:10 +01:00
Daniel Vetter
40c499f93f drm/i915/bdw: Take render error interrupt out of the mask
The handling of the error interrupts isn't wired up at all. And it
hasn't been ever since ilk happened, so don't bother.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:10 +01:00
Ben Widawsky
e76e063486 drm/i915/bdw: Add BDW PCH check first
Early platforms use the same PCH as HSW, and to avoid triggering the
!ULT, and !HSW warnings, simply put it first in the search.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:09 +01:00
Ville Syrjälä
a29857914d drm/i915: Use hsw_crt_get_config on BDW
Broadwell should also use hsw_crt_get_config(). Just move the
function pointer assignment to the if HAS_DDI block we already
have there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:09 +01:00
Ben Widawsky
a81a507d48 drm/i915/bdw: Change dp aux timeout to 600us on DDIA
Cc: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:07 +01:00
Ville Syrjälä
b42c60090c drm/i915/bdw: Enable trickle feed on Broadwell
Like on HSW, trickle feed should always be enabled on BDW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:07 +01:00
Ben Widawsky
4c2e7a5f64 drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints
Implement WaSingleSubspanDispatchOnAALinesAndPoints

BDW-A workaround.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:06 +01:00
Ben Widawsky
a75f36283d drm/i915/bdw: conservative SBE VUE cache mode
Hold vertex data in cache until last reference

BDW-A workaround

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:06 +01:00
Ben Widawsky
7f88da0cf6 drm/i915/bdw: Limit SDE poly depth FIFO to 2
BDW-A workaround

BDW Bug #1899155

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:05 +01:00
Ben Widawsky
bf66347cd3 drm/i915/bdw: Sampler power bypass disable
BDW-A workaround.

BDW Bug #1899812

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:05 +01:00
Ben Widawsky
fd392b6003 ddrm/i915/bdw: Disable centroid pixel perf optimization
BDW-A workaround

BDW Bug #1899532

v2: WARN on when not using preliminary HW support

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:04 +01:00
Ben Widawsky
4afe8d3347 drm/i915/bdw: BWGTLB clock gate disable
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:04 +01:00
Ben Widawsky
fe4ab3ceef drm/i915/bdw: Implement edp PSR workarounds
This implements a workaround for PSR dealing with some vblank issue.

WaPsrDPAMaskVBlankInSRD && WaPsrDPRSUnmaskVBlankInSRD

v2: forgot to git add bogus whitespace fix

v3: Update with workaround names.
Use for_each_pipe() and CHICKEN_PIPESL_1(pipe) macro (Ville)

Cc: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
[danvet: Kill redundant IS_BDW check and remove the copious amount of
uneeded lines added.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:03 +01:00
Ben Widawsky
e64c4a1b8a drm/i915/bdw: Disable semaphores
We've done insufficient testing on them thus far, so keep them disabled
until we do test.

v2: Use WARN when not enabling preliminary HW support as this should
only be disabled for that case.

v3: Rip out the now useless (and really noisy) DRM_INFO output.

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:03 +01:00
Ben Widawsky
6edee7f3e7 drm/i915/bdw: Create a separate BDW rps enable
This is mostly what we have for HSW with the exceptions of:
no writes:
  GEN6_RC1_WAKE_RATE_LIMIT
  GEN6_RC6pp_WAKE_RATE_LIMIT
  GEN6_RC1e_THRESHOLD
  GEN6_RC6p_THRESHOLD
  GEN6_RC6pp_THRESHOLD

GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s

Don't try to overclock, or program ring/IA frequency tables since we
don't quite have sufficient docs yet.

NOTE: These values do not reflect the changes made recently by Chris.
Since we have no evidence yet what the proper way to tweak for this
platform is, I think it is good to go, and can be optimized by Chris, or
whomever, later.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Drop spurious hunk and drop TODO - having per-platform rps
register frobbing code is in my opinion preferred, now that all the
infrastructure functions are extracted.]
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:02 +01:00
Damien Lespiau
e3c3357863 drm/i915/bdw: Broadwell has a max port clock of 300Mhz on HDMI
Just like HSW.

This means we can scan out a mode with a 300Mhz pixel clock with a depth
of 24 bits, but only a 200Mhz one with a 36bits depth.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:01 +01:00
Ben Widawsky
0f161f7075 drm/i915/bdw: Don't wait for c0 threads on forcewake
It's no longer a required workaround on BDW.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Move compile fix from a later patch to this one.]
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:01 +01:00
Ben Widawsky
46c764d41f drm/i915/bdw: Use HSW formula for ring freq scaling
The current formula we use for HSW is not what is in current docs.
However, changing to the HSW formula on my HSW does not improve power
usage, and decreases performance by about 5% in limited xonotic testing.

For gen8, until we know otherwise, or run experiments, let's use
the HSW formula - which should be the same used in the Windows driver
(and thus help make an apples-applies comparison) on gen8.

v2: Use >= 8 instead of > 7 to be consistent with all other gen
checks.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:00 +01:00
Ben Widawsky
ed8546ac1f drm/i915/bdw: Support eDP PSR
Broadwell PSR support is a superset of Haswell. With this simple
register base calculation, everything that worked on HSW for eDP PSR
should work on BDW.

Note that Broadwell provides additional PSR support. This is not
addressed at this time.

v2: Make the HAS_PSR include BDW

v3: Use the correct offset (I had incorrectly used one from my faulty
brain) (Art!)

v4: It helps if you git add

v5: Be explicit about not setting min link entry time for BDW. This
should be no functional change over v4 (Jani)

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:00 +01:00
Ben Widawsky
2a114cc1b9 drm/i915/bdw: Use The GT mailbox for IPS enable/disable
v2: Squash in fixup from Ben to synchronize the GT mailbox commands.

CC: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:59 +01:00
Ville Syrjälä
416f4727ab drm/i915/bdw: Add Broadwell display FIFO limits
Broadwell has bigger display FIFOs than Haswell. Otherwise the
two are very similar.

v2: Fix FBC WM_LP shift for BDW

v3: Rebase on top of the big Haswell wm rework.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:59 +01:00
Paulo Zanoni
77d8d00944 drm/i915/bdw: check DPD on port D when setting the DDI buffers
Use the eDP values on platforms where port D is eDP. This doesn't
affect Haswell since it uses the same DDI buffer values for eDP and
DP.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:58 +01:00
Paulo Zanoni
bafb655367 drm/i915/bdw: BDW also has only 2 FDI lanes
So treat it like Haswell.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:58 +01:00
Paulo Zanoni
8f93f4f1e8 drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis
They're not the same as the Haswell ones.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:57 +01:00
Paulo Zanoni
300644c7dc drm/i915/bdw: add BDW DDI buf translations for eDP
Broadwell has different DDI buffer translations for eDP and DP, so add
support for the missing eDP and keep Haswell the same.

A future patch addresses the suggestion from Art to check for eDP on
port D and use the eDP values there, too.

v2: Make checkpatch happy.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:57 +01:00
Art Runyan
e58623cb65 drm/i915/bdw: Add BDW DDI buffer translation values
Many of the DDI buffer translation values have changed for BDW.
Add new translation tables and selection between HSW and BDW.

v2: s/BUG/WARN/ to avoid breaking future GENs.

v3: Rebase on top of the hdmi translation table changes.

v4: Fix up the multiline comment while at it.

Signed-off-by: Art Runyan <arthur.j.runyan@intel.com> (v2)
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:56 +01:00
Ben Widawsky
50ed5fbd9d drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority
GEN8 also needs this workaround.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Add a generic comment that we need to recheck all these w/a.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:55 +01:00
Ville Syrjälä
6bbfa1c5b6 drm/i915/bdw: Use pipe CSC on Broadwell
Route cursor and sprite data through the pipe CSC unit on BDW.
Primary plane data is already sent through the pipe CSC.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:55 +01:00
Paulo Zanoni
e39bf98a91 drm/i915/bdw: get the correct LCPLL frequency on Broadwell
v2: Rebased onto Paulo's MHz->kHz change.

v3: Rebased on top of the Haswell pc8+ adjustements.

v4: Use the exact 337.5MHz clock, should have been done as part of v2.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:54 +01:00
Paulo Zanoni
756f85cffe drm/i915/bdw: Broadwell has PIPEMISC
And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF
on previous gens).

v2: Rebase on to of the pipe config bpp handling rework.

v3: Rebased on top of the pipe_config->dither refactoring.

v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we
now also build up PIPECONF completely ourselves - keeping around
random stuff set by the BIOS just isn't a good idea. I've checked BDW
BSpec and we already set all relevant bits.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:54 +01:00
Paulo Zanoni
c7670b1098 drm/i915/bdw: on Broadwell, the panel fitter is on the pipe
So you can use the panel fitter while the power well is disabled and
you also don't need to set the "pipe" bit.

v2: Rebased on top of Jesse's pfit refactor, which moved pfit state
into the pipe_config.

v3: Rebase on top of the latest Haswell/panel fitter rework, which
neatly resolves a FIXME we have in this patch here:

v4: Rebase on top of the new power domain framework.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:53 +01:00
Paulo Zanoni
018f52c9c3 drm/i915/bdw: pretend we have LPT LP on Broadwell
The platforms we currently have all have LPT LP on them. As such, we
have no way to identify the new WPT PCH that will ship with Broadwell.

NOTE: For all purposes relevant to the driver that this point, LPT and
WPT are equivalent. Therefore there should be no need to actually change
this for some time.

v2: Don't assign dev_priv->num_pch_pll any more.

v3: Rebase on top of the PCH detection changes for virtualized
enviroments.

v4: Wrote commit message

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v3)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:53 +01:00
Paulo Zanoni
6745a2ceaa drm/i915/bdw: Broadwell also has the "power down well"
Just like Haswell, but with the small twist that the panel fitter for pipe A is
now also in the always-on power well.

v2: Use the new HAS_POWER_WELL macro.

v3: Rebase on top of intel_using_power_well patches.

v4: This time actually update the PFIT check correctly so that the
pipe A pfit is in the always-on domain.

v5: Rebase on top of the VGA power domain addition.

v6: Rebase on top of the new power domain infrastructure. Also pimp the commit
message a bit while at it.

v7: Use IS_BROADWELL instead of IS_GEN8 (Ville).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:52 +01:00
Paulo Zanoni
b3dc685e2f drm/i915/bdw: add Broadwell sprite/plane/cursor checks
Just make Broadwell follow the same code paths as Haswell here,
instead of running code for the even-older platforms.

v2: Shuffle around Ben's vma prep work.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:52 +01:00
Damien Lespiau
4b30553d89 drm/i915/bdw: Broadwell has 3 pipes
v2: Rebase (Paulo Zanoni)

v3: Rebase on top of num_pipes having moved to intel_device_info.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:51 +01:00
Paulo Zanoni
4e8058a20a drm/i915/bdw: add IS_BROADWELL macro
For now it's just equivalent to IS_GEN8, but in the future we might
want to change that (e.g., on Gen 7 we have IS_VALLEYVIEW,
IS_IVYBRIDGE and IS_HASWELL).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:51 +01:00
Ben Widawsky
780f18c84c drm/i915/bdw: BSD init for gen8 also
This was an oversight and should have been in a previous series
somewhere.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:50 +01:00
Ben Widawsky
77df677291 drm/i915/bdw: ppgtt info in debugfs
It's not so much that the information is terribly useful, but rather
that the gen6/7 information is completely useless.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:50 +01:00
Ville Syrjälä
b42218c19f drm/i915/bdw: Don't muck with gtt_size on Gen8 when PPGTT setup fails
v2: Resolve rebase conflicts and switch to gen < 8 color for GenX
checking.

v3: Rebase on top of the address space refactoring.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:49 +01:00
Ben Widawsky
a5f3d68e2e drm/i915/bdw: Render ring flushing
PIPE_CONTROL added the high address dword. I'm not sure how the
simulator let me get away with this. I've explicitly left out all the
workarounds from Gen7 because in the minimal digging that I did, most
don't seem necessary, and the simulator doesn't complain without them

Note that BLT and BSD ring commands had already been updated previously.
Just render/pipe_control should have been broken.

v2: Squash in a fixup from Ville to follow the recent IVB PIPE_CONTROL
updates: "BDW uses the IVB PIPE_CONTROL style for specifying GTT vs.
PPGTT for the PIPE_CONTROL QW/DW write."

v3: Rebase on top of Chris' cleanup to have an explicit ring->scratch
buffer object instead of an opaque ring->private where everyone stores
the same stuff inside.

Reported-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (for the fixup)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:49 +01:00