Commit Graph

4 Commits

Author SHA1 Message Date
Thierry Reding
68cd8b2e27 arm64: tegra: Fix copy/paste typo in several DTS includes
The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.

Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:38:14 +02:00
Thierry Reding
be70771d4c arm64: tegra: Remove 0, prefix from unit-addresses
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:38:10 +02:00
Adam Buchbinder
ef769e3208 arm64: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-04 18:19:17 +00:00
Thierry Reding
34b4f6d059 arm64: tegra: Add Tegra132 support
NVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124
but with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI
file for the SoC, which is mostly similar to the one for Tegra124.

Based on work by Allen Martin <amartin@nvidia.com>

Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:20 +01:00