Commit Graph

120435 Commits

Author SHA1 Message Date
Nishanth Menon
54d03c5d8b ARM: dts: AM57xx/DRA7: Update SoC voltage rail limits to match data sheet
As per the data sheet starting from SPRUHQ0H (Nov 2015 - Latest[1]),
VDD_CORE can vary from 0.85v to 1.15v for AVS class0. VDD GPU/DSP
et.al. can range from 0.85v to 1.25V with AVS class0

Since dynamic voltage scaling is disabled for DRA7/AM57xx SoCs for
all SoC rails other than MPU, the bootloader is responsible for
setting up the AVS class0 voltage, however, with wrong voltage machine
constraints in dtb, regulator framework will lower the voltage below
the required voltage levels for certain samples in production flow.
This can cause catastrophic failures which can be pretty hard to
identify.

Update board files which don't match required specification.

[1] http://www.ti.com/product/AM5728/datasheet/specifications#SPRT637-7340

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-26 10:01:55 -07:00
Geert Uytterhoeven
3023aa4ad8 ARM: dts: OMAP36xx: : DT spelling s/#address-cell/#address-cells/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-26 09:07:26 -07:00
Geert Uytterhoeven
ed53f62347 ARM: dts: omap5-cm-t54: DT spelling s/interrupt-name/interrupt-names/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-26 09:07:06 -07:00
Geert Uytterhoeven
e640bc306a ARM: dts: omap5-board-common: DT spelling s/interrupt-name/interrupt-names/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-26 09:06:47 -07:00
Nishanth Menon
a4240d3af6 ARM: dts: Add support for dra72-evm rev C (SR2.0)
DRA72-EVM now has an upgrade to Rev C with SR2.0 silicon. As part of
this change, a few updates were factored in that were software
incompatible with previous board in few areas:
- We now use DP83867 ethernet phy instead of older DP838865 which fails
  in certain use cases.
- Two Ethernet ports now instead of the single one in rev B.
- polarities changed for certain pcf gpios
- Due to SoC phy current requirements, VDDA supplies are split between
 ldo3 and ldo2 (ldo2 was previously unused). NOTE: DSS (VDDA_VIDEO) is
 still supplied by ldo5, HDMI is now supplied by LDO2 instead of using
 LDO3.

NOTE: It does not make much sense to spin off a new board compatible
flag since there is no real benefit for the same.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-14 13:43:10 -07:00
Marcin Niestroj
1ae5762dd6 ARM: dts: am335x-chilisom: Enable poweroff PMIC sequence using RTC signal
ChiliSOM has TPS65217's PWR_EN pin connected to AM335x PMIC_POWER_EN
pin. Processor's PMIC_POWER_EN is controlled by it's internal RTC, hence
RTC subsystem is responsible for proper board poweroff sequence.

This change enables complete poweroff sequence for ChiliBoard, switching
PMIC's state from ACTIVE to SLEEP.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-14 13:39:34 -07:00
Marcin Niestroj
ce07a9bd9c ARM: dts: am335x-chili*: Move Ethernet MAC description from SOM to board
ChiliSOM has 2 Ethernet subsystems with different types of possibly used
PHY interfaces (i.e. MII, RMII, GMII, RGMII). Current code configured
pinmux for RMII on 1st Ethernet subsystem and enabled Ethernet MAC with
1 slave for all boards which use ChiliSOM.

This change moves pinmux configuration of 1st Ethernet subsystem to
ChiliBoard description, as this is board-specific.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-14 13:39:34 -07:00
Marcin Niestroj
71815b1825 ARM: dts: am335x-chili*: Move uart0 description from SOM to board
uart0 configuration code has been in SOM. However, it is possible to
use all (or none) of 6 uart's of AM335x processor present on ChiliSOM.

This fix moves declaration of uart0 from ChiliSOM to ChiliBoard, because
use of uart is strictly board-specific.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-14 13:39:34 -07:00
Tero Kristo
8010f13a40 ARM: dts: am43xx: add support for clkout1 clock
clkout1 clock node and its generation tree was missing. Add this based
on the data on TRM and PRCM functional spec.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-13 12:07:31 -07:00
Roger Quadros
4cb53a2308 ARM: dts: omap3-beagle: Provide NAND ready pin
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.

Read speed increases from 13212 KiB/ to 15753 KiB/s
and write speed was unchanged at 4404 KiB/s.

Measured using mtd_speedtest.ko on omap3-beagle-c4.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
63015d73f3 ARM: dts: am335x: Provide NAND ready pin
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.

Read speed increases from 7869 KiB/ to 8875 KiB/s
and write speed was unchanged at 5100 KiB/s.

Measured using mtd_speedtest.ko on am335x-evm.

Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
99a4101182 ARM: dts: am437x: Provide NAND ready pin
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.

Read speed increases from 16516 KiB/ to 18813 KiB/s
and write speed was unchanged at 9941 KiB/s.

Measured using mtd_speedtest.ko.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
a23fc15584 ARM: dts: dra7x-evm: Provide NAND ready pin
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
8675afe574 ARM: dts: dm816x: Enable gpio controller for GPMC
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
0cac398b2b ARM: dts: dm814x: Enable gpio controller for GPMC
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
94f56c8b82 ARM: dts: omap3: Enable gpio controller for GPMC
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
9e08c2da42 ARM: dts: am4372: Enable gpio controller for GPMC
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
4eb4dd570d ARM: dts: am335x: Enable gpio controller for GPMC
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
845b1a260c ARM: dts: dra7: Enable gpio controller for GPMC
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
e99d413fab ARM: dts: omap5: Enable gpio and interrupt controller for GPMC
GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
8c75b76601 ARM: dts: omap4: Enable gpio and interrupt controller for GPMC
GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
ffee5bf318 ARM: dts: omap24xx: Enable gpio and interrupt controller for GPMC
GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Paul Kocialkowski
354fe2e74b ARM: dts: omap4-kc1: Power off support
This adds support for turning off the main power supply via the TWL6030 on the
Kindle Fire (first generation).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Paul Kocialkowski
ab8e2f8c5d ARM: dts: omap4-kc1: LEDs support
This adds support for the Kindle Fire (first generation) power button LEDs, that
are wired to the TWL6030 PWM outputs.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Paul Kocialkowski
abb68f64ce ARM: dts: omap4-kc1: USB OTG support
This adds support for USB OTG on the Kindle Fire (first generation).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Paul Kocialkowski
f81ad05447 ARM: dts: Amazon Kindle Fire (first generation) codename kc1 basic support
The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011. It is using an OMAP4430 SoC GP version.

This adds devicetree support for the device, with only a few basic features
supported, such as debug uart, i2c and internal emmc.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Yegor Yefremov
5e0884a486 ARM: dts: am335x-baltos-ir5221: use dedicated RTS/CTS signals
Before "tty: Add software emulated RS485 support for 8250" patch Baltos devices
relied on MCTRL_GPIO framework to handle both modem signals and RS485 mode.

With emulated RS485 support for 8250 we can now use these pins as dedicated
RTS/CTS signals taking advantage of hardware flow control etc. when operating
in RS232 mode.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Schuyler Patton
a7cac713f9 ARM: dts: AM572x-IDK Initial Support
The AM572x-IDK board is a board based on TI's AM5728 SOC
which has a dual core 1.5GHz A15 processor. This board is a
development platform for the Industrial market with:
- 2GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector

The link to the data sheet and TRM can be found here:

http://www.ti.com/product/AM5728

This patch creates a common dtsi file that will provide a common board
dtsi file to define the nodes that are common to AM57xx (including the
upcoming AM5718) IDK boards.

Initial support is only for basic peripherals

Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Lokesh Vutla
2061d74d38 ARM: dts: am335x: Add initial support for ICEv2 board
TI's Industrial Communication Engine EVM is a low cost hardware mainly
developed for industrial communication type applications using serial
or Ethernet based interfaces. This platform features TI's AM3359 with
800MHz single core Cortex-A8 processor, 256MB DDR3, 64MB SPI flash,
8MB NOR Flash, mmc, usb, can, dual Ethernet ports.

For more information, look at HW user guide[1], Data manual[2].

Just add basic support for the moment.

[1] http://processors.wiki.ti.com/index.php/AM335x_Industrial_Communication_Engine_EVM_Rev2_1_HW_User_Guide
[2] http://www.ti.com/lit/ds/symlink/am3359.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Franklin S Cooper Jr
dce2a65249 ARM: dts: da850/am4372/am33xx: Use generic node name for ehrpwm
When possible generic node names should be used. So change the node name
from ehrpwm to pwm.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Ben Hutchings
3a1de80824 ARM: dts: dra7xx: Fix compatible string for PCF8575 chip
The binding definition for the PCF857x GPIO expanders doesn't mention
a "ti,pcf8575" compatible string.  This is apparently because TI is
only a second source - there is no functional difference between
PCF8575 chips manufactured by TI and NXP, and the same board might be
populated with either depending on availability.

This is not a problem in practice because the I2C core uses
of_modalias_node() before matching drivers and this strips the
manufacturer name.

Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Filip Matijević
83faf92065 ARM: dts: N9/N950: Add support for accelerometer
Signed-off-by: Filip Matijević <filip.matijevic.pz@gmail.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Filip Matijević
0f4f1542ea ARM: dts: N9/N950: Add support for 1GHz CPU clock
Signed-off-by: Filip Matijević <filip.matijevic.pz@gmail.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Sebastian Reichel
8d1ddfce06 ARM: dts: OMAP3-N950: Add Keypad Slide Switch
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Sebastian Reichel
d5b0eab7ff ARM: dts: Enable N950 keyboard sleep leds by default
Like the Nokia N900, the N950 has leds to show
the state of sys_clkreq and sys_off_mode pins.

A detailed description for the LEDs and
OMAP's sleep states can be found in Tony's
commit for the Nokia N900:

c1be2032f6

Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Sebastian Reichel
d9546a189c ARM: dts: OMAP3-N950: Add Vibrator
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Sebastian Reichel
536b20113f ARM: dts: OMAP3-N950: Add Keypad Matrix
Add keypad matrix information based on data from
Nokia N950 Kernel.

Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Sebastian Reichel
50413b9d65 ARM: dts: n9/n950: regulator configuration
Add regulator configuration as found in the
board files of Nokia's kernel.

Signed-off-By: Sebastian Reichel <sre@kernel.org>

Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Roger Quadros
91d075c7cf ARM: dts: dra7-evm: Fix comment about NAND configuration
The switch configuration for NAND is actually the other way round.
Also mention ON/OFF states as that is more natural to understand
(without the help of schematics) when compared to HIGH/LOW.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 14:32:02 -07:00
Nishanth Menon
8695add6c3 ARM: dts: dra7-evm: Add missing regulators
Few regulators information were missing from DT. Add those
missing regulators.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12 13:39:50 -07:00
Suman Anna
d79852a792 ARM: dts: DRA7: Add timer12 node
Add the DT node for Timer12 present on DRA7 family of
SoCs. Timer12 is present in PD_WKUPAON power domain, and
has the same capabilities as the other timers, except for
the fact that it serves as a secure timer on HS devices
and is clocked only from the secure 32K clock.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 13:01:39 -07:00
Suman Anna
722326c49e ARM: dts: DRA7: Enable Timers 13 through 16
The Timers 13 through 16 have been added previously in
disabled state. These timers are common timers that are
present on all DRA7 family of SoCs, so enable these
devices by default like the rest of the DMTimers.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 13:01:39 -07:00
Peter Ujfalusi
296ea972dc ARM: dts: dra7: Add nodes for McASP1/2/4/5/6/7/8
Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 12:48:52 -07:00
Peter Ujfalusi
e56700b87c ARM: dts: dra7xx: Correct mcasp8_ahclkx_mux name
rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for the unit offsets]
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 12:48:45 -07:00
Peter Ujfalusi
42b2274da0 ARM: dts: am57xx-beagle-x15: Enable AFIFO use for McASP3
Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 12:48:36 -07:00
Peter Ujfalusi
e80ab5c972 ARM: dts: am57xx-beagle-x15: Move clkout2 source selection to codec node
The assigned-clock* needs to be in the root of the device's node. If it is
in the sub-node the CCF will ignore it.
Since the clkout2 is used by the codec as MCLK, move the clock parent
selection to that node.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 12:48:28 -07:00
Peter Ujfalusi
6cfec12f25 ARM: dts: dra72-evm: Enable AFIFO use for McASP3
Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 12:48:21 -07:00
Peter Ujfalusi
27701fc251 ARM: dts: dra7-evm: Enable AFIFO use for McASP3
Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 12:48:14 -07:00
Misael Lopez Cruz
0c92de2cd5 ARM: dts: dra7: Use eDMA and add DAT port address for McASP3
McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead.  This
restriction is also applicable for McASP1 and McASP2.

This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.

The addressing mode used in eDMA is INC, so the silicon limitation
described above has no impact and the McASP3 DAT port can be
safely added by switching to eDMA instead of sDMA.

Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 12:48:07 -07:00
Peter Ujfalusi
248948fbbd ARM: dts: dra7: Enable eDMA
DRA7 family has eDMA available along with the sDMA and in some cases it is
better suited for servicing peripherals.

Add the needed nodes for eDMA to be usable:
edma-tpcc, edma-tptc0/1 and the edma-xbar.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11 12:48:00 -07:00