Compensate for the differences in the layout of in-memory bootloader
information as seen from little-endian mode.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9590/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS:
- a number of fixes that didn't make the 3.19 release.
- a number of cleanups.
- preliminary support for Cavium's Octeon 3 SOCs which feature up to
48 MIPS64 R3 cores with FPU and hardware virtualization.
- support for MIPS R6 processors.
Revision 6 of the MIPS architecture is a major revision of the MIPS
architecture which does away with many of original sins of the
architecture such as branch delay slots. This and other changes in
R6 require major changes throughout the entire MIPS core
architecture code and make up for the lion share of this pull
request.
- finally some preparatory work for eXtendend Physical Address
support, which allows support of up to 40 bit of physical address
space on 32 bit processors"
[ Ahh, MIPS can't leave the PAE brain damage alone. It's like
every CPU architect has to make that mistake, but pee in the snow
by changing the TLA. But whether it's called PAE, LPAE or XPA,
it's horrid crud - Linus ]
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (114 commits)
MIPS: sead3: Corrected get_c0_perfcount_int
MIPS: mm: Remove dead macro definitions
MIPS: OCTEON: irq: add CIB and other fixes
MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.
MIPS: OCTEON: More OCTEONIII support
MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.
MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.
MIPS: OCTEON: Update octeon-model.h code for new SoCs.
MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX
MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h
MIPS: OCTEON: Implement the core-16057 workaround
MIPS: OCTEON: Delete unused COP2 saving code
MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register
MIPS: OCTEON: Save and restore CP2 SHA3 state
MIPS: OCTEON: Fix FP context save.
MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs
MIPS: boot: Provide more uImage options
MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h
MIPS: ip22-gio: Remove legacy suspend/resume support
mips: pci: Add ifdef around pci_proc_domain
...
Also update union octeon_cvmemctl with new OCTEON II fields.
[aleksey.makarov@auriga.com: use __BITFIELD_FIELD]
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8940/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The wide multiplier is twice as wide, so we need to save twice as much
state. Detect the multiplier type (CPU type) at start up and install
model specific handlers.
[aleksey.makarov@auriga.com:
conflict resolution,
support for old compilers]
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Leonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8933/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The GCC_OFF12_ASM macro is used for 12-bit immediate constrains
but we will also use it for 9-bit constrains on MIPS R6 so we
rename it to something more appropriate.
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reintroduce run-time check for crypto features. The old one was deleted
because it was unreliable, now decide the crypto availability on early
boot when the model string is constructed.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add crypto helper functions which are needed for kernel level usage.
The code for these has been extracted from the EdgeRouter Pro GPL tarball.
While at it, also delete duplicate definitions of the functions.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
In the microMIPS encoding some memory access instructions have their
immediate offset reduced to 12 bits only. That does not match the GCC
`R' constraint we use in some places to satisfy the requirement,
resulting in build failures like this:
{standard input}: Assembler messages:
{standard input}:720: Error: macro used $at after ".set noat"
{standard input}:720: Warning: macro instruction expanded into multiple instructions
Fix the problem by defining a macro, `GCC_OFF12_ASM', that expands to
the right constraint depending on whether microMIPS or standard MIPS
code is produced. Also apply the fix to where `m' is used as in the
worst case this change does nothing, e.g. where the pointer was already
in a register such as a function argument and no further offset was
requested, and in the best case it avoids an extraneous sequence of up
to two instructions to load the high 20 bits of the address in the LL/SC
loop. This reduces the risk of lock contention that is the higher the
more instructions there are in the critical section between LL and SC.
Strictly speaking we could just bulk-replace `R' with `ZC' as the latter
constraint adjusts automatically depending on the ISA selected.
However it was only introduced with GCC 4.9 and we keep supporing older
compilers for the standard MIPS configuration, hence the slightly more
complicated approach I chose.
The choice of a zero-argument function-like rather than an object-like
macro was made so that it does not look like a function call taking the
C expression used for the constraint as an argument. This is so as not
to confuse the reader or formatting checkers like `checkpatch.pl' and
follows previous practice.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8482/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Mark octeon_model_get_string() with __init and make internal functions
static.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com>
Cc: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We should not need to read fuses during normal operation, also the current
code has issues with that (not safe for concurrent access). Since there
are no in-kernel users for these, just delete them. Drivers should
not need such OCTEON_HAS_FEATURE mechanism in any case, instead the
information should be passed via device tree.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com>
Cc: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7665/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Use the much more common pr_warn instead of pr_warning
with the goal of removing pr_warning eventually.
Other miscellanea:
o Coalesce formats
o Realign arguments
Signed-off-by: Joe Perches <joe@perches.com>
Cc: linux-mips <linux-mips@linux-mips.org>
Cc: LKML <linux-kernel@vger.kernel.org>
Patchwork: https://patchwork.linux-mips.org/patch/7935/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add a definition for D-Link DSR-1000N router. The bootloader on this board
supplies 20006 in the bootinfo; the enum CVMX_BOARD_TYPE_CUST_DSR1000N
comes from the GPL sources of the board.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <ddaney.cavm@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7217/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Three checks for CONFIG_CAVIUM_GDB were added in v2.6.29. But the
Kconfig symbol CAVIUM_GDB was never added to the tree. Remove these
checks.
Also remove the last reference to octeon_get_boot_debug_flag(). There is
no definition of that function anyway.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Tested-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>)
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6976/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This will be needed by the next patch to use said nodes for probing
via the device tree.
Signed-off-by: David Daney <david.daney@cavium.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6185/
Pull trivial tree updates from Jiri Kosina:
"Usual earth-shaking, news-breaking, rocket science pile from
trivial.git"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (23 commits)
doc: usb: Fix typo in Documentation/usb/gadget_configs.txt
doc: add missing files to timers/00-INDEX
timekeeping: Fix some trivial typos in comments
mm: Fix some trivial typos in comments
irq: Fix some trivial typos in comments
NUMA: fix typos in Kconfig help text
mm: update 00-INDEX
doc: Documentation/DMA-attributes.txt fix typo
DRM: comment: `halve' -> `half'
Docs: Kconfig: `devlopers' -> `developers'
doc: typo on word accounting in kprobes.c in mutliple architectures
treewide: fix "usefull" typo
treewide: fix "distingush" typo
mm/Kconfig: Grammar s/an/a/
kexec: Typo s/the/then/
Documentation/kvm: Update cpuid documentation for steal time and pv eoi
treewide: Fix common typo in "identify"
__page_to_pfn: Fix typo in comment
Correct some typos for word frequency
clk: fixed-factor: Fix a trivial typo
...
Correct common misspelling of "identify" as "indentify" throughout
the kernel
Signed-off-by: Maxime Jayat <maxime@artisandeveloppeur.fr>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Enable interfaces on EdgeRouter Lite. Tested with cavium_octeon_defconfig
and busybox shell. DHCP & ping works with eth0, eth1 and eth2.
The board type "UBNT_E100" is taken from the sources of the vendor kernel
shipped with the product.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5546/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Pull MIPS updates from Ralf Baechle:
o Add basic support for the Mediatek/Ralink Wireless SoC family.
o The Qualcomm Atheros platform is extended by support for the new
QCA955X SoC series as well as a bunch of patches that get the code
ready for OF support.
o Lantiq and BCM47XX platform have a few improvements and bug fixes.
o MIPS has sent a few patches that get the kernel ready for the
upcoming microMIPS support.
o The rest of the series is made up of small bug fixes and cleanups
that relate to various parts of the MIPS code. The biggy in there is
a whitespace cleanup. After I was sent another set of whitespace
cleanup patches I decided it was the time to clean the whitespace
"issues" for once and and that touches many files below arch/mips/.
Fix up silly conflicts, mostly due to whitespace cleanups.
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits)
MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h
MIPS: remove broken conditional inside vpe loader code
MIPS: SMTC: fix implicit declaration of set_vi_handler
MIPS: early_printk: drop __init annotations
MIPS: Probe for and report hardware virtualization support.
MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board
MIPS: ath79: add USB controller registration code for the QCA955X SoCs
MIPS: ath79: add PCI controller registration code for the QCA955X SoCs
MIPS: ath79: add WMAC registration code for the QCA955X SoCs
MIPS: ath79: register UART for the QCA955X SoCs
MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear}
MIPS: ath79: add GPIO setup code for the QCA955X SoCs
MIPS: ath79: add IRQ handling code for the QCA955X SoCs
MIPS: ath79: add clock setup code for the QCA955X SoCs
MIPS: ath79: add SoC detection code for the QCA955X SoCs
MIPS: ath79: add early printk support for the QCA955X SoCs
MIPS: ath79: fix WMAC IRQ resource assignment
mips: reserve elfcorehdr
mips: Make sure kernel memory is in iomem
MIPS: ath79: use dynamically allocated USB platform devices
...
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The patch needs to eliminate the definition of OCTEON_IRQ_BOOTDMA so
that the device tree code can map the interrupt, so in order to not
temporarily break things, we do a single patch to both the interrupt
registration code and the pata_octeon_cf driver.
Also rolled in is a conversion to use hrtimers and corrections to the
timing calculations.
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Pull MIPS update from Ralf Baechle:
"This is the MIPS update for 3.7.
A fair chunk of them are platform updates to the Cavium Octeon SOC
(which involves machine generated header files of considerable size),
Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
platforms.
Support for the commercial MIPS simulator MIPSsim has been removed as
MIPS Technologies is shifting away from this product and Qemu is
offering various more powerful platforms. The generic MIPS code can
now also probe for no-execute / write-only TLB features implemented
without the full SmartMIPS extension as permitted by the latest MIPS
processor architecture. Lots of small changes to generic code."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
MIPS: BCM63XX: Properly handle mac address octet overflow
MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
MIPS: Replace `-' in defconfig filename wth `_' for consistency.
MIPS: Wire kcmp syscall.
MIPS: MIPSsim: Remove the MIPSsim platform.
MIPS: NOTIFY_RESUME is not needed in TIF masks
MIPS: Merge the identical "return from syscall" per-ABI code
MIPS: Unobfuscate _TIF..._MASK
MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
MIPS: Add base architecture support for RI and XI.
MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
MIPS: uasm: Add INS and EXT instructions.
MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
MIPS: Make VPE count to be one-based.
MIPS: Add new end of interrupt functionality for GIC.
MIPS: Add EIC support for GIC.
MIPS: Code clean-ups for the GIC.
...
Convert #include "..." to #include <path/...> in kernel system headers.
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Dave Jones <davej@redhat.com>
The cn68XX has a new interrupt controller named CIU2, add support for
this, and use it if cn68XX detected at runtime.
Signed-off-by: David Daney <david.daney@cavium.com>
Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.
Add little-endian register layouts.
Patch cvmx-interrupt-rsl.c for changed definition.
Signed-off-by: David Daney <david.daney@cavium.com>
Also add cvmx_get_octeon_family().
Both of these are needed by the upcoming register definition refresh
patch.
Signed-off-by: David Daney <david.daney@cavium.com>
Needed by SPI driver.
Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/3796/
Signed-off-by: John Crispin <blogic@openwrt.org>
There are three parts to this:
1) Remove the definitions of OCTEON_IRQ_TWSI and OCTEON_IRQ_TWSI2.
The interrupts are specified by the device tree and these hard
coded irq numbers block the used of the irq lines by the irq_domain
code.
2) Remove platform device setup code from octeon-platform.c, it is
now unused.
3) Convert i2c-octeon.c to use device tree. Part of this includes
using the devm_* functions instead of the raw counterparts, thus
simplifying error handling. No functionality is changed.
Signed-off-by: David Daney <david.daney@cavium.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Cc: linux-mips@linux-mips.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/3939/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
OCTEON II has a new dma to phys mapping method for PCIe. Define
OCTEON_DMA_BAR_TYPE_PCIE2 to denote this case, and handle it.
OCTEON II also needs a swiotlb if the OHCI USB driver is enabled, so
allocate this too.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2983/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
cvmx.h was rearranged to fix include file ordering problems, but there
is no change other than moving some definitions around.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2984/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Several newer chips were not covered, update the code to detect them.
This necessitates updating cvmx-mio-defs.h as well, because it has new
and required definitions.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2939/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Bootloaders can pass version 3 of this structure. Add the new fields
so we can support the Device Tree.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2938/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
