AHB BIST gate is actually controlled with bit 7.
This bug was detected while trying to use the NAND controller which is
using the DMA engine to transfer data to the NAND.
Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit,
the core was disabling the DMA engine clock as part of its 'disable
unused clks' procedure, which was causing all DMA transfers to fail after
this point.
Fixes: 5e73761786 ("clk: sunxi-ng: Add sun5i CCU driver")
Cc: stable@vger.kernel.org
Reported-by: Angus Ainslie <angus@akkea.ca>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Angus Ainslie <angus@akkea.ca>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1495643669-28221-1-git-send-email-boris.brezillon@free-electrons.com
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same
silicon, and all share the same clocks.
However, they're not packaged in the same way, and therefore not all the
controllers are actually available on all these SoCs.
Introduce a clock controller driver for all these SoCs with different
compatibles to take that into account.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
