The r8a73a4 board support will use the pinctrl API to control the SCIF
pins, remove the corresponding unused function GPIOS.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
V2 of PINCTRL support for r8a73a4 IRQC hardware
and in particular the external pins IRQ0 -> IRQ57.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Implement pull-up/down support for r8a73a4 similar to the implementation
for sh73a0.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
V2 of code to add GPIO -> IRQ mappings to the
PFC table for the r8a73a4 SoC. Requires the IRQs
to be mapped at a fixed location in Linux IRQ
space. The actual IRQs are not handled by the
PFC, instead IRQC is used on r8a73a4.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers
in the PFC SoC data. Pin numbers shall be used with the GPIO API from
this point on.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial PFC support for the r8a73a4 SoC.
At this point only GPIO interface is supported, move to newer interfaces
planned as incremental changes.
Original authors are Morimoto-san with help from Yoshii-san, thanks to
them for the heavy lifting. Adjusted by Magnus to work together with
updated code in drivers/pinctrl.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Takashi Yoshii <takashi.yoshii.zj@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The output pixel clocks can be used without the input pixel clocks.
Split them in different groups.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
GPIOs are now handled by a separate driver, remove GPIO data from the
SoC information structure.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When a GPIO is handled by a separate driver the pinmux
gpio_set_direction() handler won't be called. The pin mux type then need
to be configured to GPIO at request time.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Boards/platforms that register dedicated GPIO devices will not supply a
memory resource for GPIOs. Try to locate the GPIO memory resource at
initialization time, and skip registration of the gpiochip if the
resource can't be found.
This is a temporary modification to ease the transition to separate GPIO
drivers. It should be reverted when all boards and platforms will have
been moved.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When implemented as a separate IP block, GPIOs should be handled by a
separate driver. To make this possible GPIO support needs to be optional
in the sh-pfc driver.
If no GPIO data registers are supplied in the SoC information structure
skip registration of the gpiochip.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The target is to get rid of function GPIOs completely. To reach this,
make function GPIOs support optional by skipping the function GPIO chip
registration if no function GPIOS are defined in SoC data.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Register the GPIO pin range, and request and free GPIO pins using the
pinctrl API.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch is V3 of a GPIO driver for the R-Car series of
SoCs from Renesas. This driver is designed to be reusable
between multiple SoCs that share the same basic building block,
but so far it has only been used on R-Car H1 (r8a7779).
Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on a single I/O memory
range and the 32 GPIOs are hooked up a single interrupt.
In the case of R-Car H1 either external IRQ pins or GPIOs
with interrupts can be used for on-board interupts. For
external IRQs 4 pins are supported, and in the case of GPIO
there are 202 GPIOS as 202 interrupts hooked up via 6 driver
instances and to the GIC and the Cortex-A9 Quad.
At this point this driver is interfacing as a regular
platform device driver. In the future DT support will be
submitted as an incremental feature patch.
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Refactor the GPIO macro magic to use GPIO numbers directly instead of
the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum
entries from the mach/r8a7779.h header.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7779 platforms use the pinctrl API to control functions. Function
GPIOs are unused and unneeded, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The sh_pfc_phys_to_virt() function ends with a BUG() statement without a
return. When CONFIG_BUG isn't set the function will thus have no return
value. Fix it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Conflicts:
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
This merge is to provide r8a73a4 SoC files, which are added in the
soc branch and depended on by r8a73a4 pfc-changes which are to
be added to the pinmux branch.
With the added capabilty of the intc_irqpin driver to handle shared
external IRQs, all prerequisites are fulfilled and we are ready to
migrate completely to GIC. This includes the following steps:
- Kconfig: select ARM_GIC and RENESAS_INTC_IRQPIN
- intc-r8a7740: Throw out all legacy INTC code and init the GIC. We need
to mask out all shared IRQs as it is needed by the
shared intc_irqpin driver.
- setup-r8a7740: Add 4 irqpin devices to handle external IRQs and update
all IRQ numbers to point to the GIC SPI.
- board-armadillo: Update all IRQ numbers to point to the GIC SPI.
- pfc-r8a7740: Update all IRQ numbers of the GPIOs to point to the GIC
SPI.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
On some hardware we don't have a 1-1 mapping from the external
interrupts coming from INTC to the GIC SPI pins. We can however
share lines to demux incoming IRQs on these SoCs.
This patch enables the intc_irqpin driver to detect requests for shared
interrupt lines and demuxes them properly by querying the INTC INTREQx0A
registers.
If you need multiple shared intc_irqpin device instances, be sure to mask
out all interrupts on the INTC that share the one line before you start
to register them. Else you run into IRQ floods that would be caused by
interrupts for which no handler has been set up yet when the first
intc_irqpin device is registered.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add DT support to the IRQC External IRQ Pin driver.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial DT support to the INTC External IRQ Pin
driver. At this point only hardware with 4-bit wide
sense registers is supported via DT.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds a driver for external IRQ pins connected
to the IRQC hardware block on recent SoCs from Renesas.
The IRQC hardware block is used together with more
recent ARM based SoCs using the GIC. As usual the GIC
requires external IRQ trigger setup somewhere else
which in this particular case happens to be IRQC.
This driver implements the glue code needed to configure
IRQ trigger and also handle mask/unmask and demux of
external IRQ pins hooked up from the IRQC to the GIC.
Tested on r8a73a4 but is designed to work with a wide
range of SoCs. The driver requires one GIC SPI per
external IRQ pin to operate. Each driver instance
will handle up to 32 external IRQ pins.
The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows configuration via platform data to support things
like static interrupt base address. DT support will
be added incrementally in the not so distant future.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use devm_kzalloc(), devm_ioremap_nocache()
and devm_request_irq() to simplify error
handling.
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add comments to describe the special case for
"force" versions of enable and disable functions.
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Cache IRQ in domain_irq variable instead of
making use of irq_find_mapping(). While at it
rename the irq variable to requested_irq.
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Remove whitespace damage and add newline
between variables and code.
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Adjust the sh73a0 IRQ code to make use of the
INTC External IRQ pin driver for external
interrupt pins IRQ0 -> IRQ31.
This removes quite a bit of special-case code
in intc-sh73a0.c but the number of lines get
replaced with platform device information in
setup-sh73a0.c. The PFC code is also adjusted
to make gpio_to_irq() return the correct
interrupt number.
At this point the DT reference implementations
are not covered. In the future such code shall
tie in the INTC External IRQ pin driver via
DT, so this kind of verbose code is not needed
for the long term DT case.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC hardware block usually contains a rather wide
range of features ranging from external IRQ pin handling
to legacy interrupt controller support. On older SoCs
the INTC is used as a general purpose interrupt controller
both for external IRQ pins and on-chip devices.
On more recent ARM based SoCs with Cortex-A9 the main
interrupt controller is the GIC, but IRQ trigger setup
still need to happen in the INTC hardware block.
This driver implements the glue code needed to configure
IRQ trigger and also handle mask/unmask and demux of
external IRQ pins hooked up from the INTC to the GIC.
Tested on sh73a0 and r8a7779. The hardware varies quite
a bit with SoC model, for instance register width and
bitfield widths vary wildly. The driver requires one GIC
SPI per external IRQ pin to operate. Each driver instance
will handle up to 8 external IRQ pins.
The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows configuration via platform data to support things
like static interrupt base address. DT support will
be added incrementally in the not so distant future.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7779 platforms now use the pinctrl API to control the INTC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the LBSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the USB pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the HSPI pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the SCIF pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7779 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The function is not documented in the r8a7779 datasheet. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7740 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All r8a7740 platforms now use the pinctrl API to control the LCD0 and
LCD1 pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the IrDA pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the USB pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the BSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the KEYSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinconf API to control pull-ups, the
corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the FSI pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the I2C pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the SCIFA and
SCIFB pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh73a0 platforms now use the pinctrl API to control the LCD and
LCD2 pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All sh7372 platforms now use the pinctrl API to control the SDHI and
MMCIF pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
