Commit Graph

66 Commits

Author SHA1 Message Date
Dave Gerlach
2e4b62dc5e ARM: OMAP2+: Remove suspend_set_ops from common pm late init
In omap2_common_pm_late_init suspend_set_ops was called to set common
suspend handling functions for all omap platforms. This created two
problems. First, these suspend ops were being set for all platforms,
regardless of whether or not suspend support has been integrated so in
the case of AM33XX, suspend to mem was presented as available but
failed every time. Second, some platforms will need to define a
completely separate set of suspend ops, such as AM33XX, due to
differences from previous omap platforms so there is no need to
always set the common omap ops.

This patch moves the suspend_set_ops call from omap2_common_pm_late_init
into a separate function that then gets called in the omap*_pm_init
functions for each platform.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-05-19 15:31:54 -07:00
Nishanth Menon
07484ca33e ARM: OMAP4: Fix definition of IS_PM44XX_ERRATUM
Just like IS_PM34XX_ERRATUM, IS_PM44XX_ERRATUM is valid only if
CONFIG_PM is enabled, else, disabling CONFIG_PM results in build
failure complaining about the following:
arch/arm/mach-omap2/built-in.o: In function `omap4_boot_secondary':
:(.text+0x8a70): undefined reference to `pm44xx_errata'

Fixes: c962184 (ARM: OMAP4: PM: add errata support)
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.ocm>
Acked-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-03-13 13:41:50 -07:00
Paul Walmsley
c4978fba6b ARM: OMAP2+: PM/powerdomain: move omap_set_pwrdm_state() to powerdomain code
Move omap_set_pwrdm_state() from the PM code to the powerdomain code,
and refactor it to split it up into several functions.  A subsequent patch
will rename it to conform with the existing powerdomain function names.

This version includes some additional documentation, based on a
suggestion from Jean Pihet.  It also modifies omap_set_pwrdm_state()
to not bail out early unless both the powerdomain current power state
and the next power state are equal.  (Previously it would terminate
early if the next power state was equal to the target power state,
which was insufficiently rigorous.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jean Pihet <jean.pihet@newoldbits.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tero Kristo <t-kristo@ti.com>
2013-01-29 14:59:57 -07:00
Linus Torvalds
a11da7df65 ARM: arm-soc: power management and clock changes
This branch contains a largeish set of updates of power management and
 clock setup. The bulk of it is for OMAP/AM33xx platforms, but also a
 few around hotplug/suspend/resume on Exynos.
 
 It includes a split-up of some of the OMAP clock data into separate
 files which adds to the diffstat, but gross delta is fairly reasonable.
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Merge tag 'pm-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC power management and clock changes from Olof Johansson:
 "This branch contains a largeish set of updates of power management and
  clock setup.  The bulk of it is for OMAP/AM33xx platforms, but also a
  few around hotplug/suspend/resume on Exynos.

  It includes a split-up of some of the OMAP clock data into separate
  files which adds to the diffstat, but gross delta is fairly reasonable."

* tag 'pm-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
  ARM: OMAP: Move plat-omap/dma-omap.h to include/linux/omap-dma.h
  ASoC: OMAP: mcbsp fixes for enabling ARM multiplatform support
  watchdog: OMAP: fixup for ARM multiplatform support
  ARM: EXYNOS: Add flush_cache_all in suspend finisher
  ARM: EXYNOS: Remove scu_enable from cpuidle
  ARM: EXYNOS: Fix soft reboot hang after suspend/resume
  ARM: EXYNOS: Add support for rtc wakeup
  ARM: EXYNOS: fix the hotplug for Cortex-A15
  ARM: OMAP2+: omap_device: Correct resource handling for DT boot
  ARM: OMAP2+: hwmod: Add possibility to count hwmod resources based on type
  ARM: OMAP2+: hwmod: Add support for per hwmod/module context lost count
  ARM: OMAP2+: PRM: initialize some PRM functions early
  ARM: OMAP2+: voltage: fixup oscillator handling when CONFIG_PM=n
  ARM: OMAP4: USB: power down MUSB PHY during boot
  ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
  ARM: OMAP2xxx: clock: drop obsolete clock data
  ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts
  ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections
  ARM: AM33xx: clock: drop obsolete clock data
  ARM: OMAP3xxx: clk: drop obsolete clock data
  ...
2012-12-13 10:58:20 -08:00
Kevin Hilman
74d29168e9 ARM: OMAP2+: voltage: fixup oscillator handling when CONFIG_PM=n
commit 908b75e8 (ARM: OMAP: add support for oscillator setup) added a new
API for oscillator setup, but is broken when CONFIG_PM=n.

The new functions have dummy definitions when CONFIG_PM=n, but also have
full implementations available, which conflict.

To fix, wrap the PM implmentations in #ifdef CONFIG_PM.

Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-11-14 17:21:15 -08:00
Tero Kristo
00bd228ea9 ARM: OMAP4: VC: setup I2C parameters based on board data
VC code now provides a table of pre-calculated I2C setup parameters,
which will be used based on the capacitance value calculated for the I2C
trace on the PCB. A default trace length of 6.3cm is used unless board
defines its own value during init. The parameters set will be the I2C
internal pull setup and the I2C timing parameters for high speed use
mode. Full speed mode is not supported as of now.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-11-05 15:31:12 -08:00
Tero Kristo
908b75e850 ARM: OMAP: add support for oscillator setup
This contains startup and shutdown times for the oscillator. By default
use ULONG_MAX. Oscillator setup is used for calculating and setting up
latencies for sleep modes that disable oscillator.

Based on a patch from Nishanth Menon <nm@ti.com>.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-11-05 15:12:40 -08:00
Santosh Shilimkar
ff999b8a09 ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.

Below is the abstract flow.

...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.

[..]

- CPU0 executes "GIC Restoration:"

[...]

- CPU0 swicthes to non-secure mode and jumps to OS resume code.

[...]

- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]

- CPU1 wakes up and start executing ROM code.

[..]

- CPU1 executes "GIC Restoration:"

[..]

- CPU1 swicthes to non-secure mode and jumps to OS resume code.

[...]

- CPU1 is online in OS and start executing.
[...]   -

GIC Restoration: /* Common routine for HS and GP devices */
{
       if (GICD != 1)  { /* This will be true in OSWR state */
               if (GIC_SAR_BACKUP_STATE == SAVED)
                       - CPU restores GIC distributor
               else
                       - reconfigure GIC distributor to boot values.

               GICD.Enable secure = 1
       }

       if (GIC_SAR_BACKUP_STATE == SAVED)
               - CPU restore its GIC CPU interface registers if saved.
       else
               - reconfigure its GIC CPU interface registers to boot
                       values.
}
...............................................................

So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.

The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
       bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
       bit 0 == Enable secure

But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
       bit 1 == Enable Non-secure
       bit 0 == Enable secure
Non-secure view which HLOS sees:
       bit 0 == Enable Non-secure

Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.

The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.

Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.

...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.

[..]

- CPU0 executes "GIC Restoration:"

[..]

- CPU0 swicthes to non-secure mode and jumps to OS resume code.

[..]

- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]

- CPU1 wakes up and start executing ROM code.

[..]

- CPU1 executes "GIC Restoration:"

[..]

- CPU1 swicthes to non-secure mode and jumps to OS resume code.

[..]

- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................

With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.

The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-11-05 14:26:43 -08:00
Tero Kristo
c962184459 ARM: OMAP4: PM: add errata support
Added similar PM errata flag support as omap3 has. This should be used
in similar manner, set the flags during init time, and check the flag
values during runtime.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-11-05 14:26:43 -08:00
Paul Walmsley
856c3c5b28 ARM: OMAP3: PM: apply part of the erratum i582 workaround
On OMAP34xx/35xx, and OMAP36xx chips with ES < 1.2, if the PER
powerdomain goes to OSWR or OFF while CORE stays at CSWR or ON, or if,
upon chip wakeup from OSWR or OFF, the CORE powerdomain goes ON before
PER, the UART3/4 FIFOs and McBSP2/3 SIDETONE memories will be
unusable.  This is erratum i582 in the OMAP36xx Silicon Errata
document.

This patch implements one of several parts of the workaround: the
addition of the wakeup dependency between the PER and WKUP
clockdomains, such that PER will wake up at the same time CORE_L3
does.

This is not a complete workaround.  For it to be complete:

1. the PER powerdomain's next power state must not be set to OSWR or
   OFF if the CORE powerdomain's next power state is set to CSWR or
   ON;

2. the UART3/4 FIFO and McBSP2/3 SIDETONE loopback tests should be run
   if the LASTPOWERSTATEENTERED bits for PER and CORE indicate that
   PER went OFF while CORE stayed on.  If loopback tests fail, then
   those devices will be unusable until PER and CORE can undergo a
   transition from ON to OSWR/OFF and back ON.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-22 13:35:17 -07:00
Linus Torvalds
a5ebba6b54 arm-soc: power management changes
These are various power management related changes, mainly concerning
 cpuidle on i.MX and OMAP, as well as a the move of the omap smartreflex
 driver to live in the power subsystem.
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Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc power management changes from Arnd Bergmann:
 "These are various power management related changes, mainly concerning
  cpuidle on i.MX and OMAP, as well as a the move of the omap
  smartreflex driver to live in the power subsystem."

Fix up conflicts in arch/arm/mach-{imx/mach-imx6q.c,omap2/prm2xxx_3xxx.h}

* tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
  ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge
  ARM: OMAP2+: do not allow SmartReflex to be built as a module
  ARM: OMAP2: Use hwmod to initialize mmc for 2420
  ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
  ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
  ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state
  ARM: OMAP3: PM: cleanup cam_pwrdm leftovers
  ARM: OMAP3: PM: call pre/post transition per powerdomain
  ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
  ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle
  ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
  ARM: OMAP3+: PRM: Enable IO wake up
  ARM: OMAP4: PRM: Add IO Daisychain support
  ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
  ARM: OMAP3: PM: correct enable/disable of daisy io chain
  ARM: OMAP2+: PRM: fix compile for OMAP4-only build
  W1: OMAP HDQ1W: use runtime PM
  ARM: OMAP2+: HDQ1W: use omap_device
  W1: OMAP HDQ1W: use 32-bit register accesses
  W1: OMAP HDQ1W: allow driver to be built on all OMAP2+
  ...
2012-07-23 17:43:53 -07:00
Daniel Lezcano
164e0cbf60 ARM: OMAP3/4: consolidate cpuidle Makefile
The current Makefile compiles the cpuidle34xx.c and cpuidle44xx.c files
even if the cpuidle option is not set in the kernel.

This patch fixes this by creating a section in the Makefile where these
files are compiled only if the CONFIG_CPU_IDLE option is set.

This modification breaks an implicit dependency between CPU_IDLE and PM as
they belong to the same block in the Makefile. This is fixed in the Kconfig
by selecting explicitely PM is CPU_IDLE is set.

The linux coding style recommend to use no-op functions in the headers
when the subsystem is disabled instead of adding big section in C files.

This patch fix this also.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-06-19 15:22:37 -07:00
Jean Pihet
7fb149ffe3 ARM: OMAP2+: SmartReflex: add POWER_AVS Kconfig options
Add a Kconfig menu (POWER_AVS) and rename the Kconfig options
for the OMAP SmartReflex implementation:
	CONFIG_OMAP_SMARTREFLEX renames to CONFIG_POWER_AVS_OMAP
	CONFIG_OMAP_SMARTREFLEX_CLASS3 renames to CONFIG_POWER_AVS_OMAP_CLASS3

This change makes the SmartReflex implementation ready for the move
to drivers/.

Signed-off-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-05-31 16:03:45 -07:00
Daniel Lezcano
0c2487f6b4 ARM: OMAP3: cpuidle - remove cpuidle_params_table
We do not longer need the ''cpuidle_params_table' array as
we defined the states in the driver and we checked they are
all valid.

We also remove the structure definition as it is no longer used.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-05-03 13:19:29 -07:00
Daniel Lezcano
231900afba ARM: OMAP3: cpuidle - remove rx51 cpuidle parameters table
As suggested, this table is an optimized version for rx51 and we
remove it in order to consolidate the cpuidle code between omap3
and omap4, we remove this specific data definition which is used
to override the default omap3 latencies but at the cost of extra
code and complexity.

In order to not lose the values which probably took time to be
measured, the table is converted into a comment with an array
description.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-05-03 11:01:01 -07:00
Olof Johansson
86ca5b6fef Merge branch 'uart' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
* 'uart' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: remove some orphan function declarations.
  ARM: OMAP2+: UART: remove unused fields in omap_uart_state.
2012-03-10 09:10:21 -08:00
Paul Walmsley
1416408d31 ARM: OMAP2+: PM: share some suspend-related functions across OMAP2, 3, 4
The platform_suspend_ops can be shared across OMAP2, 3, and 4, along
with all of the functions referenced in that structure.  This patch
shares them.  It also removes the suspend_state file-scoped variable
in the OMAP2 and 3 PM code; it does not appear to be actually needed
by anything.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
[khilman@ti.com: minor rework needed due to rebase/merge with conflicting changes]
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-03-05 16:01:19 -08:00
Paul Walmsley
92206fd292 ARM: OMAP2+: PM: share clkdms_setup() across OMAP2, 3, 4
clkdms_setup() is identical across OMAP2, 3, and 4, so share it.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-03-05 15:38:02 -08:00
NeilBrown
7cb034f817 ARM: OMAP2+: remove some orphan function declarations.
commit 2fd149645e (ARM: OMAP2+: UART: Remove omap_uart_can_sleep and
add pm_qos) removed omap_uart_can_sleep and omap3_can_sleep, but not
their declarations.  So remove those now.

Signed-off-by: NeilBrown <neilb@suse.de>
Reviewed-by: Shubhrajyoti D <shubhrajyoti@ti.com>
[khilman@ti.com: minor changelog edits]
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-02-21 11:13:11 -08:00
Santosh Shilimkar
9827266097 ARM: OMAP4: PM: Add CPUidle support
Add OMAP4 CPUIDLE support. CPU1 is left with defualt idle and
the low power state for it is managed via cpu-hotplug.

This patch adds MPUSS low power states in cpuidle.

	C1 - CPU0 ON + CPU1 ON + MPU ON
	C2 - CPU0 OFF + CPU1 OFF + MPU CSWR
	C3 - CPU0 OFF + CPU1 OFF + MPU OSWR

OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more
anymore just like CORE power domain. The deepest state supported is OSWr.
Ofcourse when MPUSS and CORE PD transitions to OSWR along with device
off mode, even the memory contemts are lost which is as good as
the PD off state.

On OMAP4 because of hardware constraints, no low power states are
targeted when both CPUs are online and in SMP mode. The low power
states are attempted only when secondary CPU gets offline to OFF
through hotplug infrastructure.

Thanks to Nicole Chalhoub <n-chalhoub@ti.com> for doing exhaustive
C-state latency profiling.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-12-08 11:29:01 -08:00
Linus Torvalds
ae4c42e4e4 Merge branch 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (133 commits)
  ARM: EXYNOS4: Change devname for FIMD clkdev
  ARM: S3C64XX: Cleanup mach/regs-fb.h from mach-s3c64xx
  ARM: S5PV210: Cleanup mach/regs-fb.h from mach-s5pv210
  ARM: S5PC100: Cleanup mach/regs-fb.h from mach-s5pc100
  ARM: S3C24XX: Use generic s3c_set_platdata for devices
  ARM: S3C64XX: Use generic s3c_set_platdata for OneNAND
  ARM: SAMSUNG: Use generic s3c_set_platdata for NAND
  ARM: SAMSUNG: Use generic s3c_set_platdata for USB OHCI
  ARM: SAMSUNG: Use generic s3c_set_platdata for HWMON
  ARM: SAMSUNG: Use generic s3c_set_platdata for FB
  ARM: SAMSUNG: Use generic s3c_set_platdata for TS
  ARM: S3C64XX: Add PWM backlight support on SMDK6410
  ARM: S5P64X0: Add PWM backlight support on SMDK6450
  ARM: S5P64X0: Add PWM backlight support on SMDK6440
  ARM: S5PC100: Add PWM backlight support on SMDKC100
  ARM: S5PV210: Add PWM backlight support on SMDKV210
  ARM: EXYNOS4: Add PWM backlight support on SMDKC210
  ARM: EXYNOS4: Add PWM backlight support on SMDKV310
  ARM: SAMSUNG: Create a common infrastructure for PWM backlight support
  clocksource: convert 32-bit down counting clocksource on S5PV210/S5P64X0
  ...

Fix up trivial conflict in arch/arm/mach-imx/mach-scb9328.c
2011-07-25 12:38:42 -07:00
Russell King
cbe263497d ARM: pm: omap3: move saving of the auxiliary control registers to C
Move the saving of the auxiliary control registers into C; there's
no need for this to be in assembly code.  This results in less
assembly code to deal with in OMAP.

Kevin tested full-chip retention and off on 3430/n900, 3530/Overo and
3630/Zoom3.

Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-30 08:47:35 +01:00
Jean Pihet
46e130d298 ARM: pm: omap3: run the ASM sleep code from DDR
Most of the ASM sleep code (in arch/arm/mach-omap2/sleep34xx.S)
is copied to internal SRAM at boot and after wake-up from CORE OFF
mode.  However only a small part of the code really needs to run from
internal SRAM.

This fix lets most of the ASM idle code run from the DDR in order to
minimize the SRAM usage and the overhead in the code copy.

The only pieces of code that are mandatory in SRAM are:
- the i443 erratum WA,
- the i581 erratum WA,
- the security extension code.

SRAM usage:
- original code:
  . 560 bytes for omap3_sram_configure_core_dpll (used by DVFS),
  . 852 bytes for omap_sram_idle (used by suspend/resume in RETention),
  . 124 bytes for es3_sdrc_fix (used by suspend/resume in OFF mode on ES3.x),
  . 108 bytes for save_secure_ram_context (used on HS parts only).

With this fix the usage for suspend/resume in RETention goes down 288
bytes, so the gain in SRAM usage for suspend/resume is 564 bytes.

Also fixed the SRAM initialization sequence to avoid an unnecessary
copy to SRAM at boot time and for readability.

Tested on Beagleboard (ES2.x) in idle with full RET and OFF modes.

Kevin Hilman tested retention and off on 3430/n900, 3530/Overo and
3630/Zoom3

Signed-off-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-29 19:07:47 +01:00
Tony Lindgren
48cb1258e8 Merge branch 'for_3.1/pm-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into devel-cleanup
Conflicts:
	arch/arm/mach-omap2/pm-debug.c
	arch/arm/mach-omap2/pm.h
2011-06-29 04:45:16 -07:00
Kevin Hilman
59bec58373 OMAP3: PM debug: remove register dumping
Remove OMAP3-specific register dumping feature from PM debug layer.
This is removed because:

- it's ugly
- it's OMAP3-specific, and will obviously not scale to OMAP4+
- userspace /dev/mem-based tools (like omapconf) can do this much better

Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-06-27 09:53:09 -07:00
Kevin Hilman
20d5d55149 OMAP2: PM debug: remove register dumping
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-06-20 14:12:32 -07:00
Kevin Hilman
3a7b7bdd24 OMAP3: PM debug: remove sleep_while_idle feature
Remove the OMAP-specific PM debug 'sleep_while_idle' feature which is
currently available as an OMAP-specific debugfs entry.

This duplicates existing ARM-generic functionality available as a
boot-time option using the boot cmdline option 'hohlt'.

If runtime configuration of this is needed, then adding a debugfs
entry for the ARM-generic hlt/nohlt interface should be added.

Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-06-20 14:12:32 -07:00
Tony Lindgren
98e182a26b omap2+: Remove gptimer_wakeup for now
This removes the support for setting the wake-up timer for debugging.

Later on we can reserve gptimer1 for PM code only and have similar
functionality.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
2011-06-20 01:25:39 -07:00
Jean Pihet
0490891819 OMAP3: cpuidle: change the power domains modes determination logic
The achievable power modes of the power domains in cpuidle
depends on the system wide 'enable_off_mode' knob in debugfs.
Upon changing enable_off_mode, do not change the C-states
'valid' field but instead dynamically restrict the power modes
when entering idle.

The C-states 'valid' field is just used to enable/disable some
C-states at init and shall not be changed later on.

Signed-off-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-05-20 17:15:54 +02:00
Jean Pihet
866ba0ef96 OMAP3: clean-up mach specific cpuidle data structures
- sleep_latency and wake_latency are not used, replace them by
  exit_latency which is used by cpuidle. exit_latency simply is
  the sum of sleep_latency and wake_latency,
- replace threshold by target_residency,
- changed the OMAP3 specific cpuidle code accordingly,
- changed the OMAP3 board code accordingly.

Signed-off-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-05-20 17:15:53 +02:00
Linus Torvalds
0df0914d41 Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (258 commits)
  omap: zoom: host should not pull up wl1271's irq line
  arm: plat-omap: iommu: fix request_mem_region() error path
  OMAP2+: Common CPU DIE ID reading code reads wrong registers for OMAP4430
  omap4: mux: Remove duplicate mux modes
  omap: iovmm: don't check 'da' to set IOVMF_DA_FIXED flag
  omap: iovmm: disallow mapping NULL address when IOVMF_DA_ANON is set
  omap2+: mux: Fix compile when CONFIG_OMAP_MUX is not selected
  omap4: board-omap4panda: Initialise the serial pads
  omap3: board-3430sdp: Initialise the serial pads
  omap4: board-4430sdp: Initialise the serial pads
  omap2+: mux: Add macro for configuring static with omap_hwmod_mux_init
  omap2+: mux: Remove the use of IDLE flag
  omap2+: Add separate list for dynamic pads to mux
  perf: add OMAP support for the new power events
  OMAP4: Add IVA OPP enteries.
  OMAP4: Update Voltage Rail Values for MPU, IVA and CORE
  OMAP4: Enable 800 MHz and 1 GHz MPU-OPP
  OMAP3+: OPP: Replace voltage values with Macros
  OMAP3: wdtimer: Fix CORE idle transition
  Watchdog: omap_wdt: add fine grain runtime-pm
  ...

Fix up various conflicts in
 - arch/arm/mach-omap2/board-omap3evm.c
 - arch/arm/mach-omap2/clock3xxx_data.c
 - arch/arm/mach-omap2/usb-musb.c
 - arch/arm/plat-omap/include/plat/usb.h
 - drivers/usb/musb/musb_core.h
2011-03-17 19:28:15 -07:00
Thara Gopinath
4071318983 OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
Voltage control on TWL can be done using VMODE/I2C1/I2C_SR.
Since almost all platforms use I2C_SR on omap3, omap3_twl_init by
default expects that OMAP's I2C_SR is plugged in to TWL's I2C
and calls omap3_twl_set_sr_bit. On platforms where I2C_SR is not connected,
the board files are expected to call omap3_twl_set_sr_bit(false) to
ensure that I2C_SR path is not set for voltage control and prevent
the default behavior of omap3_twl_init.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-03-09 16:15:50 -08:00
Jean Pihet
b6338bdc83 ARM: 6649/1: omap: use fncpy to copy the PM code functions to SRAM
The new fncpy API is better suited* for copying some
code to SRAM at runtime. This patch changes the ad-hoc
code to the more generic fncpy API.

*: 1. fncpy ensures that the thumb mode bit is propagated,
   2. fncpy provides the security of type safety between the
     original function and the sram function pointer.

Tested OK on OMAP3 in low power modes (RET/OFF)
using omap2plus_defconfig with !CONFIG_THUMB2_KERNEL.
Compile tested on OMAP1/2 using omap1_defconfig.

Boot tested on OMAP1 & OMAP2
Tested OK with suspend/resume on OMAP2420/n810

Boots fine on osk5912 and n800

Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Kevin Hilman <khilman@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Kevin Hilman <khilman@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-04 14:26:08 +00:00
Thara Gopinath
7bc3ed9ae6 OMAP4: Register voltage PMIC parameters with the voltage layer
TWL6030 is the power IC used along with OMAP4 in OMAP4 SDPs,
blaze boards and panda boards. This patch registers the OMAP4
PMIC specific information with the voltage layer.
This also involves implementing a different formula for
voltage to vsel and vsel to voltage calculations from
TWL4030.

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-22 14:31:45 -08:00
Thara Gopinath
fbc319f676 OMAP3: PM: Register TWL4030 pmic info with the voltage driver.
This patch registers the TWL4030 PMIC specific informtion
with the voltage driver. Failing this patch the voltage driver
is unware of the formula to use for vsel to voltage and vice versa
conversion and lot of other PMIC dependent parameters.

This file is based on the arch/arm/plat-omap opp_twl_tpl.c file
by Paul Walmsley. The original file is replaced by this file.

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-22 14:31:41 -08:00
Thara Gopinath
0c0a5d61ed OMAP3: PM: Adding smartreflex device file.
This patch adds support for device registration of various
smartreflex module present in the system. This patch introduces
the platform data for smartreflex devices which include
the efused n-target vaules, a parameter to indicate
whether smartreflex autocompensation needs to be
enabled on init or not. An API
omap_enable_smartreflex_on_init is provided for the
board files to enable smartreflex autocompensation during
system boot up.

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-22 14:31:37 -08:00
Paul Walmsley
72e06d0872 OMAP2+: powerdomain: move header file from plat-omap to mach-omap2
The OMAP powerdomain code and data is all OMAP2+-specific.  This seems
unlikely to change any time soon.  Move plat-omap/include/plat/powerdomain.h
to mach-omap2/powerdomain.h.  The primary point of doing this is to remove
the temptation for unrelated upper-layer code to access powerdomain code
and data directly.

As part of this process, remove the references to powerdomain data
from the GPIO "driver" and the OMAP PM no-op layer, both in plat-omap.
Change the DSPBridge code to point to the new location for the
powerdomain headers.  The DSPBridge code should not be including the
powerdomain headers; these should be removed.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Omar Ramirez Luna <omar.ramirez@ti.com>
Cc: Felipe Contreras <felipe.contreras@gmail.com>
Cc: Greg Kroah-Hartman <greg@kroah.com>
2010-12-21 21:05:16 -07:00
Tony Lindgren
b9e7683bbc Merge branch 'pm-opp' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-linus 2010-12-21 17:05:57 -08:00
Jean Pihet
d3cdfd2a15 OMAP3: remove unused code from the ASM sleep code
Remove unused code:
- macros,
- variables,
- unused semaphore locking API. This API shall be added back
  when needed,
- infinite loops for debug.

Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.

Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon<nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-21 14:45:54 -08:00
Eduardo Valentin
cc1b602887 OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
Limitation i583: Self_Refresh Exit issue after OFF mode

Issue:
When device is waking up from OFF mode, then SDRC state machine sends
inappropriate sequence violating JEDEC standards.

Impact:
OMAP3630 < ES1.2 is impacted as follows depending on the platform:
CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable, while
	for all other sysclk frequencies, varied levels of instability
	seen based on varied parameters.
CS1: impacted

This patch takes option #3 as recommended by the Silicon erratum:
Avoid core power domain transitioning to OFF mode. Power consumption
impact is expected in this case.
To do this, we route core OFF requests to RET request on the impacted
revisions of silicon.

Acked-by: Jean Pihet <j-pihet@ti.com>

[nm@ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a bit]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-21 14:45:53 -08:00
Nishanth Menon
80723c3fe4 OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
Currently omap3_cpuidle_update_states makes whole sale decision
on which C states to update based on enable_off_mode variable
Instead, achieve the same functionality by independently providing
mpu and core deepest states the system is allowed to achieve and
update the idle states accordingly.

Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
[khilman: fixed additional user of this API in OMAP CPUidle driver]
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-21 14:45:52 -08:00
Peter 'p2' De Schrijver
c4236d2e79 OMAP3630: PM: Disable L2 cache while invalidating L2 cache
While coming out of MPU OSWR/OFF states, L2 controller is reseted.
The reset behavior is implementation specific as per ARMv7 TRM and
hence $L2 needs to be invalidated before it's use. Since the
AUXCTRL register is also reconfigured, disable L2 cache before
invalidating it and re-enables it afterwards. This is as per
Cortex-A8 ARM documentation.
Currently this is identified as being needed on OMAP3630 as the
disable/enable is done from "public side" while, on OMAP3430, this
is done in the "secure side".

Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>

Acked-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

[nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-21 14:45:51 -08:00
Nishanth Menon
458e999eb1 OMAP3630: PM: Erratum i608: disable RTA
Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device
stability issues when enabled. This impacts modules with embedded memories
on OMAP3630

Workaround is to disable RTA on boot and coming out of core off.
For disabling RTA coming out of off mode, we do this by overriding the
restore pointer for 3630 as the first point of entry before caches are
touched and is common for GP and HS devices. To disable earlier than
this could be possible by modifying the PPA for HS devices, but not for
GP devices.

Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>

Acked-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

[ambresh@ti.com: co-developer]
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-21 14:45:50 -08:00
Nishanth Menon
8cdfd83473 OMAP3: pm: introduce errata handling
Introduce errata handling for OMAP3. This patch introduces
errata variable and stub for initialization which will be
filled up by follow-on patches.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-21 14:45:49 -08:00
Nishanth Menon
f5a6422d4e omap4: opp: add OPP table data
This patch adds OPP tables for OMAP4. New file has been added to keep
the OMAP4 opp tables and the registration of these tables with the
generic opp framework by OMAP SoC OPP interface.

Based on:
http://dev.omapzoom.org/?p=santosh/kernel-omap4-base.git;a=blob;f=arch/arm/mach-omap2/opp44xx_data.c;h=252e3d0cb6050a64f390b9311c1c4977d74f762a;hb=refs/heads/omap4_next

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-21 14:30:40 -08:00
Nishanth Menon
fd1478cd61 omap: opp: add OMAP3 OPP table data and common init
Add OPP data for OMAP34xx and OMAP36xx and initialization functions
to populate OPP tables based on current SoC.
introduce an OMAP generic opp initialization routine which OMAP3
and OMAP4+ SoCs can use to register their OPP definitions.

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-12-21 14:30:40 -08:00
Loïc Minier
ebfa88cfa1 OMAP: PM: Fix build when CONFIG_PM_DEBUG isn't set
Since 6cdee91257 the references to
enable_off_mode and sleep_while_idle can't be resolved when CONFIG_PM_DEBUG
isn't set:
arch/arm/mach-omap2/built-in.o: In function `omap_uart_restore_context':
arch/arm/mach-omap2/serial.c:253: undefined reference to `enable_off_mode'
arch/arm/mach-omap2/built-in.o: In function `omap3_can_sleep':
arch/arm/mach-omap2/pm34xx.c:479: undefined reference to `sleep_while_idle'

Simply #define these in pm.h just like omap2_pm_debug.

Signed-off-by: Loïc Minier <loic.minier@linaro.org>
[khilman: moved down into existing #ifdef section]
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-10-01 13:50:34 -07:00
Santosh Shilimkar
eb6a2c7550 omap: pm: Move set_pwrdm_state routine to common pm.c
The set_pwrdm_state() is needed on omap4 as well so move
this routine to common pm.c file so that it's available for omap3/4

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-09-23 17:14:11 -07:00
Santosh Shilimkar
86b0c1e3c0 omap: pm-debug: Move common debug code to pm-debug.c
This patch moves omap2_pm_wakeup_on_timer() and pm debug entries
form pm34xx.c to pm-debug.c and export it, so that it is available
to other OMAPs

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-09-23 17:14:09 -07:00
Ari Kauppi
8e2efde9f1 OMAP3: PM: Add milliseconds interface to suspend wakeup timer
Millisecond resolution is possible and there are use cases for it
(automatic testing).

Seconds-based interface is preserved for compatibility.

Signed-off-by: Ari Kauppi <Ext-Ari.Kauppi@nokia.com>
Reviewed-by: Phil Carmody <ext-phil.2.carmody@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-05-12 09:39:00 -07:00