Commit Graph

4 Commits

Author SHA1 Message Date
Masahiro Yamada
4e03f628b4 mmc: sdhci-cadence: fix bit shift of read data from PHY port
This macro is currently unused, but it may be useful for debug use.
Fix it just in case.

Fixes: ff6af28faf ("mmc: sdhci-cadence: add Cadence SD4HC support")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-02-15 11:32:14 +01:00
Ulf Hansson
963836ad8f mmc: sdhci-cadence: Include mmc.h
Don't rely on host.h to include the mmc.h header, but instead include it
explicitly because the driver depends on it.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
2017-02-13 13:19:59 +01:00
Masahiro Yamada
5b311c1519 mmc: sdhci-cadence: add Socionext UniPhier specific compatible string
Add a Socionext SoC specific compatible (suggested by Rob Herring).

No SoC specific data are associated with the compatible strings for
now, but other SoC vendors may use this IP and want to differentiate
IP variants in the future.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-20 11:40:52 +01:00
Masahiro Yamada
ff6af28faf mmc: sdhci-cadence: add Cadence SD4HC support
Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller.

For SD, it basically relies on the SDHCI standard code.
For eMMC, this driver provides some callbacks to support the
hardware part that is specific to this IP design.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-08 15:02:52 +01:00