Rename mach-jmr3927 directory to more proper name to make adding other
platforms easier.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
It cannot be built for a long time and nobody maintains it.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Merge rbhma4200(RBTX4927/37) and rbhma4500(RBTX4938) defconfig into
single rbtx49xx defconfig. And jmr3927 defconfig is also updated.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Make single kernel can be used on RBTX4927/37/38. Also make
some SoC-specific code independent from board-specific code.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Split out PCIC dependent code and SoC dependent code from board dependent
code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code.
Also fix some build problems on CONFIG_PCI=n.
As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards
and PCI66 support is available for all TX49 boards.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Move arch/mips/{jmr3927,tx4927,tx4938} into arch/mips/txx9/ tree.
This will help more code sharing and maintainance.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
TXx9 GPIO set/get routines are spinlock-safe. This patch make
gpio_direction_{input,output} routines also spinlock-safe so that they
can be used during early board setup.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-ffunction-sections serves as a workaround for the problems caused by the
limited branch range in some inline assembler fragments for very large
compilation units.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Declare pci_probe_only, etc. in asm-mips/pci.h file. This will fix
some sparse warnings.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
SGI-IP28 is running in so called slow mode, when kernel is started
from the PROM. PROM calls must be done in slow mode otherwise the
PROM will issue an error. To get better memory performance we now
switch to normal mode, when the PROM is no longer needed.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The following errors were caught by sparse:
>>>>>>>>>>>
arch/mips/mips-boards/generic/display.c:30:6: warning: symbol
'mips_display_message' was not declared. Should it be static?
arch/mips/mips-boards/generic/display.c:58:6: warning: symbol
'mips_scroll_message' was not declared. Should it be static?
>>>>>>>>>>>
This patch includes the asm/mips-boards/prom.h header file into
arch/mips/mips-boards/generic/display.c. This adds the needed
function declarations, and the errors are gone.
Compile-tested using defconfigs for Malta, Atlas and SEAD boards.
Runtime test was successfully performed by booting a Malta 4Kc
board up to the shell prompt.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The gcmp_probe() function is needlessly defined global, and
this patch makes it static.
Tested by booting a Malta 4Kc board up to the shell prompt.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Both the fill_ipi_map() routine and the gic_intr_map array defined
in arch/mips/mips-boards/malta/malta_int.c are not used outside of
the latter file. Thus, these objects can become static. Moreover,
these two objects are used by the MT code only, which is why this
patch adds the appropriate ifdef.
While at it, this patch removes an unnecessary preprocessing macro
in favor of the commonly used ARRAY_SIZE.
Successfully tested using a Qemu-emulated Malta board for both SMP
and UP kernels.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The following symbols
hose_head
hose_tail
are needlessly defined global in arch/mips/pci/pci.c, and
this patch makes them static.
The variable pci_isa_hose is not used, and is removed by
this patch.
Spotted by namespacecheck. Tested by booting a Malta 4Kc
board up to the shell prompt.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The pit_clockevent symbol is needlessly defined global. This patch makes
that variable static.
Spotted by sparse. Compile-tested using Malta defconfig.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Both onboard controller of the O2 support FAST-20 transfer speeds,
but the bit, which signals that to the aic driver, isn't set. Instead
of adding detection code to the scsi driver, we just fake the missing
bit in the PCI config space of the scsi chips.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Never terribly functional or popular, plagued by hard to fix bugs the time
to say goodbye has more than arrived.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The following routines
allocate_irqno()
free_irqno()
seem not to be used outside of the core kernel code, hence
exporting these functions is pointless. This patch removes
the export.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The following routines
uasm_rel_highest()
uasm_rel_higher()
are needlessly defined global. This patch makes them static.
Compile-tested using a customized config for the Malta board. Booting
the same board up to the shell prompt was also successful with this
patch applied.
Spotted by sparse.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch fixes the following sparse warning:
<<<<<<<<
arch/mips/kernel/early_printk.c:35:13: warning: symbol 'setup_early_printk'
was not declared. Should it be static?
<<<<<<<<
The fix is to define a prototype of the setup_early_printk() function and
to include the appropriate header into arch/mips/kernel/early_printk.c.
[Ralf: Sorted includes again]
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The isa_slot_offset variable and its __ISA_IO_base macro is not used
anywhere anymore. It does not look like a decent interface per today's
standards either. Remove both including all places of initialization.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
It is not used anywhere in tree.
Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The generated copy_page for R4k CPU with a 128 byte cache line size used
Create Dirty Exclusive cache line operations even if only part of the
cache line was filled. This change avoids generating cache operations,
if only part of the cache line size is copied in one loop. It also
increases the maxmimum loop size, because the generated code even fits
into the available space for r4k CPUs with 128 byte cache line size.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Resolve these mismatches by defining affected functions with the __cpuinit
attribute, rather than __init.
Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The txx9_tmr_init() will not clear a timer counter register in a certain
case. The counter register is cleared on 1->0 transition of TCE bit if
CRE=1. So just clearing the TCE bit is not enough.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The introduction of a real dma cache invalidate makes it important
to have a correct cache line size, otherwise the kernel will gives
out two memory segment, which might share one cache line. The R4400
Indy/Indigo2 CPU modules are using a second level cache line size
of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
IP22.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
