Commit Graph

4 Commits

Author SHA1 Message Date
Uwe Kleine-König
980c51ab07 clocksource: sirf/marco+prima2: drop usage of CLOCK_TICK_RATE
Since CSR SiRF was converted to multi platform in cf82e0e (ARM: sirf:
enable multiplatform support) the symbol CLOCK_TICK_RATE isn't the
platform specific definition any more, but a global dummy value. There
was no harm introduced in cf82e0e because the global value happens to
match the old platform specific one, still this dummy value isn't
intended to be used and will hopefully disappear soon, so introduce a
local #define and use that instead.

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2013-12-20 11:41:34 +01:00
Stephen Boyd
130e6b25a2 clocksource: sirf: Switch to sched_clock_register() and use 64 bits
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface and use all 64 bits of this timer.

Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
2013-07-30 11:24:55 -07:00
Stephen Boyd
38ff87f77a sched_clock: Make ARM's sched_clock generic for all architectures
Nothing about the sched_clock implementation in the ARM port is
specific to the architecture. Generalize the code so that other
architectures can use it by selecting GENERIC_SCHED_CLOCK.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[jstultz: Merge minor collisions with other patches in my tree]
Signed-off-by: John Stultz <john.stultz@linaro.org>
2013-06-12 14:02:13 -07:00
Arnd Bergmann
275786b71d ARM: sirf: use clocksource_of infrastructure
This moves the two sirf clocksource drivers to drivers/clocksource
and integrates them into the framework for locating the clock sources
automatically.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Barry Song <Baohua.Song@csr.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
2013-03-25 12:29:41 +01:00