Commit Graph

10808 Commits

Author SHA1 Message Date
Alex Deucher
4878306935 drm/radeon/dpm: add checks against vblank time
If the vblank time is too short to adjust mclk,
assume multiple displays (no mclk adjustments).

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:20 -04:00
Alex Deucher
66edc1c95d drm/radeon/dpm: add helper to calculate vblank time
Required for checking vblank time for mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:09 -04:00
Alex Deucher
7e1f3c0419 drm/radeon: remove stray line in old pm code
Looks like a remnant from an old rebase.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:00 -04:00
Alex Deucher
222dc9a072 drm/radeon/dpm: fix display_gap programming on rv7xx
Check the driver state rather than the register as the
crtc registers may not be enabled yet.

Should fix:
https://bugzilla.kernel.org/show_bug.cgi?id=60510
https://bugs.freedesktop.org/show_bug.cgi?id=66651

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:39:51 -04:00
Alex Deucher
9b5de59629 drm/radeon/dpm: implement force performance level for TN
Allows you to force the selected performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:10:06 -04:00
Alex Deucher
5d5e559193 drm/radeon/dpm: implement force performance level for ON/LN
Allows you to force the selected performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:56 -04:00
Alex Deucher
a160a6a336 drm/radeon/dpm: implement force performance level for SI
Allows you to force the selected performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:48 -04:00
Alex Deucher
170a47f010 drm/radeon/dpm: implement force performance level for cayman
Allows you to force a performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:38 -04:00
Alex Deucher
8b5e6b7f0e drm/radeon/dpm: implement force performance levels for 7xx/eg/btc
Allows you to limit the selected power levels via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:30 -04:00
Alex Deucher
70d01a5ee2 drm/radeon/dpm: add infrastructure to force performance levels
This allows you to force specific power levels within a power
state.  Due to hardware restrictions between generations, the
interface is limited to the following 3 selections:

auto: all levels enabled
low: forced to the lowest power level
high: forced to the highest power level

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:19 -04:00
Alex Deucher
67d5ced503 drm/radeon: fix surface setup on r1xx
r1xx asics have a slightly different surface register
setup compared to newer asics.  There is no specific
enable bit for macro tiling, rather, to disable macro
tiling, you need to set the surface pitch to 0.

With this fixed, the special rn50 handling can go.

Noticed-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:11 -04:00
Alex Deucher
edcaa5b125 drm/radeon: add support for 3d perf states on older asics
Certain older rv770 asics have both a performance and
a 3D performance state rather than just multiple performance
levels in the state power state.  The current code would
select the performance state rather than the 3D performance
state when the "performance" profile was selected.  This change
switches to the "balanced" profile by default which ends up being
the internal performance profile.  When the user selects the
"performance" profile, it selects the internal 3D performance
state so the user can select the higher performance modes.

For most asics this changes nothing.  For certain rv770 asics
with static performance and 3D performance states, this allows
you to select between then using by selecting the "balanced"
and "performance" dpm profiles.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:02 -04:00
Alex Deucher
c6cf7777a3 drm/radeon: set default clocks for SI when DPM is disabled
Fix patching of vddc values for SI and enable manually forcing
clocks to default levels as per NI.

This improves the out of the box performance with SI asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:08:54 -04:00
Alex Deucher
338a95a955 drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag
Some asic revisions need to disable PG when UVD is active.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:31 -04:00
Alex Deucher
62fa44bf7b drm/radeon/tn: disable PG when changing UVD clocks
Causes hangs for some people.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:30 -04:00
Alex Deucher
2b90eddcd7 drm/radeon/sumo: disable PG when changing UVD clocks
Causes hangs for some people.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:30 -04:00
Alex Deucher
0124853eb1 drm/radeon/aruba: disable additional rlc features
They cause problems with dynamic clocking.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:29 -04:00
Alex Deucher
e631227f69 drm/radeon: fix endian bug in radeon_atom_get_mclk_range_table()
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:28 -04:00
Mike Lothian
bf0936e196 drm/radeon/dpm: fix compilation with certain versions of gcc
Add #include <linux/seq_file.h> to *_dpm.c files

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-02 18:32:01 -04:00
Alex Deucher
713759291c drm/radeon/dpm: clarify debugfs warning
For chips without debugfs dpm support say that it's not
implemented rather than not supported to avoid confusion
about DPM support in general.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-02 09:14:08 -04:00
Alex Deucher
7982128c3d drm/radeon/dpm: add debugfs support for SI
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:09:06 -04:00
Alex Deucher
bdf0c4f07d drm/radeon/dpm: add debugfs support for cayman
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:57 -04:00
Alex Deucher
490ab9314b drm/radeon/dpm: add debugfs support for TN
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:49 -04:00
Alex Deucher
fb70160c5f drm/radeon/dpm: add debugfs support for ON/LN
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:41 -04:00
Alex Deucher
bd210d11cd drm/radeon/dpm: add debugfs support for 7xx/evergreen/btc
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:32 -04:00
Alex Deucher
242916a5ee drm/radeon/dpm: add debugfs support for rv6xx
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:24 -04:00
Alex Deucher
1316b79256 drm/radeon/dpm: add infrastructure to support debugfs info
This lays the frameworks to report realtime power level
feedback.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:15 -04:00
Alex Deucher
7ad8d0687b drm/radeon/dpm: re-enable state transitions for Cayman
Was disabled due to stability issues on certain boards
caused by the a bug in the parsing of the atom mc reg tables.
That's fixed now so re-enable.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:07:18 -04:00
Alex Deucher
4b5c006ef2 drm/radeon/dpm: re-enable state transitions for BTC
Was disabled due to stability issues on certain boards
caused by the a bug in the parsing of the atom mc reg tables.
That's fixed now so re-enable.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:04:02 -04:00
Alex Deucher
4da18e26e0 drm/radeon: fix typo in radeon_atom_init_mc_reg_table()
Bad pointer math.  Fixes hangs in state transitions with
BTC+ asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 15:46:49 -04:00
Alex Deucher
5c7524bf06 drm/radeon/atom: fix endian bug in radeon_atom_init_mc_reg_table()
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 15:46:40 -04:00
Alex Deucher
aa71d830c4 drm/radeon: remove sumo dpm/uvd bringup leftovers
Function doesn't do anything useful.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 15:46:32 -04:00
Dave Airlie
f7d452f4fd Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- Various fixes that make surviving concurrent piglit more possible.
- Buffer object deletion no longer synchronous
- Context/register initialisation updates that have been reported to
solve some stability issues (particularly on some problematic GF119
chips)
- Kernel side support for VP2 video decoding engines

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (44 commits)
  drm/nvd0-/disp: handle case where display engine is missing/disabled
  drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4
  drm/nouveau/bsp/nv84: initial vp2 engine implementation
  drm/nouveau/vp/nv84: initial vp2 engine implementation
  drm/nouveau/core: xtensa engine base class implementation
  drm/nouveau/vdec: fork vp3 implementations from vp2
  drm/nouveau/core: move falcon class to engine/
  drm/nouveau/kms: don't fail if there's no dcb table entries
  drm/nouveau: remove limit on gart
  drm/nouveau/vm: perform a bar flush when flushing vm
  drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches
  drm/nvc8/gr: update initial register/context values
  drm/nvc4/gr: update initial register/context values
  drm/nvc1/gr: update initial register/context values
  drm/nvc3/gr: update initial register/context values
  drm/nvc0/gr: update initial register/context values
  drm/nvd9/gr: update initial register/context values
  drm/nve4/gr: update initial register/context values
  drm/nvc0-/gr: bump maximum gpc/tpc limits
  drm/nvf0/gr: initial register/context setup
  ...
2013-07-01 14:10:20 +10:00
Maarten Lankhorst
791dc143ed drm/nvd0-/disp: handle case where display engine is missing/disabled
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:50 +10:00
Ben Skeggs
e99716f13d drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4
No code changes, proven by envyas producing identical binaries.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:50 +10:00
Ilia Mirkin
05f9a5bc58 drm/nouveau/bsp/nv84: initial vp2 engine implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:49 +10:00
Ilia Mirkin
a0376b1481 drm/nouveau/vp/nv84: initial vp2 engine implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:49 +10:00
Ilia Mirkin
44b1e3bd6a drm/nouveau/core: xtensa engine base class implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:48 +10:00
Ilia Mirkin
0d4a1450c9 drm/nouveau/vdec: fork vp3 implementations from vp2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:48 +10:00
Ben Skeggs
a0fd4ec8f1 drm/nouveau/core: move falcon class to engine/
Not really "core" per-se.  About to merge Ilia's work adding another
similar class for the VP2 xtensa engines, so, seems like a good time to
move all these to engine/.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:47 +10:00
Ben Skeggs
d2898713fb drm/nouveau/kms: don't fail if there's no dcb table entries
Fixes module not loading on Tesla K20.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:46 +10:00
Maarten Lankhorst
79442c3af0 drm/nouveau: remove limit on gart
Most graphics cards nowadays have a multiple of this limit as their vram,
so limiting GART doesn't seem to make much sense.

Signed-off-by: Maarten >Lnkhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:43 +10:00
Maarten Lankhorst
36798b61ed drm/nouveau/vm: perform a bar flush when flushing vm
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes
internally".

nvidia always seems to do this flush after writing values.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:42 +10:00
Ben Skeggs
57f0ec159b drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:41 +10:00
Ben Skeggs
eb12f57be6 drm/nvc8/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:41 +10:00
Ben Skeggs
dba50728fd drm/nvc4/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:40 +10:00
Ben Skeggs
58ef23056a drm/nvc1/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:40 +10:00
Ben Skeggs
8b637ae3a3 drm/nvc3/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:39 +10:00
Ben Skeggs
d8b02dbbc3 drm/nvc0/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:39 +10:00
Ben Skeggs
37c3afd07c drm/nvd9/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:38 +10:00