Commit Graph

38 Commits

Author SHA1 Message Date
Mikko Perttunen
2a79c034b5 gpu: host1x: Disassemble more instructions
The disassembler for debug dumps was missing some newer host1x opcodes.
Add disassembly support for these.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20 14:19:52 +02:00
Mikko Perttunen
eb2ee1a28d gpu: host1x: Improve debug disassembly formatting
The host1x driver prints out "disassembly" dumps of the command FIFO
and gather contents on submission timeouts. However, the output has
been quite difficult to read with unnecessary newlines and occasional
missing parentheses.

Fix these problems by using pr_cont to remove unnecessary newlines
and by fixing other small issues.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20 14:19:52 +02:00
Mikko Perttunen
2316f29fb5 gpu: host1x: Enable gather filter
The gather filter is a feature present on Tegra124 and newer where the
hardware prevents GATHERed command buffers from executing commands
normally reserved for the CDMA pushbuffer which is maintained by the
kernel driver.

This commit enables the gather filter on all supporting hardware.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20 14:19:52 +02:00
Mikko Perttunen
c3f52220f2 gpu: host1x: Enable Tegra186 syncpoint protection
Since Tegra186 the Host1x hardware allows syncpoints to be assigned to
specific channels, preventing any other channels from incrementing
them.

Enable this feature where available and assign syncpoints to channels
when submitting a job. Syncpoints are currently never unassigned from
channels since that would require extra work and is unnecessary with
the current channel allocation model.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20 14:19:52 +02:00
Mikko Perttunen
f1b53c4e2c gpu: host1x: Add Tegra186 support
Add support for the implementation of Host1x present on the Tegra186.
The register space has been shuffled around a little bit, requiring
addition of some chip-specific code sections. Tegra186 also adds
several new features, most importantly the hypervisor, but those are
not yet supported with this commit.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20 14:19:51 +02:00
Mikko Perttunen
4ac45eb8d1 gpu: host1x: Fix bitshift/mask multipliers
Some parts of Host1x uses BIT_WORD/BIT_MASK/BITS_PER_LONG to calculate
register or field offsets. This worked fine on ARMv7, but now that
BITS_PER_LONG is 64 but our registers are still 32-bit things are
broken.

Fix by replacing..
- BIT_WORD with (x / 32)
- BIT_MASK with BIT(x % 32)
- BITS_PER_LONG with 32

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17 17:57:06 +02:00
Mikko Perttunen
8474b02531 gpu: host1x: Refactor channel allocation code
This is largely a rewrite of the Host1x channel allocation code, bringing
several changes:

- The previous code could deadlock due to an interaction
  between the 'reflock' mutex and CDMA timeout handling.
  This gets rid of the mutex.
- Support for more than 32 channels, required for Tegra186
- General refactoring, including better encapsulation
  of channel ownership handling into channel.c

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:25:38 +02:00
Mikko Perttunen
404bfb78da gpu: host1x: Add IOMMU support
Add support for the Host1x unit to be located behind
an IOMMU. This is required when gather buffers may be
allocated non-contiguously in physical memory, as can
be the case when TegraDRM is also using the IOMMU.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-05 18:11:43 +02:00
Thierry Reding
813a9d4ecd gpu: host1x: Remove redundant parentheses
There's no need to wrap the BIT() macro into an extra set of parentheses
because it's already implemented to use its own set.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:31 +02:00
Thierry Reding
0b8070d12e gpu: host1x: Whitespace cleanup for readability
Insert a number of blank lines in places where they increase readability
of the code. Also collapse various variable declarations to shorten some
functions and finally rewrite some code for readability.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:30 +02:00
Thierry Reding
6df633d0dc gpu: host1x: Fix a couple of checkpatch warnings
Fix a couple of occurrences where no blank line was used to separate
variable declarations from code or where block comments were wrongly
formatted.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:28 +02:00
Thierry Reding
5c0d8d386b gpu: host1x: Use unsigned int consistently for IDs
IDs can never be negative so use unsigned int. In some instances an
explicitly sized type (such as u32) was used for no particular reason,
so turn those into unsigned int as well for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:24 +02:00
Thierry Reding
14c95fc896 gpu: host1x: Consistently use unsigned int for counts
The number of channels, syncpoints, bases and mlocks can never be
negative, so use unsigned int instead of int. Also make loop variables
the same type for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:23 +02:00
Bhaktipriya Shridhar
57574bd779 gpu: host1x: hw: intr_hw: Remove create_workqueue
System workqueues have been able to handle high level of concurrency
for a long time now and there's no reason to use dedicated workqueues
just to gain concurrency. Since the workqueue host->intr_wq is involved
in sync point interrupts, and sync point wait and is not being used on
a memory reclaim path, dedicated host->intr_wq has been replaced with the
use of system_wq.

Unlike a dedicated per-cpu workqueue created with create_workqueue(),
system_wq allows multiple work items to overlap executions even on
the same CPU; however, a per-cpu workqueue doesn't have any CPU
locality or global ordering guarantees unless the target CPU is
explicitly specified and thus the increase of local concurrency
shouldn't make any difference.

cancel_work_sync() has been used  in _host1x_free_syncpt_irq() to ensure
that no work is pending by the time exit path runs.

Signed-off-by: Bhaktipriya Shridhar <bhaktipriya96@gmail.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:22 +02:00
Arnd Bergmann
287980e49f remove lots of IS_ERR_VALUE abuses
Most users of IS_ERR_VALUE() in the kernel are wrong, as they
pass an 'int' into a function that takes an 'unsigned long'
argument. This happens to work because the type is sign-extended
on 64-bit architectures before it gets converted into an
unsigned type.

However, anything that passes an 'unsigned short' or 'unsigned int'
argument into IS_ERR_VALUE() is guaranteed to be broken, as are
8-bit integers and types that are wider than 'unsigned long'.

Andrzej Hajda has already fixed a lot of the worst abusers that
were causing actual bugs, but it would be nice to prevent any
users that are not passing 'unsigned long' arguments.

This patch changes all users of IS_ERR_VALUE() that I could find
on 32-bit ARM randconfig builds and x86 allmodconfig. For the
moment, this doesn't change the definition of IS_ERR_VALUE()
because there are probably still architecture specific users
elsewhere.

Almost all the warnings I got are for files that are better off
using 'if (err)' or 'if (err < 0)'.
The only legitimate user I could find that we get a warning for
is the (32-bit only) freescale fman driver, so I did not remove
the IS_ERR_VALUE() there but changed the type to 'unsigned long'.
For 9pfs, I just worked around one user whose calling conventions
are so obscure that I did not dare change the behavior.

I was using this definition for testing:

 #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \
       unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO))

which ends up making all 16-bit or wider types work correctly with
the most plausible interpretation of what IS_ERR_VALUE() was supposed
to return according to its users, but also causes a compile-time
warning for any users that do not pass an 'unsigned long' argument.

I suggested this approach earlier this year, but back then we ended
up deciding to just fix the users that are obviously broken. After
the initial warning that caused me to get involved in the discussion
(fs/gfs2/dir.c) showed up again in the mainline kernel, Linus
asked me to send the whole thing again.

[ Updated the 9p parts as per Al Viro  - Linus ]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://lkml.org/lkml/2016/1/7/363
Link: https://lkml.org/lkml/2016/5/27/486
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-27 15:26:11 -07:00
Thierry Reding
a134789a67 gpu: host1x: Add Tegra210 support
The host1x unit found in Tegra210 SoCs is very similar to the unit in
Tegra124, but it has 2 additional channels for a total of 14 channels.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14 10:50:33 +01:00
Dmitry Osipenko
3fe2c7d4c8 gpu: host1x: Fix MLOCK's debug info
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-By: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-02 14:40:12 +02:00
Thierry Reding
ba73fbc2ca gpu: host1x: Print address/offset pairs consistently
Consistently use a format of %pad+%#x to print address/offset in debug
messages.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:41 +01:00
Thierry Reding
7f27d60b28 gpu: host1x: Fix typo in comment
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:38 +01:00
Thierry Reding
0169b93f44 gpu: host1x: Make mapped field of push buffers void *
This reduces the amount of casting that needs to be done to get rid of
annoying warnings on 64-bit builds.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:35 +01:00
Thierry Reding
b40d02bf96 gpu: host1x: Use struct host1x_bo pointers in traces
Rather than cast to a u32 use the struct host1x_bo pointers directly.
This avoid annoying warnings for 64-bit builds.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:32 +01:00
Stephen Warren
22bbd5d949 gpu: host1x: handle the correct # of syncpt regs
BIT_WORD() truncates rather than rounds, so the loops in
syncpt_thresh_isr() and _host1x_intr_disable_all_syncpt_intrs() use <=
rather than < in an attempt to process the correct number of registers
when rounding of the conversion of count of bits to count of words is
necessary. However, when rounding isn't necessary because the value is
already a multiple of the divisor (as is the case for all values of
nb_pts the code actually sees), this causes one too many registers to
be processed.

Solve this by using and explicit DIV_ROUND_UP() call, rather than
BIT_WORD(), and comparing with < rather than <=.

Fixes: 7ede0b0bf3 ("gpu: host1x: Add syncpoint wait and interrupts")
Cc: <stable@vger.kernel.org> # 3.10
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-16 17:11:04 +02:00
Thierry Reding
be2cd59b80 gpu: host1x: Remove unnecessary include
Nothing from the asm/mach/irq.h header is needed in this file, so there
is no need to include it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-01-14 14:39:45 +01:00
Thierry Reding
e6fff4aaf9 gpu: host1x: Add Tegra124 support
Tegra124 has 192 syncpoints whereas its predecessors had 32 syncpoints.
This required changes to the hardware register layout.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:52 +01:00
Thierry Reding
18b94f1cfb gpu: host1x: Use the correct HW headers for host1x02
An earlier patch added a subset of the required HW specific header files
but didn't actually include the right ones when compiling for host1x02.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:51 +01:00
Olof Johansson
43dd5554fc gpu: host1x: Silence a few warnings with LPAE=y
When building with LPAE=y (64-bit dma_addr_t), the following warnings are seen:

drivers/gpu/host1x/hw/cdma_hw.c:57:3: warning: format '%x' expects
  argument of type 'unsigned int', but argument 5 has type 'dma_addr_t'

drivers/gpu/host1x/hw/debug_hw.c:167:10: warning: format '%x' expects
  argument of type 'unsigned int', but argument 3 has type 'dma_addr_t'

The agreed-to solution for this is upcast to u64 and using %llx.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-28 15:13:47 +01:00
Arto Merilainen
f5a954fed9 gpu: host1x: Add syncpoint base support
This patch adds support for hardware syncpoint bases. This creates
a simple mechanism to stall the command FIFO until an operation is
completed.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:48 +01:00
Thierry Reding
5407f31bd3 gpu: host1x: Add support for Tegra114
Tegra114 uses a slightly updated version of host1x with an additional
syncpoint.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:41 +01:00
Thierry Reding
fc3be3e8fc gpu: host1x: Use relative include paths
This is slightly safer than adding -Idrivers/gpu/host1x to cflags-y.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:40 +01:00
Thierry Reding
35d747a81d gpu: host1x: Expose syncpt and channel functionality
Expose the buffer objects, syncpoint and channel functionality in the
public public header so that drivers can use them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:20:11 +01:00
Thierry Reding
e1e906448d gpu: host1x: Make host1x header file public
In preparation to support host1x clients other than DRM, move this
header into a public location.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:20:10 +01:00
Thierry Reding
9eb9b220fc gpu: host1x: Cleanup includes
Most of the included files are either not required or already included
by some other header file.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:20:07 +01:00
Thierry Reding
474318cabc gpu: host1x: Remove unused Makefile
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:20:04 +01:00
Arto Merilainen
ebae30b1fb gpu: host1x: Rework CPU syncpoint increment
This patch merges host1x_syncpt_cpu_incr to host1x_syncpt_incr() as
they are in practise doing the same thing. host1x_syncpt_incr() is
also modified to return error codes. User space interface is modified
accordingly to pass return values.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2013-06-22 12:43:55 +02:00
Terje Bergstrom
6236451d83 gpu: host1x: Add debug support
Add support for host1x debugging. Adds debugfs entries, and dumps
channel state to UART in case of stuck job.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-04-22 12:32:46 +02:00
Terje Bergstrom
6579324a41 gpu: host1x: Add channel support
Add support for host1x client modules, and host1x channels to submit
work to the clients.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-04-22 12:32:43 +02:00
Terje Bergstrom
7ede0b0bf3 gpu: host1x: Add syncpoint wait and interrupts
Add support for sync point interrupts, and sync point wait. Sync
point wait used interrupts for unblocking wait.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-04-22 12:32:42 +02:00
Terje Bergstrom
7547168743 gpu: host1x: Add host1x driver
Add host1x, the driver for host1x and its client unit 2D. The Tegra
host1x module is the DMA engine for register access to Tegra's
graphics- and multimedia-related modules. The modules served by
host1x are referred to as clients. host1x includes some other
functionality, such as synchronization.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2013-04-22 12:32:40 +02:00