This patch fix spelling typo in Documentation/DocBook.
It is because .html and .xml files are generated by make htmldocs,
I have to fix a typo within the source files.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
We cannot unconditionally use dma_map_single() to map data for use with
SPI since transfers may exceed a page and virtual addresses may not be
provided with physically contiguous pages. Further, addresses allocated
using vmalloc() need to be mapped differently to other addresses.
Currently only the MXS driver handles all this, a few drivers do handle
the possibility that buffers may not be physically contiguous which is
the main potential problem but many don't even do that. Factoring this
out into the core will make it easier for drivers to do a good job so if
the driver is using the core DMA code then generate a scatterlist
instead of mapping to a single address so do that.
This code is mainly based on a combination of the existing code in the MXS
and PXA2xx drivers. In future we should be able to extend it to allow the
core to concatenate adjacent transfers if they are compatible, improving
performance.
Currently for simplicity clients are not allowed to use the scatterlist
when they do DMA mapping, in the future the existing single address
mappings will be replaced with use of the scatterlist most likely as
part of pre-verifying transfers.
This change makes it mandatory to use scatterlists when using the core DMA
mapping so update the s3c64xx driver to do this when used with dmaengine.
Doing so makes the code more ugly but it is expected that the old s3c-dma
code can be removed very soon.
Signed-off-by: Mark Brown <broonie@linaro.org>
It is fairly common for SPI devices to require that one or both transfer
directions is always active. Currently drivers open code this in various
ways with varying degrees of efficiency. Start factoring this out by
providing flags SPI_MASTER_MUST_TX and SPI_MASTER_MUST_RX. These will cause
the core to provide buffers for the requested direction if none are
specified in the underlying transfer.
Currently this is fairly inefficient since we actually allocate a data
buffer which may get large, support for mapping transfers using a
scatterlist will allow us to avoid this for DMA based transfers.
Signed-off-by: Mark Brown <broonie@linaro.org>
The process of DMA mapping buffers for SPI transfers does not vary between
devices so in order to save duplication of code in drivers this can be
factored out into the core, allowing it to be integrated with the work that
is being done on factoring out the common elements from the data path
including more sharing of dmaengine code.
In order to use this masters need to provide a can_dma() operation and while
the hardware is prepared they should ensure that DMA channels are provided
in tx_dma and rx_dma. The core will then ensure that the buffers are mapped
for DMA prior to calling transfer_one_message().
Currently the cleanup on error is not complete, this needs to be improved.
Signed-off-by: Mark Brown <broonie@linaro.org>
The transfer_one_message callback handles messages, not transfers.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Mark Brown <broonie@linaro.org>
Explicitly note the transfer_one and transfer_one_message are mutually
exclusive, to make the text a little more newcomers friendly.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Mark Brown <broonie@linaro.org>
A respun version of the merges for the pull request previously sent with
a few additional fixes. The last two merges were fixed up by hand since
the branches have moved on and currently have the prior merge in them.
Quite a busy release for the SPI subsystem, mostly in cleanups big and
small scattered through the stack rather than anything else:
- New driver for the Broadcom BC63xx HSSPI controller.
- Fix duplicate device registration for ACPI.
- Conversion of s3c64xx to DMAEngine (this pulls in platform and DMA
changes upon which the transiton depends).
- Some small optimisations to reduce the amount of time we hold locks
in the datapath, eliminate some redundant checks and the size of a
spi_transfer.
- Lots of fixes, cleanups and general enhancements to drivers,
especially the rspi and Atmel drivers.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJS4RZvAAoJELSic+t+oim9XKAP/00WcCARVzqWmzZYhW2nCqVw
zRu/DEC+RFlvUSOrwx5SojZNCJekKrsbJuzvapXKIj+SL5+wDm2gUo188s+J8e5V
mXA9CGb2+tQUgzuQzKZ82kf5WT1a/VpgdVqxZ2EGBHqdJwMV6cG20YneTd9/A0ar
QbD9Ikon07cE6j8sp/HKxzSnER+3ii4OTJPJCXkNPHiDE9xkA/FR4qy/DksC2hpy
y6IHCNGA3yHB/8bC7hxUKabOBwPpvQlGELTLHKTVy4umoAE0/aYSjwMdE67SbqXg
mxDLcDjacNb4ga9hfWiYdZOKRdYiljt1zXksKHldp+R654YFTSVGmYipMoc0l52b
jyycLM9ZjQ8Q74ySY+BIdZ4RDKFg4QajDhd/sIJtI354HLdoJCQa82j3luj6/Ewu
JSlI4EGZUjOWPZb72kkrwj0LFBT5k639fMmLPDCLLlg5sUvx2afFl96s9Z25mFGj
JzgwhjBIcF8AmllLTEpS6cP8MOBeThJ79gTxmbH60tsWxil2yCS4etg+h6GFo7g9
GBXL9UF63Q6t9Mg8/0oACDs/YyMMbFImi6p20B+Pr0QZiltiTSSc4Z7eo4gG4UYh
m4svqZcMG8w6csMAMb6I6a9+EojERPt53bZayasnnX/e5HsXJah4qop9Pjrma4ed
PQHMx8ivWztwyqqjoYTz
=CbUw
-----END PGP SIGNATURE-----
Merge tag 'spi-v3.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"A respun version of the merges for the pull request previously sent
with a few additional fixes. The last two merges were fixed up by
hand since the branches have moved on and currently have the prior
merge in them.
Quite a busy release for the SPI subsystem, mostly in cleanups big and
small scattered through the stack rather than anything else:
- New driver for the Broadcom BC63xx HSSPI controller
- Fix duplicate device registration for ACPI
- Conversion of s3c64xx to DMAEngine (this pulls in platform and DMA
changes upon which the transiton depends)
- Some small optimisations to reduce the amount of time we hold locks
in the datapath, eliminate some redundant checks and the size of a
spi_transfer
- Lots of fixes, cleanups and general enhancements to drivers,
especially the rspi and Atmel drivers"
* tag 'spi-v3.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (112 commits)
spi: core: Fix transfer failure when master->transfer_one returns positive value
spi: Correct set_cs() documentation
spi: Clarify transfer_one() w.r.t. spi_finalize_current_transfer()
spi: Spelling s/finised/finished/
spi: sc18is602: Convert to use bits_per_word_mask
spi: Remove duplicate code to set default bits_per_word setting
spi/pxa2xx: fix compilation warning when !CONFIG_PM_SLEEP
spi: clps711x: Add MODULE_ALIAS to support module auto-loading
spi: rspi: Add missing clk_disable() calls in error and cleanup paths
spi: rspi: Spelling s/transmition/transmission/
spi: rspi: Add support for specifying CPHA/CPOL
spi/pxa2xx: initialize DMA channels to -1 to prevent inadvertent match
spi: rspi: Add more QSPI register documentation
spi: rspi: Add more RSPI register documentation
spi: rspi: Remove dependency on DMAE for SHMOBILE
spi/s3c64xx: Correct indentation
spi: sh: Use spi_sh_clear_bit() instead of open-coded
spi: bitbang: Grammar s/make to make/to make/
spi: sh-hspi: Spelling s/recive/receive/
spi: core: Improve tx/rx_nbits check comments
...
The documentation for spi_master.set_cs() says:
assert or deassert chip select, true to assert
i.e. its "enable" parameter uses assertion-level logic.
This does not match the implementation of spi_set_cs(), which calls
spi_master.set_cs() with the wanted logic level of the chip select line,
which depends on the polarity of the chip select signal.
Correct the documentation to match the implementation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
spi_write_then_read() takes a "void *" for rxbuf, so there's no need to
cast the buffer pointer to "u8 *".
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Trent Piepho observed that since the current realistic maximum number of
data lines is four we can pack the spi_transfer struct more efficiently
if we use a bitfield for the number of bits, allowing the fields to fit
in a single byte along with cs_change.
If space becomes an issue further optimiation is possible by only using
the constants and packing the values chosen for them.
Reported-by: Trent Piepho <tpiepho@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
fiq.h contains only a function declaration and is not used by anyone
else. Move the declaration to the driver header file and remove the
unnecessary platform dependency from the driver.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Now that spi_device->mode is a u16, the chip_select, bits_per_mode,
and mode fields pack poorly, taking 8 bytes: four data and four
padding. By moving (u8)bits_per_word up one position, to after
(u8)chip_select, they pack better and only use 4 bytes.
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Sourav Poddar <sourav.poddar@ti.com>g
Signed-off-by: Mark Brown <broonie@linaro.org>
Commit 20bc4d5d56
(gpio: 74x164: Add support for the daisy-chaining) introduce check
for DT for the driver, so driver cannot be used without DT.
There are no in-tree users of this driver, so remove non-DT support
completely.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The loops which SPI controller drivers use to process the list of transfers
in a spi_message are typically very similar and have some error prone areas
such as the handling of /CS. Help simplify drivers by factoring this code
out into the core - if drivers provide a transfer_one() function instead
of a transfer_one_message() function the core will handle processing at the
message level.
/CS can be controlled by either setting cs_gpio or providing a set_cs
function. If this is not possible for hardware reasons then both can be
omitted and the driver should continue to implement manual /CS handling.
This is a first step in refactoring and it is expected that there will be
further enhancements, for example factoring out of the mapping of transfers
for DMA and the initiation and completion of interrupt driven transfers.
Signed-off-by: Mark Brown <broonie@linaro.org>
Many SPI drivers perform setup and tear down on every message, usually
doing things like DMA mapping the message. Provide hooks for them to use
to provide such operations.
This is of limited value for drivers that implement transfer_one_message()
but will be of much greater utility with future factoring out of standard
implementations of that function.
Signed-off-by: Mark Brown <broonie@linaro.org>
This patch adds a new spi_w8r16be() helper, which is similar to spi_w8r16()
except that it converts the read data word from big endian to native endianness
before returning it. The reason for introducing this new helper is that for SPI
slave devices it is quite common that the read 16 bit data word is in big
endian. So users of spi_w8r16() have to convert the result to native endianness
manually. A second reason is that in this case the endianness of the return
value of spi_w8r16() depends on its sign. If it is negative (i.e. a error code)
it is already in native endianness, if it is positive it is in big endian. The
sparse code checker doesn't like this kind of mixed endianness and special
annotations are necessary to keep it quiet (E.g. casting to be16 using __force).
Doing the conversion to native endianness in the helper function does not
require such annotations since we are not mixing different endiannesses in the
same variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Help simplify the cleanup code for SPI master drivers by providing a
managed master registration function, ensuring that the master is
automatically unregistered whenever the device is unbound.
Signed-off-by: Mark Brown <broonie@linaro.org>
The R8A7790 has QSPI module which is very similar to RSPI.
This patch adds into RSPI module together to supports QSPI module.
Signed-off-by: Hiep Cao Minh <cm-hiep@jinso.co.jp>
Signed-off-by: Mark Brown <broonie@linaro.org>
Core:
- Support Allocation Units 8MB-64MB in SD3.0, previous max was 4MB.
- The slot-gpio helper can now handle GPIO debouncing card-detect.
- Read supported voltages from DT "voltage-ranges" property.
Drivers:
- dw_mmc: Add support for ARC architecture, and support exynos5420.
- mmc_spi: Support CD/RO GPIOs.
- sh_mobile_sdhi: Add compatibility for more Renesas SoCs.
- sh_mmcif: Add DT support for DMA channels.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.13 (GNU/Linux)
iQIcBAABAgAGBQJSLxu8AAoJEHNBYZ7TNxYMkV8P/RZMkP3L88wPmvdQ4IxVD/Bg
jphPsZTAlY8pLY7EcBVfbIGfBMMoVZ8CayuAbj9u5jFiMBNDUKRnKrky1m95F62n
xXiS5vUiKdWpByMpfKmrqvJr6eS8SWq5z/yug1c3s1Y9T363KgfypgJLvNgbMGiv
qbmjE+Zw65nMwHCk+4Rvq6s4aN6KosRZP0ABsn1foXt3kybSgemp5ShrlEyXohfS
E91EiYxHFC4fdmuWiZZvL1tyHFeV25omyZA90mpkioNItiwoyOM2rfjfEfNq+WBw
UrmdBesbGsF0Zi12CBa9LtzdRjYK8PugBWKW3mycS5++NX9KW6Ac/EpGqFeH9KgL
WZ2v4aQjkbnzQKUB2HcWAyXm88G9MkNvpLbIrmIPtson+q0UjgPYWe5BI3dy/Y1v
YS1JeseslVtSTKzGYsa1GJ7Nc1xYiILRz0RS4YGYXNjwvrl89i2UH7cglYDW36Xd
vxvRBaFpVsj1mfjjITEoG6nE0v5aYH6gSITY79XR+/kN871/99/oIUaWdpjcm9yv
SIYmK7ipcvxugkQ7BoMGbym/dvuUrZ+Vnf8dFlGPTJegZVsnfgrVAnRpvcVwW8+x
4Z79wUPSIETRqj2XX2I/Y0JnrXry+dLLVyeK1tELoeOKev73Ai2lcqPSz6J0tzJs
IErcz0hM1znL2RtgNwio
=+EYB
-----END PGP SIGNATURE-----
Merge tag 'mmc-updates-for-3.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc
Pull MMC updates from Chris Ball:
"MMC highlights for 3.12:
Core:
- Support Allocation Units 8MB-64MB in SD3.0, previous max was 4MB.
- The slot-gpio helper can now handle GPIO debouncing card-detect.
- Read supported voltages from DT "voltage-ranges" property.
Drivers:
- dw_mmc: Add support for ARC architecture, and support exynos5420.
- mmc_spi: Support CD/RO GPIOs.
- sh_mobile_sdhi: Add compatibility for more Renesas SoCs.
- sh_mmcif: Add DT support for DMA channels"
* tag 'mmc-updates-for-3.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc: (50 commits)
Revert "mmc: tmio-mmc: Remove .set_pwr() callback from platform data"
mmc: dw_mmc: Add support for ARC
mmc: sdhci-s3c: initialize host->quirks2 for using quirks2
mmc: sdhci-s3c: fix the wrong register value, when clock is disabled
mmc: esdhc: add support to get voltage from device-tree
mmc: sdhci: get voltage from sdhc host
mmc: core: parse voltage from device-tree
mmc: omap_hsmmc: use the generic config for omap2plus devices
mmc: omap_hsmmc: clear status flags before starting a new command
mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
mmc: sh_mmcif: revision-specific CLK_CTRL2 handling
mmc: sh_mmcif: revision-specific Command Completion Signal handling
mmc: sh_mmcif: add support for Device Tree DMA bindings
mmc: sh_mmcif: move header include from header into .c
mmc: SDHI: add DT compatibility strings for further SoCs
mmc: dw_mmc-pci: enable bus-mastering mode
mmc: dw_mmc-pci: get resources from a proper BAR
mmc: tmio-mmc: Remove .set_pwr() callback from platform data
mmc: tmio-mmc: Remove .get_cd() callback from platform data
mmc: sh_mobile_sdhi: Remove .set_pwr() callback from platform data
...
All platforms now pass the CD and RO GPIOs to the MMC SPI driver, those
callbacks are not used anymore. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Add support for passing CD/RO GPIO numbers directly to the mmc_spi
driver instead of relying solely on board code callbacks to retrieve the
CD/RO signals values. The driver will enable debouncing on the card
detect GPIO if the cd_debounce field is set to a non-zero value.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = <1/2/4>" in place of using
"spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
(1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
single, dual and quad.
(2)keep tx_nbits and rx_nbits are contained by @spi_device->mode
example: if @spi_device->mode = DUAL, then tx/rx_nbits can not be set
to QUAD(SPI_NBITS_QUAD)
(3)if "@spi_device->mode & SPI_3WIRE", then tx/rx_nbits should be in
single(SPI_NBITS_SINGLE)
Signed-off-by: wangyuhang <wangyuhang2014@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
On a 64-bit platform, ~0UL fills 64-bits, which causes SPI_BIT_MASK(32)
not to fit into 32 bits. This causes a warning when the result is assigned
to a 32-bit variable. Use ~0U instead to prevent this. This fixes:
drivers/spi/spi-gpio.c: In function 'spi_gpio_probe':
drivers/spi/spi-gpio.c:446:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Most SPI drivers that implement runtime PM support use identical code to
do so: they acquire a runtime PM lock in prepare_transfer_hardware() and
then they release it in unprepare_transfer_hardware(). The variations in
this are mostly missing error checking and the choice to use autosuspend.
Since these runtime PM calls are normally the only thing in the prepare
and unprepare callbacks and the autosuspend API transparently does the
right thing on devices with autosuspend disabled factor all of this out
into the core with a flag to enable the behaviour.
Signed-off-by: Mark Brown <broonie@linaro.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Make spi core calculate the message length while
populating the other transfer parameters.
Usecase, driver can use it to populate framelength filed in their
controller.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Convert drivers using bitbang to use the core mesasge pump infrastructure,
saving some code and meaning that these drivers get to take advantage of
work done on improving the core implementation.
Signed-off-by: Mark Brown <broonie@linaro.org>
Allow drivers to avoid implementing their own checks for simple rates by
specifying the limits in the master structure.
Signed-off-by: Mark Brown <broonie@linaro.org>
Currently no drivers use the ability to override spi_bitbang_transfer()
and if any started this would make it harder to convert the bitbang code
to use transfer_one_message() so remove the export in order to prevent
anyone starting.
Signed-off-by: Mark Brown <broonie@linaro.org>
Do not load endian value from platform data
and rather autodetect it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one
representing support for all bits up-to-and-including the "max" supported
value, and one representing support for all bits up-to-but-not-including
the "min" supported value, and then taking the difference between the
two, resulting in a mask representing support for all bits between
(inclusive) the min and max values.
However, the second mask ended up representing all bits up-to-and-
including rather up-to-but-not-including. Fix this bug.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The parameters to SPI_BPW_RANGE_MASK() are in the range 1..32. If 32 is
used as a parameter, part of the expression is "1 << 32". Since 32 is >=
the size of the type in use, such a shift is undefined behaviour. Add
macro SPI_BIT_MASK to Implement a special case and thus avoid undefined
behaviour. Use this new macro rather than BIT() when implementing
SPI_BPW_RANGE_MASK().
This fixes build warnings such as:
drivers/spi/spi-gpio.c:446:2: warning: left shift count >= width of type [enabled by default]
SPI_BPW_MASK() already avoids this, since its parameter is also in range
1..32, yet it only shifts by up to one less than the input parameter.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Introduce two macros to make setting up spi_master.bits_per_word_mask
easier, and avoid mistakes like writing BIT(n) instead of BIT(n - 1).
SPI_BPW_MASK is for a single supported value of bits_per_word_mask.
SPI_BPW_RANGE_MASK represents a contiguous set of bit lengths.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
