Commit Graph

10 Commits

Author SHA1 Message Date
Young_X
cd7fdc45bc
ASoC: au8540: use 64-bit arithmetic instead of 32-bit
Add suffix ULL to constant 256 in order to give the compiler complete
information about the proper arithmetic to use.

Notice that such constant is used in a context that expects an
expression of type u64 (64 bits, unsigned) and the following
expression is currently being evaluated using 32-bit arithmetic:

    256 * fs * 2 * mclk_src_scaling[i].param

Signed-off-by: Young_X <YangX92@hotmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-29 11:44:49 +00:00
Colin Ian King
d101f9b96e
ASoC: nau8540: remove redundant variable osrate
Variable osrate is being assigned but is never used hence it is
redundant and can be removed.

Cleans up clang warning:
warning: variable 'osrate' set but not used [-Wunused-but-set-variable]

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-08-01 12:16:22 +01:00
Kuninori Morimoto
415bc3a0bf
ASoC: nau8540: replace codec to component
Now we can replace Codec to Component. Let's do it.

Note:
	xxx_codec_xxx()		->	xxx_component_xxx()
	.idle_bias_off = 0	->	.idle_bias_on = 1
	.ignore_pmdown_time = 0	->	.use_pmdown_time = 1
	-			->	.endianness = 1
	-			->	.non_legacy_dai_naming = 1

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-02-12 09:59:09 +00:00
John Hsu
fe83b1b7d7
ASoC: nau8540: improve FLL performance
Add these parameters to improve the FLL performance.
The comments show as follows:

(1)ICTRL_LATCH: FLL DSP speed capability control
When FLL running at high frequency with long decimal number, DSP needs
to operate at high speed. FLL DSP can optimize between performance and
power consumption by ICTRL_LATCH.(111 has highest power consumption.)
The default setting can be used to reduce power.
(2)CUTOFF500: loop filter cutoff frequency at 500Khz
It will give the best FLL performance but highest power consumption
to enable the cutoff frequency. FLL Loop Filter enable to reduce FLL
output noise, especially,(DCO frequency)/(FLL input reference frequency)
is not a integer.
(3)GAIN_ERR: FLL gain error correction threshold setting
The threshold is comparison between DCO and target frequency.
The value 1111 has the most sensitive threshold, that is, 1111 can have
the most accurate DCO to target frequency. However, the gain error setting
conditionally and inversely depends on FLL input reference clock rate.
Higher FLL reference input frequency can only set lower gain error, such
as 0000 for input reference from MCLK=12.288Mhz. On the other side, if FLL
reference input is from Frame Sync, 48KHz, higher error gain can apply
such as 1111.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-16 11:59:52 +00:00
John Hsu
6573c0510b
ASoC: nau8540: fix the record pop noise
When the record starts, the driver turns on MICBIAS and the voltage is
pulled up for an instant. If the receiver starts to capture the signal
between the instant, there is an pop noise in the stream beginning.
To avoid the pop noise, the driver makes a delay in the sequence.
After MICBIAS powered up, the driver waits 300 ms for the voltage
going down. Then turns on the ADC output, and sends signal to receiver.
The pop noise can be erased.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-07 11:29:01 +01:00
John Hsu
14323ff8c2
ASoC: nau8540: PGA short to ground
Change channel PGA input mode selection for better recording quality.
The patch shorts the inputs to ground with 12kOhm differentially
terminated.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-07 11:28:48 +01:00
John Hsu
e4d0db60e8
ASoC: nau8540: reset state machine for channel phase sync
The four channel ADCs in NAU85L40 have difference control registers,
it is hard to synchronous these four channels without correct sequence.
The phase difference will not be a constant and not to conjecture easily.
It may be 2.55 degree, or more ,or less.
Intended to prevent phase difference of channels, the solution as follows:
(1)Channel_Sync need to be enabled.
(2)Do soft reset without affecting register when recording done.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-07 11:28:35 +01:00
Bhumika Goyal
a180ba45b1 ASoC: codecs: add const to snd_soc_codec_driver structures
Declare snd_soc_codec_driver structures as const as they are only passed
as an argument to the function snd_soc_register_codec. This argument is
of type const, so declare the structures with this property as const.
In file codecs/sn95031.c, snd_soc_codec_driver structure is also used in
a copy operation along with getting passed to snd_soc_register_codec.
So, it can be made const too.
Done using Coccinelle:

@match disable optional_qualifier@
identifier s;
position p;
@@
static struct snd_soc_codec_driver s@p={...};

@good1@
identifier match.s;
position p;
@@
snd_soc_register_codec(...,&s@p,...)

@bad@
identifier match.s;
position p!={match.p,good1.p};
@@
s@p

@depends on !bad disable optional_qualifier@
identifier match.s;
@@
static
+const
struct snd_soc_codec_driver s={...};

Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-08-10 16:10:50 +01:00
John Hsu
babd658503 ASoC: nau8540: fix tab conversion problem
Fix the tab converting to space problem.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-04-18 18:05:19 +01:00
John Hsu
c1644e3de4 ASoC: nau8540: new codec driver
Add codec driver of NAU85L40

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-02-04 12:37:26 +01:00