Commit Graph

5 Commits

Author SHA1 Message Date
Stefan Agner
3b60a26fdc ARM: imx: clk-vf610: fix SAI clock tree
The Synchronous Audio Interface (SAI) instances are clocked by
independent clocks: The bus clock and the audio clock (as shown in
Figure 51-1 in the Vybrid Reference Manual). The clock gates in
CCGR0/CCGR1 for SAI0 through SAI3 are bus clock gates, as access
tests to the registers with/without gating those clocks have shown.
The audio clock is gated by the SAIx_EN gates in CCM_CSCDR1,
followed by a clock divider (SAIx_DIV). Currently, the parent of
the bus clock gates has been assigned to SAIx_DIV, which is not
involved in the bus clock path for the SAI instances (see chapter
9.10.12, SAI clocking in the Vybrid Reference Manual).

Fix this by define the parent clock of VF610_CLK_SAIx to be the bus
clock.

If the driver needs the audio clock (when used in master mode), a
fixed device tree is required which assign the audio clock properly
to VF610_CLK_SAIx_DIV.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-12-02 09:46:26 +08:00
Sanchayan Maity
0753f56e41 clk: clk-vf610: Add clock for Vybrid OCOTP controller
Add clock support for Vybrid On-Chip One Time Programmable
(OCOTP) controller.

While the OCOTP block does not require explicit clock gating,
for programming the OCOTP timing register the clock rate of
ipg clock is required for timing calculations related to fuse
and shadow register read sequence. We explicitly specify the
ipg clock for OCOTP as a result.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-09-22 18:02:40 -07:00
Mirza Krak
fbfd617ea4 ARM: imx: clk-v610: Add clock for I2C2 and I2C3
Add support for clock gating of I2C2 and I2C3.
We use I2C2 in a (not yet mainlined) device tree.

Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-06-03 14:49:38 +08:00
Stefan Agner
d930d56825 ARM: imx: clk-vf610: enable debug access port by default
Enabled DAP (debug access port) by default. This enables the hw-
breakpoint framework to make use of the breakpoints and watchpoints
supported by hardware.

[    0.215805] hw-breakpoint: found 2 (+1 reserved) breakpoint and 1 watchpoint registers.
[    0.224624] hw-breakpoint: maximum watchpoint size is 4 bytes.

Without this clock, the hw-breakpoint driver claims an undefined
instruction during initialization:
[    0.227380] hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
[    0.227519] hw-breakpoint: CPU 0 failed to disable vector catch

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-06-03 14:49:36 +08:00
Shawn Guo
11f6812009 ARM: imx: move clock drivers into drivers/clk
After the cleanup on clock drivers, they are now ready to be moved into
drivers/clk.  Let's move them into drivers/clk/imx folder.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-03 14:44:33 +08:00