pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.
Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.
e.g. before fix, the pll tree is:
osc 6 6 24000000 0 0
pll1_bypass_src 0 0 24000000 0 0
pll1 0 0 792000000 0 0
pll1_bypass 0 0 792000000 0 0
pll1_sys 0 0 792000000 0 0
After the fix, it's:
osc 6 6 24000000 0 0
pll1 0 0 792000000 0 0
pll1_bypass 0 0 792000000 0 0
pll1_sys 0 0 792000000 0 0
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.
We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.
So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
After the cleanup on clock drivers, they are now ready to be moved into
drivers/clk. Let's move them into drivers/clk/imx folder.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
