Commit Graph

11 Commits

Author SHA1 Message Date
Paul Mundt
8263a67e16 sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-17 17:49:49 +09:00
Yoshihiro Shimoda
2f47f44790 sh: Support fixed 32-bit PMB mappings from bootloader.
This provides a method for supporting fixed PMB mappings inherited from
the bootloader, as an alternative to the dynamic PMB mapping currently
used by the kernel. In the future these methods will be combined.

P1/P2 area is handled like a regular 29-bit physical address, and local
bus device are assigned P3 area addresses.

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-10 15:49:54 +09:00
Paul Mundt
a99d6fde69 sh: Convert sh64 /proc/asids to debugfs and generic sh.
This converts the sh64 /proc/asids entry to debugfs and enables it for
all SH parts that have debugfs enabled.

On MMU systems this can be used to determine which processes are using
which ASIDs which in turn can be used for finer grained cache tag
analysis.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-12-22 18:44:03 +09:00
Paul Mundt
185aed7557 sh: Provide a sane valid_phys_addr_range() to prevent TLB reset with PMB.
With the PMB enabled, only P1SEG and up are covered by the PMB mappings,
meaning that situations where out-of-bounds physical addresses are read
from will lead to TLB reset after the PMB miss, allowing for use cases
like dd if=/dev/mem to reset the TLB.

Fix this up to make sure the reference is between __MEMORY_START (phys)
and __pa(high_memory). This is coherent across all variants of sh/sh64
with and without MMU, though the PMB bug itself is only applicable to
SH-4A parts.

Reported-by: Hideo Saito <saito@densan.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-11-12 12:53:48 +09:00
Yoshinori Sato
cce2d453e4 SH2(A) cache update
Includes:
- SH2 (7619) Writeback support.
- SH2A cache handling fix.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-08-04 16:33:47 +09:00
Paul Mundt
9895f9429c sh: clear/copy_page renames in lib and lib64.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:54 +09:00
Paul Mundt
efddb4c882 sh: Rename the _32 and _64 TLB flush variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:54 +09:00
Paul Mundt
811d50cb43 sh: Move in the SH-5 TLB miss.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:50 +09:00
Paul Mundt
3eeffb3204 sh: Split out tlb-flush in to _32 and _64 variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:47 +09:00
Paul Mundt
ad81eb9173 sh: Split out ioremap in to _32 and _64 variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:46 +09:00
Paul Mundt
83ce3ac1d1 sh: Split out extable.c _32 and _64 variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:44 +09:00