For the gate part of the peripheral clock setting the bit disables the
clock and clearing it enables the clock. This is not the default behavior
of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Fixes: 8ca4746a78 ("clk: mvebu: Add the peripheral clock driver for Armada 3700")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
While trying using a peripheral clock on a driver, I saw that the clock
pointer returned by the provider was NULL.
The problem was a missing indirection. It was the pointer stored in the
hws array which needed to be updated not the value it contains.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Fixes: 8ca4746a78 ("clk: mvebu: Add the peripheral clock driver for Armada 3700")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
These clocks are the ones which will be used as source for the
peripherals of the Armada 3700 SoC. On this SoC there is two blocks of
clocks: the North bridge one and the South bridge one.
Most of them are gatable. Most of the time their rate are their parent
rated divided by a ratio depending of two registers. Their parent can be
choose between the TBG clocks for most of them.
However, some of them can't choose their parent or directly depend of the
xtal clocks. Other ones do not use exactly the same pattern to find the
ratio between their parent rate and their rate.
For these reason each clock is a composite clock and the operations they
use are different depending of the clock.
According to the datasheet it would be possible to select the parent
clock and the ratio, however currently the driver does not support it.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
