Add vcc_mmc1 fixed regulator to remove the 'no vmmc regulator found' warning
when probing the mmc1 device.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add fixed regulator for vmmc0 and attach the vmmc for it to the mmc0
node on the SAM5D3 Xplained board. This will remove the following
warning from the kernel:
atmel_mci f0000000.mmc: No vmmc regulator found
Note, atmel_defconfig will need fixed regulator support enabled if this
is to be used properly.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[use a fixed regulator instead of gpio one]
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The SAM5D3 Xplained device tree is missing the vqmmc node which is
tied to 3.3V on the board. Add this to avoid the kernel warning that
there is no vqmmc node.
atmel_mci f0000000.mmc: No vqmmc regulator found
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The mmc1 channel is not populated on the SAM5D3 Xplained board, however
it is enabled and therefore the driver is attaching to it.
The node configuration for mmc1 is missing, so add an mmc1 node in the
device tree and set its status to disabled. Also add the vmmc and the
necessary slot configuration if this node were enabled to avoid the following
warnings from the driver:
atmel_mci f8000000.mmc: No vmmc regulator found
atmel_mci f8000000.mmc: No vqmmc regulator found
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
commit 111573ccd8 ("mtd: atmel_nand: check NFC busy flag by HSMC_SR
instead of NFC cmd regs")
check NFC busy by nfc SR instead of NFC cmd regs. So we don't need to
map NFC cmd registers to include NFCBUSY bit.
That means we only need map 0x08000000 instead of 0x10000000 for NFC
cmd regs.
This patch reduce the NFC cmd regs map for sama5d3 & sama5d4.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Update the pinctrl ranges property to support pioD controller whose
mapping is not contiguous with other pio controllers. Without this
update, getting resource will fail, then pinctrl probe will fail too
because there is a missing pio controller.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The Ux500 SOCs have a special backup RAM that needs to be
defined in the device tree.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This documents the device tree bindings on the top level of
the Ux500 boards.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds device tree bindings for the ARM Cortex-A5 and
Cortex-A9 Snoop Control Units.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Now that the rework to have one sub-node per device in the chip and
system controllers is done, their dedicated compatible can be removed.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Berlin clock documentation was part of the Marvell Berlin SoC
documentation because the Berlin clock configuration was inside the
chip controller. With the recent rework of the chip and system
controller handling (now all sub-devices of the soc and system
controller nodes are registred with simple-mfd, and each device has its
own sub-node), the documentation of the Berlin clock driver can be moved
to the generic clock documentation directory.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Berlin pinctrl documentation was part of the Marvell Berlin SoC
documentation because the Berlin pinctrl configuration was inside the
chip and the system controllers. With the recent rework of the chip and
system controller handling (now an MFD driver registers all sub-devices
of the two soc and system controller nodes and each device has its own
sub-node), the documentation of the Berlin pinctrl driver can be moved
to the generic pinctrl documentation directory.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Berlin reset documentation was part of the Marvell Berlin SoC
documentation because the Berlin reset configuration was inside the chip
controller. With the recent rework of the chip and system controller
handling (now an MFD driver registers all sub-devices of the two soc and
system controller nodes and each device has its own sub-node), the
documentation of the Berlin reset driver can be moved to the generic
reset documentation directory.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
We're moving from a single node for multiple devices to a node with one
sub-node per sub-device, registered by simple-mfd. Update the
documentation to reflect the changes.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Because the support of Marvell Berlin SoCs is still a work in progress,
add a statement to explicitly consider our device tree files and
bindings as unstable.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The current GPLv2 only licensing on this dts makes it very impractical
for other software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense
this dts under a GPLv2/X11 dual-license.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The current GPLv2 only licensing on this dtsi makes it very impractical
for other software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense
this dtsi under a GPLv2/X11 dual-license.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The current GPLv2 only licensing on this dts makes it very impractical
for other software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense
this dts under a GPLv2/X11 dual-license.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The current GPLv2 only licensing on this dtsi makes it very impractical
for other software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense
this dtsi under a GPLv2/X11 dual-license.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The current GPLv2 only licensing on this dts makes it very impractical
for other software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense
this dts under a GPLv2/X11 dual-license.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The current GPLv2 only licensing on this dtsi makes it very impractical
for other software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense
this dtsi under a GPLv2/X11 dual-license.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Add basic support for Hitex LPC4350 Evaluation Board. Board
features a LPC4350 Soc, 8 MB SDRAM, 8 MB SPI Flash, USB and
Ethernet.
More information can be found on:
http://www.hitex.com/index.php?id=3212
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@gmail.com>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Adds basic support for Embedded Artists' LPC4357 Developer's Kit. Board
features a LPC4357 Soc, 32 MB SDRAM, 128 MB NAND Flash, 16 MB SPI
Flash, USB and Ethernet.
More information can be found on:
http://www.embeddedartists.com/products/kits/lpc4357_kit.php
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
NXP LPC18xx/43xx SoCs are very similar devices and should be able to
share a common base (lpc18xx.dtsi). Diffences between the devices are
put in a dtsi which is specific to that device.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A series adding support for the Compulab CM-A510
- Add alias for mdio on Armada 38x
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlVV6S0ACgkQCwYYjhRyO9W1tQCghag9/kiZ0qMJSesLBLwG7tcE
yrcAniOoTLzP6cMF+jqtuTrXwoke13JN
=OfeD
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.2' of git://git.infradead.org/linux-mvebu into next/dt
Merge "mvebu dt changes for v4.2 (part #1)" from Gregory CLEMENT:
- A series adding support for the Compulab CM-A510
- Add alias for mdio on Armada 38x
* tag 'mvebu-dt-4.2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add alias for mdio on Armada 38x
ARM: dts: dove: Add Compulab SBC-A510 to Makefile
ARM: dts: dove: Add proper support for Compulab CM-A510/SBC-A510
ARM: dts: dove: Remove Compulab CM-A510 from Makefile
ARM: dts: dove: Add internal i2c multiplexer node
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVVGaiAAoJEFGvii+H/Hdh+EgP/3TFK863t7j9r4UdN76dPogx
GUvaT0U1H6/zs3P9B0/L4FVVdkIhEXZ7NvkiEjGuMySpSoAAouWclaW40FQUysK4
Pr9A0Qssp0QjjIwBpT/cRWyCmTpP00qbYsDRlKWtDmMu4A134UCUTXY5008+S++2
EqVyP28hpkImAvPEt2jj14kFep/HroxVPvsD7/vWM0SP5BY3zXxHl5wSD/6XzmEa
/jJonhhNWVd+/Vkgu331360vEx6zvC66GhIqFLHlSz7dUI4cw008c4NtxcYjFUVl
0Jv9YXyxD3GC52S1cZ0MGrWaMXC9LBOq4/5THU/rU+7n3rrkIl/Wrj4zvyKy6IUo
E/XRzZ0EBRooSR+z/ptZ1QBZouhWRRi5iN8Ql+AqHhUg9QV03wXtauijpkRgKRnO
+eiPeuMvHnWzfWLrfHamQTgHAJdfD8o0+nBx/0mvy76JidamIsbYoRB1NSixKNEz
lZXeQoKQ7H+2Ojky+QQArBFnxH1z1OAga2lKh1MXaHs6mvNzHL1W1btcg66sIjFV
FJHqJjZgPgbelG+fqvYtegfOQKVAGVMDhnGUUeVA22bTPgHvdaLCCTiaCXdpsNC9
cuM0yykWZL0NcZiGXtWSs/2rA7Fw25TJkZ23i1lye15nNeyFLoEZIE1UbtcxylPt
edoYW47mgIS0Xdoi/wim
=KpAt
-----END PGP SIGNATURE-----
Merge tag 'rpi-dt-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi into next/dt
Merge "RaspberryPi Device Tree changes due for v4.2" from Lee Jones:
* tag 'rpi-dt-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi:
ARM: bcm2835: dt: Use 0x4 prefix for DMA bus addresses to SDRAM.
ARM: bcm2835: dt: Add the mailbox to the device tree
ARM: bcm2835: dt: Fix i2c0 node name
ARM: bcm2835: dt: Use pinctrl header
ARM: bcm2835: dt: Add header file for pinctrl constants
ARM: bcm2835: dt: Add root properties for Raspberry Pi
ARM: bcm2835: dt: Add vendor prefix for Raspberry Pi
The Ux500 like other Cortex-A9 SoC's has a Snoop Control
Unit (SCU) and a Watchdog in the same address range as
the local timers. Add these to the SoC device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Enable DMA for HSUSB on r8a7790 and r8a7791 SoCs
* Configure the HOME key as wake-up source on kzm9g board
* Use generic names for device nodes on SH Mobile SoCs and boards
* Add "nor-jedec" compatible value to SH Mobile boards
* Add IRQC clock to r8a73a4, r8a779* SoCs
* Remove MSIOF address from r8a7790 and r8a7791 SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVU/RhAAoJENfPZGlqN0++yMMP/1gRmFjcDdkM9uZclxU7MAo2
eMAQPn1a/ziWIck5cLrCQhk+xZg5FqFhTrzq0oRVa3p6Dq7HOLki3eugp30OjQ/F
c8J2QeYRHDwpVNvSfu/h4YEiKIVURKYFQTn9bSx6B4AefD70+vkRNyZLfDFP/oO/
w/NwkNcyDCHGSlltUddTAggf+XNwWd2S/+KEqFpdeFXUWR/7X3GTzwqji2iyG8Ft
tAJOe6xveAv0WyXCVXs7sf6/LXyyfpzI5jQpmIN3tv4yuUbmIhiihSW1zEFKggQl
+Wa9YQhixdYBRQEDLkCP2qGxwg4q+/58/RHvN3S0eQUrf3/dsnjIdnoLxuEMBpIi
xKqtnO02FNzjcc7XNitaE5hzdNLikVCg8zs48yo4nvBYaWOnsUFXQ5jgkhl/eiqa
q3FsFrk44/1QnHoHmICasfwxJ1TOv5R/FpDxJrBUAFtTfPkRGl/hgpUi0g9d1CNk
XAw/+gUfyJZTHz9la7okwFYb83lHSGHwH3maaRHJ7WCN/T7hGd6BQNZgj3vGkCVq
A9p1t97Pu1+3Yd2IjaRItSlTUW0nvy+uZY58aXluBhM3WKR6ZkaiQC/GWy1Z8fAH
49K1fKR32cu0+zBrD9exaW/Xsc8YKb71C3F/nCwsLOlkLpqJ3Bm2Ys4pe8jHsOJ5
pmSWiLDmIFkccDY2qA6t
=OdRc
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-for-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC DT Updates for v4.2" from Simon Horman:
* Enable DMA for HSUSB on r8a7790 and r8a7791 SoCs
* Configure the HOME key as wake-up source on kzm9g board
* Use generic names for device nodes on SH Mobile SoCs and boards
* Add "nor-jedec" compatible value to SH Mobile boards
* Add IRQC clock to r8a73a4, r8a779* SoCs
* Remove MSIOF address from r8a7790 and r8a7791 SoCs
* tag 'renesas-dt-for-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits)
ARM: shmobile: r8a7791: Enable DMA for HSUSB
ARM: shmobile: r8a7791: add USB-DMAC device nodes
ARM: shmobile: r8a7790: Enable DMA for HSUSB
ARM: shmobile: r8a7790: add USB-DMAC device nodes
ARM: shmobile: kzm9g dts: Configure the HOME key as wake-up source
ARM: shmobile: koelsch dts: Use generic names for device nodes
ARM: shmobile: lager dts: Use generic names for device nodes
ARM: shmobile: bockw dts: Use generic names for device nodes
ARM: shmobile: koelsch dts: Add "nor-jedec" compatible value
ARM: shmobile: bockw dts: Add "nor-jedec" compatible value
ARM: shmobile: lager dts: Add "nor-jedec" compatible value
ARM: shmobile: bockw-reference dts: Add "nor-jedec" compatible value
ARM: shmobile: henninger dts: Add "nor-jedec" compatible value
ARM: shmobile: armadillo800eva dts: Use generic names for device nodes
ARM: shmobile: marzen dts: Use generic names for device nodes
ARM: shmobile: kzm9d dts: Use generic names for device nodes
ARM: shmobile: ape6evm dts: Use generic names for device nodes
ARM: shmobile: sh73a0 dtsi: Use generic names for device nodes
ARM: shmobile: r8a7791 dtsi: Use generic names for device nodes
ARM: shmobile: r8a7790 dtsi: Use generic names for device nodes
...
- clocks descriptions (pxa27x, pxa3xx)
- timer descriptions (pxa27x, pxa3xx)
- IPs which are embedded on the SoC
- keypad
- udc (USB client)
- power I2C
These are amongst the building blocks for future pxa device-tree board
description.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVUm1JAAoJEAP2et0duMsSxJUQAIXpLJWnPYKPj24AQYwQki4T
PlhDxYUPSOFJy2JVBnk+wwuPH+7qFwwZ+6q/y/7l6O5U4okHzoQCL/CySCBHJiFJ
poLFqPfbZn+6WSR9px47v4nDniaoOsBLwb/Z/B7AOC9FgqNBX9lwpkCQeb5ybRk2
vfqUZjbyq5/bxhPSCKh29wclqrO88xaowK9fClXFhgUNjmL/5YEBi3qYKErtGZyi
udAh2rnljIWzgzTfpIs/ovtjgPV8Qy7s0iw0YJLcak3Pl9lmyUA/iQLgK21RfX7J
nQr3AFHkmKs+r496TYrbA5+PLd00LSBs6FIFRHJBvqSEiecqm/hYzY/T+g8KAziG
p7bG9B7DCpM8wvScqGnzaLI0g0wYZVm7XGeSjMnFxQON1Zyk2tg/e7fXSTt/B7/W
mOgmU9bb981zfS6yocrXZaeq48ApnO7dVoWN9orwIOfjSaQA1N4eNeD9VwVNQIxT
sPlmrH4+DH5Ov/coQtGS467W2+leJTtAEYv4SHqqXIj74Je9tiEc9UVVeJhJauxd
LMfPkl4/P9WaBVFqICAGbBE+F597hOIG9CPec0gKVg8c4wq3Ji2fHEy+wZXBSSuC
t06d5yt082ffrPY0qqZSGal7vUUzDMav+HUmGU/34QpQbUE6rr7sflOPpSLIK1Qe
sURcpwaKhGmNqhnOBxm3
=GbmD
-----END PGP SIGNATURE-----
Merge tag 'pxa-dt-4.2' of https://github.com/rjarzmik/linux into next/dt
Merge "device-tree pxa update" from Robert Jarzmik:
- clocks descriptions (pxa27x, pxa3xx)
- timer descriptions (pxa27x, pxa3xx)
- IPs which are embedded on the SoC
- keypad
- udc (USB client)
- power I2C
These are amongst the building blocks for future pxa device-tree board
description.
* tag 'pxa-dt-4.2' of https://github.com/rjarzmik/linux:
ARM: dts: pxa: add pxa-timer to pxa27x and pxa3xx
ARM: dts: pxa: add pxa27x-keypad to pxa27x
ARM: dts: pxa: add pxa27x-udc to pxa27x
ARM: dts: pxa: add clocks
ARM: dts: pxa: add pwri2c to pxa device-tree
Merge "Device Tree changes" from Florian Fainelli:
New devices:
- Felix adds support for the Buffalo WXR-1900DHP and adds the USB led on Buffalo
WZR-1750DHP
- Rafal adds support for the SmartRG SR400ac, Asus RT-AC68U and RT-AC56U
New peripheral support:
- Brian adds Device Tree nodes for the Broadcom NAND controller found on
BCM7xxx, BCM63138 and Cygnus SoCs
- Brian adds Device Tree nodes for the SATA AHCI and PHY controller found on
BCM7xxx
- I add the Device Tree nodes and bindings documents for bringing-up secondary
CPUs and timer/syscon-reboot on BCM63138
* tag 'arm-soc/for-4.2/dts' of http://github.com/broadcom/stblinux:
ARM: BCM5301X: Add DT for Asus RT-AC56U
ARM: BCM5301X: Add DT for Asus RT-AC68U
ARM: dts: BCM63xx: Add timer and syscon-reboot nodes
dt-bindings: Add documentation for the BCM63138 timer and syscon-reboot
ARM: dts: brcmstb: add nodes for SATA controller and PHY
ARM: dts: cygnus: Enable NAND support for Cygnus
ARM: bcm63138: add NAND DT support
ARM: bcm7445: add NAND to DTS
ARM: BCM5301X: Add DT for SmartRG SR400ac
ARM: BCM5301X: Add DT for Buffalo WXR-1900DHP
ARM: BCM5301X: Add USB LED for Buffalo WZR-1750DHP
ARM: dts: BCM63xx: Add SMP nodes and required properties
Documentation: DT: Document SMP DT nodes and properties for BCM63138
ARM: dts: BCM63xx: Add PMB busses nodes
Documentation: DT: Add Broadcom BCM63138 PMB binding
GPLv2-only devicetrees make reuse difficult for software components licensed
under a different license.
The consensus is that a GPL/X11 dual-license should allow all necessary uses,
so relicense the rk3288-evb files to this combination.
CCs were aquired by git shortlog -sne so it should've hopefully catched
every contributor.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Doug Anderson <dianders@chromium.org>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Caesar Wang <caesar.wang@rock-chips.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Chris Zhong<zyw@rock-chips.com>
Acked-by: Roger Chen <roger.chen@rock-chips.com>
Acked-by: Yunzhi Li <lyz@rock-chips.com>
on behalf of Rockchip
Acked-by: Eddie Cai <eddie.cai@rock-chips.com>
GPLv2-only devicetrees make reuse difficult for software components licensed
under a different license.
The consensus is that a GPL/X11 dual-license should allow all necessary uses,
so relicense the rk3288.dtsi to this combination.
CCs were aquired by git shortlog -sne so it should've hopefully catched
every contributor.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Doug Anderson <dianders@chromium.org>
Acked-by: Sonny Rao <sonnyrao@chromium.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Caesar Wang <caesar.wang@rock-chips.com>
Acked-by: Lin Huang <hl@rock-chips.com>
Acked-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Jianqun Xu<jay.xu@rock-chips.com>
Acked-by: Daniel Kurtz <djkurtz@chromium.org>
Acked-by: Roger Chen <roger.chen@rock-chips.com>
Acked-by: Yunzhi Li <lyz@rock-chips.com>
on behalf of Rockchip
Acked-by: Eddie Cai <eddie.cai@rock-chips.com>
This patch fixes a regression where serial is enabled by the first
(board) DTSI, then disabled by the second (SoC) file. To enable
serial and keep it enabled, we need to include the file which enables
it last.
Reported-by: LAVA [via Peter Griffin <peter.griffin@linaro.org>]
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top
2 bits. The bits in the bus address mean:
From the VideoCore processor:
0x0... L1 and L2 cache allocating and coherent
0x4... L1 non-allocating, but coherent. L2 allocating and coherent
0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent
0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent
From the GPU peripherals (note: all peripherals bypass the L1
cache. The ARM will see this view once through the VC MMU):
0x0... Do not use
0x4... L1 non-allocating, and incoherent. L2 allocating and coherent.
0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent
0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent
The 2835 firmware always configures the MMU to turn ARM physical
addresses with 0x0 top bits to 0x4, meaning present in L2 but
incoherent with L1. However, any bus addresses we were generating in
the kernel to be passed to a device had 0x0 bits. That would be a
reserved (possibly totally incoherent) value if sent to a GPU
peripheral like USB, or L1 allocating if sent to the VC (like a
firmware property request). By setting dma-ranges, all of the devices
below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and
friends return addresses with 0x4 bits and avoid cache incoherency.
This matches the behavior in the downstream 2708 kernel (see
BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h).
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Device tree node names should contain the node's reg property address value.
The i2c0 node was apparently forgotten in commit 25b2f1bd0b (ARM: bcm2835:
node name unit address cleanup).
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This patch converts all bcm2835 dts and dtsi files to use the pinctrl
header file.
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This new header file defines pincontrol constants to use
from bcm2835 DTS files for pincontrol properties option.
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This patch adds root compatible properties for the following boards:
- Raspberry Pi Model A
- Raspberry Pi Model A+
- Raspberry Pi Model B
- Raspberry Pi Model B (no P5)
- Raspberry Pi Model B rev2
- Raspberry Pi Model B+
- Raspberry Pi Compute Module
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Since the prefix is already in use, we need to add it in the
vendor list.
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
GPLv2-only devicetrees make reuse difficult for software components licensed
under a different license.
The consensus is that a GPL/X11 dual-license should allow all necessary uses,
so relicense the rk3188-radxarock.dts to this combination.
CCs were aquired by git shortlog -sne so it should've hopefully catched
every contributor.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Julien Chauveau <chauveau.julien@gmail.com>
GPLv2-only devicetrees make reuse difficult for software components licensed
under a different license.
The consensus is that a GPL/X11 dual-license should allow all necessary uses,
so relicense the rk3066a-bqcurie2.dts to this combination.
CCs were aquired by git shortlog -sne so it should've hopefully catched
every contributor.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
