A 64-bit BAR consists of a BAR pair, where the second BAR has the
upper bits, so we cannot simply call pci_ioremap_bar() on every single
BAR index.
The second BAR in a BAR pair will not have the IORESOURCE_MEM resource
flag set. Only call ioremap on BARs that have the IORESOURCE_MEM
resource flag set.
pci 0000:01:00.0: BAR 4: assigned [mem 0xc0300000-0xc031ffff 64bit]
pci 0000:01:00.0: BAR 2: assigned [mem 0xc0320000-0xc03203ff 64bit]
pci 0000:01:00.0: BAR 0: assigned [mem 0xc0320400-0xc03204ff 64bit]
pci-endpoint-test 0000:01:00.0: can't ioremap BAR 1: [??? 0x00000000 flags 0x0]
pci-endpoint-test 0000:01:00.0: failed to read BAR1
pci-endpoint-test 0000:01:00.0: can't ioremap BAR 3: [??? 0x00000000 flags 0x0]
pci-endpoint-test 0000:01:00.0: failed to read BAR3
pci-endpoint-test 0000:01:00.0: can't ioremap BAR 5: [??? 0x00000000 flags 0x0]
pci-endpoint-test 0000:01:00.0: failed to read BAR5
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
pci_disable_msi() throws a Kernel BUG if the driver has successfully
requested an IRQ and not released it. Fix it here by freeing IRQs before
invoking pci_disable_msi().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) in
pci_endpoint_test_remove() returns 0, which results in returning early
without releasing the resources. This is as a result of misc_device not
having a valid name. Fix it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Return value of pci_endpoint_test_probe is not set properly in a couple of
failure cases. Fix it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
If you call ida_simple_remove(&pci_endpoint_test_ida, id) with a negative
"id" then it triggers an immediate BUG_ON(). Let's not allow that.
Fixes: 2c156ac71c ("misc: Add host side PCI driver for PCI test function device")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
"size + max" can have an arithmetic overflow when we're allocating:
orig_src_addr = dma_alloc_coherent(dev, size + alignment, ...
Add a few checks to prevent that.
Fixes: 13107c6068 ("misc: pci_endpoint_test: Add support to provide aligned buffer addresses")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
In certain platforms like TI's DRA7 SoCs, use of legacy PCI interrupt is
exclusive with use of MSI (Section 24.9.4.6.2.1 Legacy PCI Interrupts in
http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf).
However pci_endpoint_test driver enables MSI by default in probe. In order
for pci_endpoint_test to be able to test legacy interrupt, MSI should be
disabled. Add a module param 'no_msi' to disable MSI (only when legacy
interrupt has to be tested).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[bhelgaas: folded in static fix from Colin Ian King <colin.king@canonical.com>]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
BAR sizes are hard-coded in pci_endpoint_test driver corresponding to the
sizes used in pci-epf-test function driver. This might break if the sizes
in pci-epf-test function driver are modified (and the corresponding change
is not done in pci_endpoint_test PCI driver).
To avoid hard coding BAR sizes, use pci_resource_len() API.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Some platforms like TI's K2G have a restriction that the host side buffer
address should be aligned to either 1MB/2MB/4MB or 8MB addresses depending
on how it is configured in the endpoint (Ref: 11.14.4.9.1 Outbound Address
Translation in K2G TRM SPRUHY8F January 2016 – Revised May 2017). This
restriction also applies to the MSI addresses provided by the RC. However
it's not possible for the RC to know about this restriction and it may not
provide 1MB/2MB/4MB or 8MB aligned address. So MSI interrupts should be
disabled even if the K2G EP has MSI capabiltiy register.
Add support to not enable MSI interrupts in pci_endpoint_test driver so
that it can be used to test K2G EP.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Some platforms like TI's K2G have a restriction that the host side buffer
address should be aligned to either 1MB/2MB/4MB or 8MB (Ref: 11.14.4.9.1
Outbound Address Translation in K2G TRM SPRUHY8F January 2016 – Revised May
2017) addresses depending on how it is configured in the endpoint.
Add support to provide such aligned address here so that pci_endpoint_test
driver can be used to test K2G EP.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
pci_endpoint_test driver assumes the PCI_ENDPOINT_TEST registers will
always be mapped to BAR_0. This need not always be the case like in TI's
K2G where BAR_0 is mapped to PCI controller application registers.
Add support so that PCI_ENDPOINT_TEST registers can be mapped to any BAR.
Change the bar_size used for BAR test accordingly.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Add PCI endpoint test driver that can verify base address register, legacy
interrupt/MSI interrupt and read/write/copy buffers between host and
device. The corresponding pci-epf-test function driver should be used on
the EP side.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
