Commit Graph

3775 Commits

Author SHA1 Message Date
Icenowy Zheng
37cabc74e5 clk: sunxi-ng: fix PRCM CCU ir clk parent
The first parent of ir clk in PRCM CCU is wrongly written as "osc32K"
instead of "osc32k".

Change it to "osc32k".

Fixes: cdb8b80b60 ("clk: sunxi-ng: add support for PRCM CCUs")

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-10 09:04:23 +02:00
Priit Laes
cb545960de clk: sunxi-ng: Display index when clock registration fails
Add clock index to clock registration failure message. Clock name
is sometimes not available, when things go really wrong.

Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-06 09:10:30 +02:00
Chen-Yu Tsai
68f37d8624 clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
The DDR1 PLL on the A33 is an oddball amongst the A33 CCU clocks.
It is a clock multiplier, with the effective multiplier in the
range of 12 ~ 255 and no offset between the multiplier value and
the value programmed into the register.

Implement the zero offset and minimum value of 12 for this clock.

Fixes: d05c748bd7 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05 09:03:02 +02:00
Chen-Yu Tsai
25eb035c3f clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
The CPU cluster PLLs on the A80 are NP clocks that are atypical in two ways:

  - The P factor is 1 bit wide, and translates to a /1 or /4 divider.

  - The P factor should only be used for output frequencies lower than
    288 MHz. The N factor has a lower limit of 12, which likely contributed
    to this extra divider.

According to the user manual, the clocks can only go as low as 200 MHz.
The vendor BSP kernel does not even define operating points below 360
MHz for these clocks. The lower end for cpufreq in the vendor kernel is
even higher. The mainline Linux kernel doesn't support cpufreq for the
A80 at the moment. This means the lower frequencies are untested, and
will likely remain unused.

The new sunxi-ng style clocks don't support the quirks listed above.
Instead of trying to work the quirks in for something of little usage,
we re-model the clocks into N-type multipler clocks, with P fixed at 1.
At probe time we check if P is set to 4, and fix it up if needed. This
is highly unlikely though.

Fixes: b8eb71dcdd ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05 09:02:56 +02:00
Chen-Yu Tsai
cf719012b2 clk: sunxi-ng: mult: Support PLL lock detection
Some PLL clocks are N (multiplier) type clocks, or can be simplified
as such. An example of the former is the DDR1 PLL clock on the A33.
An example of the latter is the CPU PLL clock on the A80, in which
the P divider is only used for low frequencies that are of little
use. Both clocks support PLL lock detection.

The mult clock macro implies support for this, but that is not true.
The field is simply discarded. This patch adds proper support for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05 09:01:41 +02:00
Icenowy Zheng
cdb8b80b60 clk: sunxi-ng: add support for PRCM CCUs
SoCs after A31 has a clock controller module in the PRCM part.

Support the clock controller module on H3/5 and A64 now.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04 17:43:52 +02:00
Priit Laes
b0f0daa8fe clk: sunxi-ng: sun5i: Fix mux width for csi clock
Mux for CSI clock is 3 bits, not 2.

Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06 10:25:56 +01:00
Peter Robinson
05c04bef44 clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
Tighten the depends on the various AllWinn SoCs so we don't
inadvertantly get clock drivers when we're not wanting them
like 32 bit SoC clocks for 64 bit configs. Ensure there's
still test coverage though.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06 10:25:56 +01:00
Icenowy Zheng
9be1c8afb4 clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
Allwinner H5 is a SoC that features a design which keeps the peripheral
compatible with H3, so that it have also a CCU like the one on H3 --
only one bus gate/reset is added, and the mmc sample/output phases are
removed because of MMC controller update.

Add its support in our existing H3 CCU driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06 10:25:56 +01:00
Chen-Yu Tsai
845d6b0ff9 clk: sunxi-ng: gate: Support common pre-dividers
Some clock gates have a pre-divider between the source input and the
gate itself. A notable example is the HSIC 12 MHz clock found on the
A83T, which has the 24 MHz main oscillator as its input, and a /2
pre-divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06 10:25:56 +01:00
Chen-Yu Tsai
9ad0bb39fc clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock
The enable bit offset for the hdmi-ddc module clock is wrong. It is
pointing to the main hdmi module clock enable bit.

Reported-by: Bob Ham <rah@settrans.net>
Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Cc: stable@vger.kernel.org # 4.9.x-
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06 07:36:04 +01:00
Arnd Bergmann
69c9ae5041 clk: sunxi: ccu-sun5i needs nkmp
A randconfig build ran into this rare link error:

drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_nkmp_ops'
drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.7+0x4): undefined reference to `ccu_nkmp_ops'

This adds the missing 'select'.

Fixes: 5e73761786 ("clk: sunxi-ng: Add sun5i CCU driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06 07:36:04 +01:00
Chen-Yu Tsai
ac8616e4c8 clk: sunxi-ng: mp: Adjust parent rate for pre-dividers
The MP style clocks support an mux with pre-dividers. While the driver
correctly accounted for them in the .determine_rate callback, it did
not in the .recalc_rate and .set_rate callbacks.

This means when calculating the factors in the .set_rate callback, they
would be off by a factor of the active pre-divider. Same goes for
reading back the clock rate after it is set.

Cc: stable@vger.kernel.org
Fixes: 2ab836db50 ("clk: sunxi-ng: Add M-P factor clock support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06 07:36:04 +01:00
Linus Torvalds
a1a0db36d8 ARM: SoC: late DT updates for v4.11
These updates have been kept in a separate branch mostly because
 they rely on updates to the respective clk drivers to keep the
 shared header files in sync.
 
 This includes two branches for arm64 dt updates, both following up
 on earlier changes for the same platforms that are already merged:
 
 Samsung:
   - add USB3 support in Exynos7
   - minor PM related updates
 
 Amlogic:
   - new machines: WeTek Set-top-boxes
   - various devices added to DT
 
 There are also a couple of bugfixes that trickled in since the
 start of the merge window:
 
 - The moxart_defconfig was not building the intended platform
 - CPU-hotplug was broken on ux500
 - Coresight was broken on Juno (never worked)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIVAwUAWLmRS2CrR//JCVInAQKrkQ//bd8TCGXA0tRwDMEGejtWChZcNkGZDaer
 sNMyE/c1p5+/4euSmf3jW1JsIx4JDtjr0psKeRpgYId8GVdvaYceFbSMJl6o9hDc
 pm3sqb66xEgrWQoSBA2Urz/RhSIrxkYbuTpYbN4teV9I/IFgTUggaBSzfkq3SLRE
 bEVSbCw0S/6t3vJgW4CKCI75+a3NexqImvi8txNwueQQMnDLnOkG97vMUQJgDq0j
 E+CeOk0mvlGF+TiVoAhUxT3YIt8azUTfUVw7CBIRvo/49sUCiETk6xie93FaC7GI
 Tmg9KK+oZhrmqt8PBGkikxQMHATnKrfJbMNi/K6nrxW91ylSkwTN/7jfhSjFDrdI
 4WNB2x3u6KUnQ0XOKVY36gUnV8kJ/2K9pTZpq0K7m4czo8YAid9LumvDnqhPI0Xg
 fXxq3YBx7AfzsdBL3+nQ7AH3tr9Bvt01kMZwYwNgpqtglEBScAgzyrPG/yyTBFq7
 KOkoyNojTaHZHcDtYqSaxYls+2tdeyvYuQJ7QGQ5DJCW99NgbRuFfIUJvgwRPoKt
 13ioIJxDUHmemR6xFURWVH1dPkkqwtJht7us5jcxuxBL9ZhmEb6vophvyxj62zTZ
 8A+PE3cC1azhKph7rVrUl9KEoYZzedwDaTGBNpYz1gN7DxDvWHYINEPB4bBLzYmv
 uWsSYVbV2Qs=
 =A3U6
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late DT updates from Arnd Bergmann:
 "These updates have been kept in a separate branch mostly because they
  rely on updates to the respective clk drivers to keep the shared
  header files in sync.

  This includes two branches for arm64 dt updates, both following up on
  earlier changes for the same platforms that are already merged:

  Samsung:
   - add USB3 support in Exynos7
   - minor PM related updates

  Amlogic:
   - new machines: WeTek Set-top-boxes
   - various devices added to DT

  There are also a couple of bugfixes that trickled in since the start
  of the merge window:

   - The moxart_defconfig was not building the intended platform
   - CPU-hotplug was broken on ux500
   - Coresight was broken on Juno (never worked)"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
  ARM: deconfig: fix the moxart defconfig
  ARM: ux500: resume the second core properly
  arm64: dts: juno: update definition for programmable replicator
  arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
  arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
  arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
  pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
  arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
  ARM64: dts: meson-gxbb-p200: add ADC laddered keys
  ARM64: dts: meson: meson-gx: add the SAR ADC
  ARM64: dts: meson-gxl: add the pwm_ao_b pin
  ARM64: dts: meson-gx: add the missing pwm_AO_ab node
  clk: gxbb: fix CLKID_ETH defined twice
  ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
  clk: gxbb: add the SAR ADC clocks and expose them
  dt-bindings: amlogic: Add WeTek boards
  ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
  dt-bindings: vendor-prefix: Add wetek vendor prefix
  ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
  ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
  ...
2017-03-03 16:15:48 -08:00
Arnd Bergmann
d4b80d9aac Merge branch 'next/late' with mainline
* next/late: (25 commits)
  arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
  arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
  arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
  pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
  arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
  ARM64: dts: meson-gxbb-p200: add ADC laddered keys
  ARM64: dts: meson: meson-gx: add the SAR ADC
  ARM64: dts: meson-gxl: add the pwm_ao_b pin
  ARM64: dts: meson-gx: add the missing pwm_AO_ab node
  clk: gxbb: fix CLKID_ETH defined twice
  clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
  clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
  ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
  clk: gxbb: add the SAR ADC clocks and expose them
  dt-bindings: amlogic: Add WeTek boards
  ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
  dt-bindings: vendor-prefix: Add wetek vendor prefix
  ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
  ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
  ARM64: dts: meson-gxbb-vega-s95: Add LED
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-03-02 17:52:44 +01:00
Linus Torvalds
5d8a00eee2 The usual collection of new drivers, non-critical fixes, and updates
to existing clk drivers. The bulk of the work is on Allwinner and
 Rockchip SoCs, but there's also an Intel Atom driver in here too.
 
 New Drivers:
  - Tegra BPMP firmware
  - Hisilicon hi3660 SoCs
  - Rockchip rk3328 SoCs
  - Intel Atom PMC
  - STM32F746
  - IDT VersaClock 5P49V5923 and 5P49V5933
  - Marvell mv98dx3236 SoCs
  - Allwinner V3s SoCs
 
 Removed Drivers:
  - Samsung Exynos4415 SoCs
 
 Updates:
  - Migrate ABx500 to OF
  - Qualcomm IPQ4019 CPU clks and general PLL support
  - Qualcomm MSM8974 RPM
  - Rockchip non-critical fixes and clk id additions
  - Samsung Exynos4412 CPUs
  - Socionext UniPhier NAND and eMMC support
  - ZTE zx296718 i2s and other audio clks
  - Renesas CAN and MSIOF clks for R-Car M3-W
  - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1
  - TI CDCE913, CDCE937, and CDCE949 clk generators
  - Marvell Armada ap806 CPU frequencies
  - STM32F4* I2S/SAI support
  - Broadcom BCM2835 DSI support
  - Allwinner sun5i and A80 conversion to new style clk bindings
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQIcBAABCAAGBQJYsLxxAAoJEK0CiJfG5JUl0p0P/AiBaYvrmHBx3H9jdC3iQxd2
 7luFN3OqpykmZc3xx2xO3WaZ96kwwxiMu8sj3+VQo6oCkEuOY2ru6uPiDOcF4P3+
 8ku2taoWlESDbVLebVTNJoRXBaBLaV+9BCN7AKvXpVw+/UkJI5hgr0yMdh4tgtvu
 K08tTMkDNDbA33KXuJo8/chQFqi2W6XBXk22YMkqqA8jx0F4EM759LcgUlD1YfBS
 HKkgSOgsW3Zwhl27ZEAJMthcmS4+wFaEgFBeipg/hxTLI3aQtmDtRfXwg0wkbBx2
 8sVz9SyBwkjOT9+41kve+Je94NK3blnJEjbxPASveMwyhdX1TlDQCPfrXya/1zxz
 N1By1NpA6iEYwi4hy+OtBYlcsBHztAM/+eljDY2kEDvfiKjMa44GYmgBu4n8pq+n
 75NJxws6ZkzPs5/QsLT3hvTaL1SNX6PaEW8HabDXO40ccZc4CYvFZVOXMAnKaXzZ
 31hj8EvQ5x6hci+SPYyVu6j3ipOxN96VcZqEJ+hWyyuZEMK6Up1o/0lGZFgwa0UD
 SIl7RiTFKO6ko+8hYlk1g0DGtEyWDsdso1Bw4zaHwMngM/CwjJVzpK5T2t1fJyEh
 lN5MdhcOi0nsiRWdRxOwOlHDLf93qSo87mvseU1MCEXYN1aqTV3VxSm1YU8ZgQVk
 sAjpsJqj45enfDa9BmIt
 =o8o/
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The usual collection of new drivers, non-critical fixes, and updates
  to existing clk drivers. The bulk of the work is on Allwinner and
  Rockchip SoCs, but there's also an Intel Atom driver in here too.

  New Drivers:
   - Tegra BPMP firmware
   - Hisilicon hi3660 SoCs
   - Rockchip rk3328 SoCs
   - Intel Atom PMC
   - STM32F746
   - IDT VersaClock 5P49V5923 and 5P49V5933
   - Marvell mv98dx3236 SoCs
   - Allwinner V3s SoCs

  Removed Drivers:
   - Samsung Exynos4415 SoCs

  Updates:
   - Migrate ABx500 to OF
   - Qualcomm IPQ4019 CPU clks and general PLL support
   - Qualcomm MSM8974 RPM
   - Rockchip non-critical fixes and clk id additions
   - Samsung Exynos4412 CPUs
   - Socionext UniPhier NAND and eMMC support
   - ZTE zx296718 i2s and other audio clks
   - Renesas CAN and MSIOF clks for R-Car M3-W
   - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1
   - TI CDCE913, CDCE937, and CDCE949 clk generators
   - Marvell Armada ap806 CPU frequencies
   - STM32F4* I2S/SAI support
   - Broadcom BCM2835 DSI support
   - Allwinner sun5i and A80 conversion to new style clk bindings"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits)
  clk: renesas: mstp: ensure register writes complete
  clk: qcom: Do not drop device node twice
  clk: mvebu: adjust clock handling for the CP110 system controller
  clk: mvebu: Expand mv98dx3236-core-clock support
  clk: zte: add i2s clocks for zx296718
  clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()
  clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i
  clk: sunxi-ng: Check kzalloc() for errors and cleanup error path
  clk: tegra: Add BPMP clock driver
  clk: uniphier: add eMMC clock for LD11 and LD20 SoCs
  clk: uniphier: add NAND clock for all UniPhier SoCs
  ARM: dts: sun9i: Switch to new clock bindings
  clk: sunxi-ng: Add A80 Display Engine CCU
  clk: sunxi-ng: Add A80 USB CCU
  clk: sunxi-ng: Add A80 CCU
  clk: sunxi-ng: Support separately grouped PLL lock status register
  clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
  clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
  clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
  clk: qcom: SDHCI enablement on Nexus 5X / 6P
  ...
2017-02-25 14:28:06 -08:00
Linus Torvalds
195849ea13 ARM: DT updates for v4.11
A total of 380 patches this time, mostly adding support for more hardware
 in the device tree descriptions. There is not much exciting here for 4.11,
 but I've tried my best to condense the information from the pull requests
 I got into a readable summary.
 
 Noteworthy changes to existing platforms include:
   - The GIC memory map was a bit wrong almost everywhere and now
     gets fixed up
   - The Allwinner platforms convert to the generic pinmux properties
   - The Marvell EBU platforms now use the new DSA binding
   - Samsung Exynos4212 was unused and gets removed
   - The Renesas power management got improved
 
 New production machines:
   - Lego Mindstorms EV3
     https://www.lego.com/en-us/mindstorms/about-ev3
   - Beelink X2 Android media box
     http://linux-sunxi.org/Beelink_X2
   - "Romulus" baseboard management controller for OpenPower
   - Axentia TSE-850 Data Radio Channel (DARC) encoder
     http://www.axentia.se/db/equipment.html
   - Luxul XAP-1410 and XWR-1200 wireless access points
     https://luxul.com/xap-1410
 
 New SoCs:
   - Allwinner H2+ and V3s, both minor variations of already
     supported chips
     http://www.allwinnertech.com/index.php?c=product&a=index&id=38
   - Marvell Prestera DX packet processors based on Armada XP architecture
     http://www.marvell.com/switching/prestera-dx/
   - Samsung Exynos4412 Prime gets added, a minor variation of Exynos4412
 
 New developer and reference boards:
   - Lichee Pi One, Lichee Pi Zero and Orange Pi Zero,
     all based on Allwinner SoCs
     http://linux-sunxi.org/LicheePi_One
     http://www.orangepi.org/orangepizero/
   - SAMA5d36ek Reference platform
     http://www.atmel.com/tools/sama5d36-ek.aspx
   - Beaglebone Green Wireless and Black Wireless
     https://beagleboard.org/black-wireless
     https://beagleboard.org/green-wireless
   - phyCORE-AM335x System on Module
     http://phytec.com/products/system-on-modules/phycore/am335x/
   - New revision of "vf610-zii" Zodiac Inflight Innovations board
   - Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam i.Core
     http://www.opossom.com/english/index.html
     http://www.savageboard.org/
     http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ul
     http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
   - Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is
 
 Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas, qcom,
     rockchip, sti, stm32 and tegra
 
 New device supports added to some boards and SoCs, briefly by platform:
   - Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU
   - Aspeed: network, ipmi bt, gpio, pinmux
   - Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc
   - TI DaVinci: gpio, lcdc, usb, video-in, uart
   - TI Keystone 2: MSM RAM, power/reset, uart
   - Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal
   - Marvell EBU: ethernet switch on Turris Omnia
   - NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic,
     eeprom, mmc, nand
   - TI OMAP:
   - Qualcomm: coresight, gyro/accelerometer, hdmi
   - Renesas: pmic, soc-id
   - Rockchip: qos
   - Samsung: audio on Odroid-X
   - Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor
   - STi: video in/out
   - STM32: timer, pwm, i2c, rtc, add, i2s
   - NVIDIA Tegra: tpm
   - Uniphier: mmc/sd pinmux
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIVAwUAWK9aamCrR//JCVInAQJPpBAA2qUQYRfCgzK1fEu6X+c8pzqITqlV+Hx7
 8tBsZFINywKLnUXLs4Ip4DDK8uDsIACXSmGMdmhUVIXLsuRxJBl8av+ndd+ERGoF
 bg/iAIyA9hjKRhorE1wDyC4wg1S4P8laPevbK7NcDYDbK9MRmGSmEyP2uvhfLtVy
 2zoPfIE5aEipx6GoIATzLRqpMO6rWB/eg9OUZVKN5Hwh3LNCKtkX726GC9WGVqoE
 zslF1S6VH63dfru2Vlu5eFdvmiox54gBJBMR7yld+EIiXWilNT0eWfEYRd3CMT6E
 EwRCNiNRa21DHstBdL9pTuE+K0LpAUXlznjiqeWrZVuJfdHJy51pGVWwoc4ynbhI
 TS/GFgJI4iG2xrE3EIJS5cAl1S9WtNOYYvZATM35blFbZv7ASoAGdj2EECIIPwJr
 CR4l9Y2k/fuNHAzhR4B0fEKj/uWj7ONqcolpf8W6lZx0MvVNgeDwdx0eoLrbrxY9
 MJFb9OgD+BhNp5lIElysl0L9aEp3PxV668nSg4qV+Mo4w/5/OXhHK8675bXlITFU
 4Rw6fxRUBeO2B0LSonE4Ds8QKMQCs2yfxyMPWMn8yK/xFkwpHzwoJuRR2RYpbQTb
 5Hrnfk23k+2rflht07XBxNqqaznDQyPPvAvoB0ZZ2kchPYl75MlpAfOGlgfhXcmm
 Kp4g7VYyfAs=
 =ucQ/
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Arnd Bergmann:
 "A total of 380 patches this time, mostly adding support for more
  hardware in the device tree descriptions. There is not much exciting
  here for 4.11, but I've tried my best to condense the information from
  the pull requests I got into a readable summary.

  Noteworthy changes to existing platforms include:

   - The GIC memory map was a bit wrong almost everywhere and now gets
     fixed up

   - The Allwinner platforms convert to the generic pinmux properties

   - The Marvell EBU platforms now use the new DSA binding

   - Samsung Exynos4212 was unused and gets removed

   - The Renesas power management got improved

  New production machines:

   - Lego Mindstorms EV3:
        https://www.lego.com/en-us/mindstorms/about-ev3

   - Beelink X2 Android media box:
        http://linux-sunxi.org/Beelink_X2

   - "Romulus" baseboard management controller for OpenPower

   - Axentia TSE-850 Data Radio Channel (DARC) encoder:
        http://www.axentia.se/db/equipment.html

   - Luxul XAP-1410 and XWR-1200 wireless access points:
        https://luxul.com/xap-1410

  New SoCs:

   - Allwinner H2+ and V3s, both minor variations of already supported
     chips:
        http://www.allwinnertech.com/index.php?c=product&a=index&id=38

   - Marvell Prestera DX packet processors based on Armada XP
     architecture:
        http://www.marvell.com/switching/prestera-dx/

   - Samsung Exynos4412 Prime gets added, a minor variation of
     Exynos4412

  New developer and reference boards:

   - Lichee Pi One, Lichee Pi Zero and Orange Pi Zero, all based on
     Allwinner SoCs:
        http://linux-sunxi.org/LicheePi_One
        http://www.orangepi.org/orangepizero/

   - SAMA5d36ek Reference platform:
        http://www.atmel.com/tools/sama5d36-ek.aspx

   - Beaglebone Green Wireless and Black Wireless:
        https://beagleboard.org/black-wireless
        https://beagleboard.org/green-wireless

   - phyCORE-AM335x System on Module:
        http://phytec.com/products/system-on-modules/phycore/am335x/

   - New revision of "vf610-zii" Zodiac Inflight Innovations board

   - Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam
     i.Core:
        http://www.opossom.com/english/index.html
        http://www.savageboard.org/
        http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ul
        http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q

   - Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is

   - Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas,
     qcom, rockchip, sti, stm32 and tegra

  New device supports added to some boards and SoCs, briefly by platform:

   - Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU

   - Aspeed: network, ipmi bt, gpio, pinmux

   - Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc

   - TI DaVinci: gpio, lcdc, usb, video-in, uart

   - TI Keystone 2: MSM RAM, power/reset, uart

   - Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal

   - Marvell EBU: ethernet switch on Turris Omnia

   - NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic, eeprom,
     mmc, nand

   - TI OMAP:

   - Qualcomm: coresight, gyro/accelerometer, hdmi

   - Renesas: pmic, soc-id

   - Rockchip: qos

   - Samsung: audio on Odroid-X

   - Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor

   - STi: video in/out

   - STM32: timer, pwm, i2c, rtc, add, i2s

   - NVIDIA Tegra: tpm

   - Uniphier: mmc/sd pinmux"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (380 commits)
  ARM: dts: armada-385-linksys: fix DSA compatible property
  ARM: dts: Fix typo in armada-xp-98dx4251
  ARM: DTS: Fix register map for virt-capable GIC
  dt-bindings: arm,gic: Fix binding example for a virt-capable GIC
  ARM: dts: sun8i: sinlinx: Enable audio nodes
  ARM: dts: sun8i: parrot: Enable audio nodes
  ARM: dts: sun8i: Add audio codec, dai and card for A33
  ARM: dts: Add EMAC AXI settings for Arria10
  ARM: dts: am335x-chiliboard: Support charger
  ARM: dts: am335x-chiliboard: Support power button
  ARM: sun8i: dt: Add mali node
  dt-bindings: gpu: Add Mali Utgard bindings
  ARM: dts: stm32: Add I2C1 support for STM32429 eval board
  ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
  ARM: dts: stm32: Use clock DT binding definition on stm32f429 family
  dt-bindings: mfd: stm32f4: Add missing binding definition
  dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro
  ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
  ARM: dts: stm32: add Timers driver for stm32f429 MCU
  ARM: dts: add the AB8500 sysclk to the device trees
  ...
2017-02-23 15:46:25 -08:00
Chris Brandt
f59de56335 clk: renesas: mstp: ensure register writes complete
When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.

Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-16 10:36:05 -08:00
Arnd Bergmann
3e011039a3 Amlogic DT updates for v4.11, round 2
- add SAR ADC driver
 - add ADC laddered keys to meson-gxbb-p200 board
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABCAAGBQJYlNIUAAoJEFk3GJrT+8Zl6+YP/1U3aOeboRpqQiKucyMEU8bi
 GWxVAfbeIO6n9s9NMqxhBIc9fpx1sVvt8748va8xIJfQun+qrYFPvGJlK45EXfmq
 3sJSf3mu6pMyjB5FZ7m7R69G60Y80TeQ9hDvbAbSvW5c7fM69lBNouXATXK7tyaT
 v00pRNPZZ8yDmcNnxLxKYJ5bMPS9uloHYihROTTjFF+Q2zwg6hn1Zo7j/O8Yn4sw
 DNoorRLBwvI/HpkDeIl4I4T3h7oNqSzBs2h4R9k6kDUP+MkguHSBkysF6QfRnCp8
 MA3W+j5Rxk0neKNkXJlDry3cApwsmOjm47H68PSa2ODGo1BQhw+RtcZkdMinH7UU
 Lq0j/12oft1UHW+WcB5+x4d+gaVLAtNbNFIQLa/lgo/uX/6nkyKlnit74h6OoSvR
 hiYaRWKQwHgR7t2JzMLLVXQoadebkv8rahR0sQBInRus/s+XGC/n78VAUHNJYUKC
 +lykvMOokxSwJA3RtethsGmf9PEclr9LSLqenZ7GsrvYyv6ZuaLQjChN+EtMyQgt
 C5vRw0octczi51OBDrmiHPVOKs9ZPM9BC3bQLpKLUyiW+LDQmKZ6rVAV21Ofbm+X
 rPAyq6q3GXJWDty9QJzYpLZfSyWsqDwwjzzYw8RcLjyOMrnA/DU8oRa0uxzl03ZZ
 h2UTspCfUSPaRuAZ7vo0
 =SARm
 -----END PGP SIGNATURE-----

Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late

Pull "Amlogic DT updates for v4.11, round 2" from Kevin Hilman:

- add SAR ADC driver
- add ADC laddered keys to meson-gxbb-p200 board

* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: meson-gxbb-p200: add ADC laddered keys
  ARM64: dts: meson: meson-gx: add the SAR ADC
  ARM64: dts: meson-gxl: add the pwm_ao_b pin
  ARM64: dts: meson-gx: add the missing pwm_AO_ab node
  clk: gxbb: fix CLKID_ETH defined twice
  ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
  clk: gxbb: add the SAR ADC clocks and expose them
  dt-bindings: amlogic: Add WeTek boards
  ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
  dt-bindings: vendor-prefix: Add wetek vendor prefix
  ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
  ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
  ARM64: dts: meson-gxbb-vega-s95: Add LED
  ARM64: dts: meson-gx: add the serial CTS and RTS pin groups
  ARM64: dts: meson-gx: add the missing uart_AO_B
  clk: meson-gxbb: Export HDMI clocks
  ARM64: dts: meson-gxm: add SCPI configuration for GXM
  ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
2017-02-16 17:50:04 +01:00
Arnd Bergmann
d0f7de9258 Samsung DeviceTree ARM64 update for v4.11, third round:
1. Add necessary initial configuration for clocks of display subsystem.
    Till now it worked mostly thanks to bootloader.
 2. Use macro definitions instead of hard-coded values for pinctrl on Exynos7.
 3. Enable USB 3.0 (DWC3) on Exynos7.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYk3YaAAoJEME3ZuaGi4PXYwAP/2d7SiLymurXwmctrxm9Q5kI
 ZD7xdTr5JWq/sbuGfDHLKUz4iPMBsdQqRwczZ+DSls+Iet1fNw4enmoU/p1SpZ/5
 31EFB3uN28DSL4ZA3SzOrzPgcdMRxXOYhUMq9DTY5N8h0LlI2TwB3WBDgWTpGB6R
 NXX3wKulH2hXJyOizOZh2yel5KvzLqug7j/V0u9K1OmUISmTy3XfDWaXIVk33MUw
 IZ6qpgTzShw6sZj5VmR9CFPFbDjwExTVenIA9gwewJlQNQnqrsg0BdEF3ZvasW+V
 eFeLV4ieZHKzEoVjwdxGgTLLwjjL/orsWQ5CYiQNeCKC85rgTVfijTe8s+QKOYAq
 SiV1GghHACExpCULhtQiqioFsUAUPJ+iq/EZ9NfNh7QzE5Y05RJ7bRgRd2UdBlN8
 BXhekgN5RepLwKWHK8oYivMMpIKzDve1ICRpQYBVxmmwg9nzRz6Nij2YUi4oEb5j
 77FOuyKe5M+QCIoKVn2v/CDQMemGkI8OEsKubjDKcOZ2V2COw7Sr1L/GCGVCslLM
 FyOjaTKeoIzkrx62qgqGFuNwEaZwW0dDacHrZrccEAn9P9G7O/cU8EE9F5nJqGG0
 IeDaPH7BqQ0gOHbvrEkljSbJuuOMQmZJl6qh8MMJYB9P8u9Ft3OXUXJ1qBNZB4si
 E5nFWGj0CMm0UfBWgkD/
 =02Sx
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late

Pull "Samsung DeviceTree ARM64 update for v4.11, third round" from Krzysztof Kozłowski:

1. Add necessary initial configuration for clocks of display subsystem.
   Till now it worked mostly thanks to bootloader.
2. Use macro definitions instead of hard-coded values for pinctrl on Exynos7.
3. Enable USB 3.0 (DWC3) on Exynos7.

* tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (27 commits)
  arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
  arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
  arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
  pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
  arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
  clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
  clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
  arm64: dts: exynos: Add clocks to Exynos5433 LPASS module
  arm64: dts: exynos: set LDO7 regulator as always on
  arm64: dts: exynos: configure TV path clocks for Ultra HD modes
  arm64: dts: exynos: Fix drive strength of sd0_xxx pin definitions
  arm64: dts: exynos: Disable pull down for audio pins in Exynos5433 SoCs
  arm64: dts: exynos: Add TM2 touchkey node
  arm64: dts: exynos: Remove unneeded unit names in Exynos5433 nodes
  arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2
  arm64: dts: exynos: Add HDMI node to Exynos5433
  arm64: dts: exynos: Add DECON_TV node to Exynos5433
  arm64: dts: exynos: Fix addresses in node names on Exynos5433
  arm64: dts: exynos: Make TM2 and TM2E independent from each other
  arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E
  ...
2017-02-16 17:46:52 +01:00
Guenter Roeck
6ff8ec98e1 clk: qcom: Do not drop device node twice
of_find_node_by_name() drops the reference to a passed device node.
It is not necessary to drop it again, and doing so may result in the
device node being released prematurely.

Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Fixes: ee15faffef ("clk: qcom: common: Add API to register board clocks backwards compatibly")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-15 17:17:55 -08:00
Thomas Petazzoni
1006ccccd0 clk: mvebu: adjust clock handling for the CP110 system controller
This commit:

 - makes the GOP_DP (bit 9) gatable clock a child clock of the
   SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit
   18 was just named SD_MMC, but since it also covers the GOP block, it
   is renamed SD_MMC_GOP.

 - makes the MG (bit 5) gatable clock a child clock of the MG_CORE
   clock (bit 6)

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-14 10:59:15 -08:00
Chris Packham
3370726042 clk: mvebu: Expand mv98dx3236-core-clock support
The initial implementation in commit e120c17a70 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-10 09:21:30 -08:00
Baoyou Xie
48239135dd clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.

Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-10 09:17:38 -08:00
Wei Yongjun
09bdcd6e17 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()
PTR_ERR should access the value just tested by IS_ERR, otherwise
the wrong error code will be returned.

Fixes: 783ab76ae5 ("clk: sunxi-ng: Add A80 Display Engine CCU")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-06 15:01:29 -08:00
Arnd Bergmann
f3f1ea34fe clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i
We get a link error when CCU_MULT is not set with the
newly added driver:

drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.17+0x4): undefined reference to `ccu_mult_ops'
drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.5+0x4): undefined reference to `ccu_mult_ops'

Fixes: 5e73761786 ("clk: sunxi-ng: Add sun5i CCU driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-06 14:48:59 -08:00
Stephen Boyd
5d806f9fc8 clk: sunxi-ng: Check kzalloc() for errors and cleanup error path
This kzalloc() could fail. Let's bail out with -ENOMEM here
instead of NULL dereferencing. That silences static checkers. We
should also cleanup on the error path even though this function
returning an error probably means the system won't boot.

Cc: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-06 14:48:32 -08:00
Thierry Reding
ca6f2796ee clk: tegra: Add BPMP clock driver
This driver uses the services provided by the BPMP firmware driver to
implement a clock driver based on the MRQ_CLK request. This part of the
BPMP ABI provides a means to enumerate and control clocks and should
allow the driver to work on any chip that supports this ABI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03 12:36:36 -08:00
Stephen Boyd
5775a4c76f Non-critical fix for the pclk_edp divider on rk3399, one new clock-id
and making niu (interconnect) clocks critical on rk3288, as
 CLK_IGNORE_UNUSED is not enough to keep them running all the time
 when more users access particular clock subtrees.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAliRFEMQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgWHMB/0ZQ1p88CmxkN8kiaJBkO8UpmLuRrPivXoH
 HiZBN9fvxdR7DcrhQvH8kSt2Ir9h3Rc22TzPWChcwq1io66Bd8BuXkPP/vP9am8J
 It0VeERQzyHTLY++DYTsBmQmuaxPRm9cFsxLY5i4vowipjinFj/gDDX6DIg97j2p
 r0ytQQhOM47sRhfJSrGFsfXZIa5z5Ty0Qg04ESGmvIllrMUlm9N7+U667qknkYLW
 j2T7jWAK2l3RVe9AC7Bf10l7sldzHPHY5MuQ5WiFUWW3OgJyIUKJbD8jythg9i8V
 +54LsmX3HkIjS1OiIwECtU1Nv2t8w9RqDRCubzp/Yf+ff+oDL0h3
 =VeAF
 -----END PGP SIGNATURE-----

Merge tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull Rockchip clk updates from Heiko Stuebner:

  "Non-critical fix for the pclk_edp divider on rk3399, one new
  clock-id and making niu (interconnect) clocks critical on
  rk3288, as CLK_IGNORE_UNUSED is not enough to keep them running
  all the time when more users access particular clock subtrees."

* tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3288: make all niu clocks critical
  clk: rockchip: use rk3288 vip_out clock ids
  clk: rockchip: add rk3288 vip_out clock id
  clk: rockchip: fix the incorrect pclk_edp div width for RK3399
2017-02-03 12:07:35 -08:00
Masahiro Yamada
2a3532214e clk: uniphier: add eMMC clock for LD11 and LD20 SoCs
Add clock for the Cadence eMMC controller on LD11/LD20.
For the other SoCs, the clock for the eMMC controller is included
in the MIO/SD control block.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03 11:55:21 -08:00
Masahiro Yamada
19771622d8 clk: uniphier: add NAND clock for all UniPhier SoCs
Add clock line for the Denali NAND controller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03 11:55:20 -08:00
Stephen Boyd
2fbae64aad Allwinner clock changes for 4.11
- Support for one new SoC, the V3s
   - Convertion of two old SoCs to the new framework, the old sun5i family
     and the A80
   - A bunch of fixes
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYkEtDAAoJEBx+YmzsjxAgLl0QAIt0GnG4tXyTsRqrregO8Qbt
 UPK/Qs0hOW5VbpPzKDsWPwNGnTbvYy9I/RDnFiMJtEVU7Cj6ttEO4XvEKnaFF0N+
 0ux0ATUIrz6p1pbSUTxV0dCfkqcI78+ECLV4Nsvs7pj5RoJVt4Z5gBMAdErrsB+6
 q1VYLXIhs5atK1dTgjEWe4VTwaCpNCwoPMgbedOuZMLB0zFRVxtB/JSxlwGHpdoy
 vYZqSUgqmDG1WNLKXAiqsa3k9BnSsX/surAfd6mVlk1MauyKzgHKzxkBrvbNjAMR
 juaQcSXwkTOm8bRXj7E7NSFFBWiPUJt6dvXCxRJau79k+bYyPduv0UNu7T0a1IjM
 lN0PyJcY22m9O9nsoXVSMvU9YJJd91R94UQRpRSQxN1sOLMGVwnCDhQnB5RJhV3p
 gRZNZETTT/rP8E3plJJdce5xCsI6FXUT0jYTQW9cWVTcZbhKsntgNoEE4w/tqWIw
 dgE/2UzReyBkWzi9OgjKyca+q8zEd6i1w9DqAg3MwwR8K03oS/aKkBaHjgwk/i8x
 uiRXxhT5gLFhYOCwz3DmWw3OjwU7uCifyybGKCoxUE7U/3d2AalsTISCm3PX3dxl
 RTDPJWKOSfCyzTJNZpHM5MtIKGh/jM4/yUQ3ARXTGyIa9Uxb4DXlEH6gXvrZ4BUA
 UsyJ8d19owDqLIBYaE42
 =Jkg2
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock updates from Maxime Ripard:

  - Support for one new SoC, the V3s
  - Conversion of two old SoCs to the new framework, the old sun5i family
    and the A80
  - A bunch of fixes

* tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
  ARM: dts: sun9i: Switch to new clock bindings
  clk: sunxi-ng: Add A80 Display Engine CCU
  clk: sunxi-ng: Add A80 USB CCU
  clk: sunxi-ng: Add A80 CCU
  clk: sunxi-ng: Support separately grouped PLL lock status register
  clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
  clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
  clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
  clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU
  clk: sunxi-ng: Call divider_round_rate if we only have a single parent
  ARM: gr8: Convert to CCU
  ARM: sun5i: Convert to CCU
  clk: sunxi-ng: Add sun5i CCU driver
  clk: sunxi-ng: Implement global pre-divider
  clk: sunxi-ng: Implement multiplier maximum
  clk: sunxi-ng: mult: Fix minimum in round rate
  clk: sunxi-ng: Implement factors offsets
  clk: sunxi-ng: multiplier: Add fractional support
  clk: sunxi-ng: add support for V3s CCU
  dt-bindings: add device binding for the CCU of Allwinner V3s
  ...
2017-02-03 11:47:47 -08:00
Viresh Kumar
8a31d9d942 PM / OPP: Update OPP users to put reference
This patch updates dev_pm_opp_find_freq_*() routines to get a reference
to the OPPs returned by them.

Also updates the users of dev_pm_opp_find_freq_*() routines to call
dev_pm_opp_put() after they are done using the OPPs.

As it is guaranteed the that OPPs wouldn't get freed while being used,
the RCU read side locking present with the users isn't required anymore.
Drop it as well.

This patch also updates all users of devfreq_recommended_opp() which was
returning an OPP received from the OPP core.

Note that some of the OPP core routines have gained
rcu_read_{lock|unlock}() calls, as those still use RCU specific APIs
within them.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> [Devfreq]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2017-01-30 09:22:21 +01:00
Chen-Yu Tsai
783ab76ae5 clk: sunxi-ng: Add A80 Display Engine CCU
With the A80 SoC, Allwinner grouped and moved some subsystem specific
clock controls to a separate address space, and possibly separate
hardware block.

One such subsystem is the display engine. The main clock control unit
now only has 1 set of bus gate, dram gate, module clock, and reset
control for the entire display subsystem. These feed into a secondary
clock control unit, which has controls for each individual module
of the display pipeline. This block is not documented in the user
manual. Allwinner's kernel was used as the reference.

Add support for the display engine clock controls found on the A80.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:38:30 +01:00
Chen-Yu Tsai
439b65c4bb clk: sunxi-ng: Add A80 USB CCU
Add support for the USB clock controls found on the A80.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:37:51 +01:00
Chen-Yu Tsai
b8eb71dcdd clk: sunxi-ng: Add A80 CCU
Add support for the main clock unit found in the A80. Some clocks were
not documented in the released user manual, but were found in the
official kernel from Allwinner. These include controls for the I2S,
SPDIF, SATA, and eDP blocks.

Note that on the A80, some subsystems have separate clock controllers
downstream of the main clock unit. These include the MMC, USB, and
display engine subsystems.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:37:30 +01:00
Chen-Yu Tsai
3de64bf187 clk: sunxi-ng: Support separately grouped PLL lock status register
On the Allwinner A80 SoC, the PLL lock status indicators are grouped
together in a separate register, as opposed to being scattered in each
PLL's configuration register.

Add a flag to support this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:36:20 +01:00
Chen-Yu Tsai
82aab516ec clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
If the CLK_SET_RATE_PARENT flag is set, we want to try getting the
closest parent rate.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:36:03 +01:00
Chen-Yu Tsai
216abdcc3a clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
This patch adds support for the CLK_SET_RATE_NO_REPARENT flag to the
mux determine_rate helper, based on examples from clk-composite and
clk-mux.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:35:50 +01:00
Chen-Yu Tsai
ed48205fb4 clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
The determine_rate helper used ccu_mux_helper_adjust_parent_for_prediv()
to adjust the parent_rate to account for pre-dividers, but then passed
the pristine parent clock rate from clk_hw_get_rate() to the round()
callback, thereby ignoring the pre-divider adjustment. In addition,
it was saving the adjusted parent rate back into struct
clk_rate_request.

This patch fixes this by saving the pristine parent clock rate, and
adding a copy that is adjusted and passed to the round() callback.
The pristine copy, if it is the best solution, would be saved back
to struct clk_rate_request.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:35:37 +01:00
Jeremy McNicoll
eaff16bc49 clk: qcom: SDHCI enablement on Nexus 5X / 6P
Add missing clock branch to enable onboard storage
for msm899(2/4).

Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27 13:33:05 -08:00
Stephen Boyd
1955595069 Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY,
Exynos PLL code updates and overall minor clean-ups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJYiz9+AAoJEE1bIKeAnHqLQZQP/RbrWxuvEcUiMJPkzVRCJW/v
 YRSC43ZGLQ2xDypO29pyzPKbxtZPLqA+Rlg5R2M8VcP6kUVgcHkQU4xLJTMBjKVR
 2daBdSR+vUdkrTJ1Dgm37x2TaSZZ8dmCUkQn5H8HSRKXuf+Z+TTOm2p0Ysl2fX93
 840CkRxBhe6a4rVS/PMopMLeJrIcBJJcqt8vNtzK31KJDqsPZy2j5txRA1NqT0Dp
 1E7Gb4bb+xdFb+g3f1Qpyznn34dO9sUUhVYUyTsibz/IReEGshcSz11bbrupgTp1
 OBr6x5j8MYcbj41qC7kkIN6Vz+KLBGyBPnd7SE5j3yE8y2wykZALdutFFDvrd+nb
 hBTKRErmfXQIPk74magrd6AvfVhHS6d6UbM6pISE9pit9tqUAcHGBJ3GDe+afnNi
 DZPem8S1DmRp6WjYfXSOJQrSACqx/jjV8uo0erDjYYr7oAEBaWo7e0bqyazzQL2/
 HNzp2LjM9QT+KFFJW/TP/cJju+l59ugp/xHOGJkBWTOBU8j9rKu3cVipEfcndZ52
 sxnemcMPmZ3IPQjIaW8GYyshFH0hsxU0AIkc+Hko2Qyvkc/4DFvJTHbZOC+fU8ix
 jBQEIoGT+kugFPloBrwdnMBOOx/5lSMcF/WqwZgIhLrm+ll5npf02bCYTt6tGUZd
 z76TgLRCLn8mopfjCAp6
 =QhYQ
 -----END PGP SIGNATURE-----

Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

 - Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY
 - Exynos PLL code updates and overall minor clean-ups

* tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung:
  clk: samsung: mark s3c...._clk_sleep_init() as __init
  clk: samsung: Add enable/disable support for PLL35XX clocks
  clk: samsung: exynos5433: Correct typos in SoC name
  clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
  clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
2017-01-27 11:53:06 -08:00
Stephen Boyd
d646d812f3 clk: renesas: Updates for v4.11 (take two)
- Use CLK_IS_CRITICAL to handle critical clocks,
   - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
   - Add IIC-DVFS clocks for R-Car H3 and M3-W,
   - Minor cleanups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYiw4ZAAoJEEgEtLw/Ve77TfgQAJexnyItLU6fs3X5gx6smoWQ
 rPYXw0tWWfYEkmHJbF/vcfgC+sh/6sMVIn4IS6HqDWd1HdOtJPYTX8CvwlsQx0Ry
 NrcoConiFlatEM5sNf6w0aAUkwrDxIjZMNNnShfZRkZL7s9Jlhs5UUUbBY4uYPGG
 kJ7qr6hUoxQQ1S3z8iz/ol++tp/A+8zN0J+zLDdxcV0SRjxh/NWOOtjno9tWXXqd
 60eseC5FJNQOYV/6DXkpHsxNLsG6N2i7CVPC3SWxrijTQB1BDYAj/Pc3rD4u7Exo
 g2QTb8ywufWFi5ANhQX2oirewaiw6B2PoQyw7+7a/86OlTQVM7lfRb8hNnOJycqd
 X2YKBCNGeg4sysGURSYIDlzoq0ZDZnw7URc2+0HfeZXJjRCTmswpzRAv/wq4ILLK
 uAy5skI+XWKCuVk/w8lsWBo29hcu9Mm1lTsW739niJR4Kk9WQkK+JgF7x8FxzmLx
 7W8Rpbiz1N1D8ajlJWo/FAMdfx0SqevLlQlhCNVjExl7szmOcsF8RPnx542oRfwe
 wgJLCmCc9msP6FdWWSXB5BLNgPbaCAOoPfzpn5xouOe2xj6V5Ctv5kBTLfTqs+5S
 3SxsU08UZ4mxBeynjtuNwaX35KVs5Y1+FZQQD5MNxq8C2OvDx5ioWkH+YWFjOmgA
 9zghcMX9FG1KNLWh+RUD
 =WluB
 -----END PGP SIGNATURE-----

Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Use CLK_IS_CRITICAL to handle critical clocks,
  - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1,
  - Add IIC-DVFS clocks for R-Car H3 and M3-W,
  - Minor cleanups.

* tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add IIC-DVFS clock
  clk: renesas: r8a7795: Add IIC-DVFS clock
  clk: renesas: cpg-mssr: Add support for reset control
  clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock
  clk: renesas: cpg-mssr: Document suitability for RZ/G1
  dt-bindings: clock: renesas: cpg-mssr: Document reset control support
  clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff
  clk: renesas: mstp: Make INTC-SYS a critical clock
  clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
2017-01-27 11:51:37 -08:00
jbrunet
2d3b74d383 clk: gxbb: fix CLKID_ETH defined twice
CLKID_ETH is define in the dt-bindings but has not be commented out in the
clock driver. Just do it now.

Fixes: 738f66d321 ("clk: gxbb: add AmLogic GXBB clk controller driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-27 10:56:57 -08:00
Chris Packham
e120c17a70 clk: mvebu: support for 98DX3236 SoC
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.

The clock gating options are a subset of those on the Armada XP.

The core clock divider is different to the Armada XP also.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27 10:48:03 -08:00
Martin Kaiser
02c952c8f9 clk: samsung: mark s3c...._clk_sleep_init() as __init
These functions are referencing s3c...._clk_regs[], which are marked as
__initdata. When compiling with CONFIG_DEBUG_SECTION_MISMATCH=y, this
produces warnings like

WARNING: vmlinux.o(.text+0x198350):
Section mismatch in reference from the function s3c2410_clk_sleep_init()
to the (unknown reference) .init.data:(unknown)

Mark the s3c...._clk_sleep_init() functions as __init in
order to fix this.

Fixes: ca2e90ac18 ("clk: samsung: add clock controller driver for s3c2412")
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27 13:30:00 +01:00
Marek Szyprowski
96a8d7536f clk: samsung: Add enable/disable support for PLL35XX clocks
Some PLLs might be disabled by default after turning off and then on
a power domain which they belongs to.  To avoid configuring a disabled
PLL, add proper code for handling PLL enable/disable.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27 13:29:59 +01:00
Marek Szyprowski
9341e39d41 clk: samsung: exynos5433: Correct typos in SoC name
This patch fixes simple typos in Exynos5433 clocks driver. The SoC name
was referred a few times as '5443' instead of '5433'.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27 13:29:43 +01:00
Marek Szyprowski
698e0d1d22 clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure
such configuration for those boards with 'assigned-clock-*' properties,
parameters for those two additional rates are needed.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27 11:34:00 +01:00
Marek Szyprowski
5ccb58968b clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27 11:33:59 +01:00