Commit Graph

8 Commits

Author SHA1 Message Date
Tony Lindgren
be76fd3197 ARM: dts: Add #pinctrl-cells for pinctrl-single instances
Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while
pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the
driver changes as the driver supports also the legacy binding without
#pinctrl-cells.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-11-07 08:27:49 -07:00
Nishanth Menon
11b897a2f7 ARM: dts: keystone-k2g: Add Message Manager node
Introduce the message manager node for the A15 queues on which Linux
runs. The Message Manager is primarily used for communication with
Power Management controller on K2G.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2016-08-31 16:32:16 -04:00
Andrew F. Davis
e0f0b54c02 ARM: dts: keystone-k2g: Add DSP GPIO controller node
Add the DSP GPIO controller node on K2G SoC.
This is used to send interrupts to the only DSP processor
subsystem present on the SoC. The IP is identical to that
of the equivalent nodes on existing K2 SoCs.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2016-08-31 16:29:59 -04:00
Andrew F. Davis
0884b1b338 ARM: dts: keystone-k2g: Add keystone IRQ controller node
Add the Keystone IRQ controller IP node on K2G SoC. This allows the
ARM CorePac core to receive interrupts from remote processor devices
(eg: DSP) on the SoC.

The IP is identical in functionality to that of the equivalent
nodes on existing K2 SoCs. The only difference is the ARM INTC
interrupt id/event number.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2016-08-31 16:29:59 -04:00
Andrew F. Davis
08fa198ded ARM: dts: keystone-k2g: Add device state controller node
Add the device state controller node as a syscon node to the
K2G SoC. This module provides similar device control functionality
as that on the existing K2 SoCs.

One example usage would be the boot address programming of the
DSP processor sub-system.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2016-08-31 16:29:59 -04:00
Lokesh Vutla
eb53a15b1a ARM: dts: keystone: Header file for pinctrl constants
The pinctrl IP used in some of the Keystone 2 devices differ vs other
TI SoCs. Therefore, create a Keystone specific pinctrl header.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2016-06-09 09:40:21 -07:00
Vitaly Andrianov
fb25225919 ARM: dts: k2g: Add pinctrl support
Add pinctrl support.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2016-06-09 09:40:21 -07:00
Vitaly Andrianov
734539eaf4 ARM: dts: keystone: Add Initial DT support for TI K2G SoC family
K2G is the newest addition of TI's Keystone 2 product family. It is a
single core Cortex A15 and a C66x DSP.

K2G supports standard peripherals such as SPI, UART, MMC and USB 2.0.

Includes two dual-core Programmable Real-time Unit and Industrial
Communication Subsystems (PRU-ICSS).

The technical reference manual for K2G can be found here:
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf

This device is targeted for a variety of applications which include, but
are not limited to:

Home audio
Professional audio
Industrial Programmable Logic Control

The peripheral nodes that have been included in this patch have been
tested during bring-up. Since all peripherals will not necessarily be
used on all boards, disable all peripherals by default. This allow
the board dts to selectively choose which peripherals it wants to
enable.

This SoC now uses the next generation of power management architecture
with the PM functionality located in a microcontroller embedded in the SOC.

Support for this new PM architecture along with other peripherals will be
added in future patches.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2016-02-25 09:25:35 -08:00