Commit Graph

203757 Commits

Author SHA1 Message Date
Stephen Boyd
2ec941304d clk: qcom: Add support for MSM8960's global clock controller (GCC)
Add a driver for the global clock controller found on MSM8960
based platforms. This should allow most non-multimedia device
drivers to probe and control their clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:01:02 -08:00
Stephen Boyd
b36ba30c8a clk: qcom: Add reset controller support
Reset controllers and clock controllers are combined into one IP
block on Qualcomm chipsets. Usually a reset signal is associated
with each clock branch but sometimes a reset signal is associated
with a handful of clocks. Either way the register interface is
the same; set a bit to assert a reset and clear a bit to deassert
a reset. Add support for these types of resets signals.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:01:02 -08:00
Stephen Boyd
6e0ad1b6c1 clk: qcom: Add support for branches/gate clocks
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:01:01 -08:00
Stephen Boyd
bcd61c0f53 clk: qcom: Add support for root clock generators (RCGs)
Add support for the root clock generators on Qualcomm devices.
RCGs are highly customizable mux/divider/counter clocks that can
be used to generate almost any rate desired given some input
source that is faster than the desired rate.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:01:00 -08:00
Stephen Boyd
9e2631313c clk: qcom: Add support for phase locked loops (PLLs)
Add support for Qualcomm's PLLs (phase locked loops). This is
sufficient enough to be able to determine the rate the PLL is
running at. We can add rate setting support later when it's
needed.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:00:59 -08:00
Stephen Boyd
085d7a4554 clk: qcom: Add a regmap type clock struct
Add a clock type that associates a regmap pointer and some
enable/disable bits with a clk_hw struct. This will be the struct
that a hw specific implementation wraps if it wants to use the
regmap helper functions.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:00:58 -08:00
Stephen Boyd
3fa2252b7a clk: Add set_rate_and_parent() op
Some of Qualcomm's clocks can change their parent and rate at the
same time with a single register write. Add support for this
hardware to the common clock framework by adding a new
set_rate_and_parent() op. When the clock framework determines
that both the parent and the rate are going to change during
clk_set_rate() it will call the .set_rate_and_parent() op if
available and fall back to calling .set_parent() followed by
.set_rate() otherwise.

Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:00:57 -08:00
Barry Song
7bf21bc81f clk: sirf: re-arch to make the codes support both prima2 and atlas6
sirfprima2 and sirfatlas6 are two different SoCs in CSR SiRF series. for
prima2 and atlas6, there are many shared clocks but there are still
some different register layout and hardware clocks, then result in
different clock table.

here we re-arch the driver to
1. clk-common.c provides common clocks for prima2 and atlas6,
2. clk-prima2.h describles registers of prima2 and clk-prima2.c provides
prima2 specific clocks and clock table.
3. clk-atlas6.h describles registers of atlas6 and clk-atlas6.c provides
atlas6 specific clocks and clock table.
4. clk.h and clk.c expose external interfaces and provide uniform entry
for both prima2 and atlas6.

so both prima2 and atlas6 will get support by drivers/clk/sirf.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 12:00:53 -08:00
Mike Turquette
5d2043fbe4 clk: composite: pass mux_hw into determine_rate
The composite clock's .determine_rate implementation can call the
underyling .determine_rate callback corresponding to rate_hw or the
underlying .determine_rate callback corresponding to mux_hw. In both
cases we pass in rate_hw, which is wrong. Fixed by passing mux_hw into
the correct callback.

Reported-by: Lemon Dai <dailemon.gl@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-15 07:48:03 -08:00
Mike Turquette
119754e576 Merge branch 'clk-next-shmobile' into clk-next 2014-01-14 11:41:26 -08:00
Valentine Barshak
209f4fedcf clk: shmobile: Fix MSTP clock array initialization
The clks member of the clk_onecell_data structure should
point to a valid clk array (no NULL entries allowed),
and the clk_num should be equal to the number
of elements in the clks array.

The MSTP driver fails to satisfy the above conditions.
The clks array may contain NULL entries if not all
clock-indices are initialized in the device tree.
Thus, if the clock indices are interleaved we end up
with NULL pointers in-between.

The other problem is the driver uses maximum clock index
as the number of clocks, which is incorrect (less than
the actual number of clocks by 1).

Fix the first issue by pre-setting the whole clks array
with ERR_PTR(-ENOENT) pointers instead of zeros; and
use maximum clkidx + 1 as the number of clocks to fix
the other one.

This should make of_clk_src_onecell_get() return the following:
* valid clk pointers for all clocks registered;
* ERR_PTR(-EINVAL) if (idx >= clk_data->clk_num);
* ERR_PTR(-ENOENT) if the clock at the selected index was not
  initialized in the device tree (and was not registered).

Changes in V2:
* removed brackets from the one-line for loop

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-14 11:35:57 -08:00
Valentine Barshak
6413b090de clk: shmobile: Fix MSTP clock index
Use clkidx when registering MSTP clocks instead of loop counter
since the value is then used to access the specific clock index bit
in the mstp register.

The issue was introduced by the following commit:
f94859c215 "clk: shmobile: Add MSTP clock support"

Changes in V2:
* none

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-14 11:35:45 -08:00
Mike Turquette
baa39cd20e (A bit late) first round of Samsung clock patches for v3.14.
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Merge tag 'for_3.14/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung

(A bit late) first round of Samsung clock patches for v3.14.
2014-01-08 16:38:10 -08:00
Tomasz Figa
b06c698716 clk: max77686: Register OF clock provider
If max77686 chip is instantiated from device tree, it is desirable to
have an OF clock provider to allow device tree based look-up of clocks.
This patch adds OF clock provider registration to the clk-max77686
driver.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-08 09:57:07 -08:00
Tomasz Figa
3966c947f4 clk: max77686: Refactor driver data handling
As a prerequisite for further patch adding OF clock provider support to
the driver, this patch changes the driver to store an array of struct
clk * as driver data.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-08 09:57:07 -08:00
Tomasz Figa
d73ac4ca66 clk: max77686: Fix clean-up in error and remove paths
This patch fixes invalid kfree() and adds missing call to clk_unregister()
in error and remove paths in max77686_clk_probe(). While at it, error
handling is also cleaned up.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-08 09:53:52 -08:00
Tomasz Figa
badbc542f9 clk: max77686: Make max77686_clk_register() return struct clk *
As a preparation for further patches, this patch modifies the clock
registration helper function to return a pointer to the newly registered
clock. No functional change is done to the driver.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-08 09:46:03 -08:00
Tomasz Figa
b0f8517771 clk: max77686: Refactor successful exit of probe function
The function can simply return 0, without jumping to a separate label,
which does exactly the same. This patch does not introduce any
functional change, just a clean-up.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-08 09:46:03 -08:00
Tomasz Figa
cf7d4a6f84 clk: max77686: Provide .recalc_rate() operation
It is usually nice to know frequency of a clock, so this patch adds a
.recalc_rate() callback returning rates of provided clocks.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-08 09:46:03 -08:00
Tomasz Figa
21c8ed2dc0 clk: max77686: Correct callback used for checking clock status
Changing status of clock gates in max77686 requires i2c transfers, which
can sleep, so this is done in prepare and unprepare callbacks. Due to
this, checking whether whether the clock is ungated must be done
in is_prepared() callback as well, for consistency.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-08 09:46:02 -08:00
Andrew Bresticker
3538a2cf0e clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:43 +01:00
Andrew Bresticker
35399dda01 clk: exynos5250: add clock ID for div_pcm0
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0.  Add a clock ID for it so that
we can reference it in device trees.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:42 +01:00
Andrew Bresticker
547f33509c clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings.  Default names will be used
when an input clock is not given.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:41 +01:00
Andrew Bresticker
b37a422410 clk: exynos-audss: convert to platform device
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs.  This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed.  Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:41 +01:00
Andrzej Hajda
ad3ab455d3 clk: exynos5440: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:40 +01:00
Andrzej Hajda
cba9d2fa8b clk: exynos5420: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:39 +01:00
Andrzej Hajda
2fe8f00c49 clk: exynos5250: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:38 +01:00
Andrzej Hajda
2d73823750 clk: exynos4: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:38 +01:00
Andrew Bresticker
f521ac8b39 clk: exynos5250: register APLL rate table
Register the APLL rate table so that we can set the APLL rate from
the cpufreq driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:01:49 +01:00
Mike Turquette
dbdf6ff51e Merge branch 'clk-next-unregister' into clk-next
Conflicts:
	drivers/clk/clk.c
2013-12-31 11:35:12 -08:00
Mike Turquette
391e3903e6 Merge branch 'for_3.14/keystone-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into clk-next-keystone 2013-12-30 10:58:22 -08:00
Sachin Kamat
e86ffc4199 clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apll
Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the
clock rate in the cpufreq driver.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:43:28 +01:00
Tomasz Figa
96987ded8f clk: samsung: exynos5250: Fix parents of gate clocks from MFC domain
This patch adds mout_aclk333_sub mux clock and updates gate clocks from
MFC domain to have it as their parent as specified in SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:49 +01:00
Tomasz Figa
bfeb9f274b clk: samsung: exynos5250: Correct parent list of audio muxes
According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:49 +01:00
Tomasz Figa
256dd646a3 clk: samsung: exynos5250: Add missing unpopulated mux parents
This patch updates mux parent arrays with unpopulated mux inputs, as all
inputs need to be specified in parent arrays passed to
clk_register_mux(), otherwise clk_set_parent() can generate out of bound
accesses to the array.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:48 +01:00
Tomasz Figa
3818f11740 clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:48 +01:00
Tomasz Figa
796d1f4cd6 clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domain
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions
of GSCL domain gate clocks to use it as their parent, as specified in
SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:47 +01:00
Tomasz Figa
38ee37540f clk: samsung: exynos5250: Make names of mux and div clocks consistent
This patch renames all mux clocks to start with mout_ prefix and all div
clocks to start with div_ prefix for consistency with other clocks
already defined this way.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:47 +01:00
Tomasz Figa
2786c9622e clk: samsung: exynos5250: Sort definitions by registers and bitfield
This patch reorders clock definitions, so they are sorted by register
addresses and bitfield shifts. When at it, blank lines are added to
separate definitions of clocks from different registers.

Overall this should make the driver more readable and reduce the number
of potential conflicts when adding new entries.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:15:46 +01:00
Tomasz Figa
2bb00c68e0 Merge branch 'samsung-fixes' into samsung-next-base 2013-12-30 18:15:23 +01:00
Krzysztof Kozlowski
3fd68c99f3 clk: exynos: File scope reg_save array should depend on PM_SLEEP
Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only
by suspend and resume functions.

This fixes the warning on CONFIG_PM_SLEEP=n:
drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable]

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 18:01:09 +01:00
Abhilash Kesavan
2feed5aecf clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:59:25 +01:00
Abhilash Kesavan
8fb9aeb7a7 clk: samsung: exynos5250: Add MDMA0 clocks
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:55:52 +01:00
Abhilash Kesavan
3bf34666a0 clk: samsung: exynos5250: Fix ACP gate register offset
The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:53:26 +01:00
Andrew Bresticker
97c3557c3e clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:53:22 +01:00
Seung-Woo Kim
5fdd1b56be clk: samsung: exynos4: Correct SRC_MFC register
The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30 17:53:18 +01:00
Mike Turquette
6b71e0d9d6 Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi
Allwinner sunXi SoCs clock changes

This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi:
add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and
mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH
1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu
Tsai, which adds support for output clocks present on A20.
2013-12-29 13:37:56 -08:00
Chen-Yu Tsai
6f86341726 clk: sunxi: Allwinner A20 output clock support
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
2013-12-28 17:14:21 -03:00
Emilio López
76192dc887 clk: sunxi: support better factor DT nodes
The DT nodes should look like

    abc_clk: clk@deadbeef {
        ...
        clock-output-names = "abc";
    }

But our old DT nodes look like

    abc: abc@deadbeef {
        ...
    }

So, let's support both formats, until we can transition everything
to the new, correct one.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:08:25 -03:00
Emilio López
7551769a22 clk: sunxi: mod0 support
This commit implements support for the "module 0" type of clocks, as
used by MMC, IR, NAND, SATA and other components.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:08:22 -03:00