Commit Graph

19 Commits

Author SHA1 Message Date
Christian Lamparter
ab703f818a dmaengine: dw: lazy allocation of dma descriptors
This patch changes the driver to allocate DMA descriptors when
needed. This stops memory resources to be wasted and letting
them sit idle in the free_list structure when the device doesn't
need it... This also solves the problem, that a driver has to
guess the number of how many descriptors it needs to allocate
in advance. Currently, the dma engine will just fail when put
under load by sata_dwc_460ex.

Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-19 21:14:45 +05:30
Andy Shevchenko
b68fd09762 dmaengine: dw: move residue to a descriptor
Residue is a property of any active descriptor. So, any descriptor may be in
different state but residue is a feature of active descriptor. Check if the
asked descriptor is active and return proper residue value for it.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-13 21:36:16 +05:30
Andy Shevchenko
423f9cbf2d dmaengine: dw: move dwc->initialized to dwc->flags
We have already dedicated variable for flags, therefore no need to create an
additional storage for that. Covert dwc->initialized to use dwc->flags.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-13 21:36:16 +05:30
Andy Shevchenko
5e09f98e77 dmaengine: dw: move dwc->paused to dwc->flags
We have already dedicated variable for flags, therefore no need to create an
additional storage for that. Convert dwc->paused to use dwc->flags.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-13 21:36:15 +05:30
Andy Shevchenko
897e40d3b1 dmaengine: dw: substitute dma_read_byaddr by dma_readl_native
Since struct dw_dma is allocated and regs member is assigned properly we can
use standard IO accessors to the DMA registers.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-13 21:36:10 +05:30
Mans Rullgard
2a0fae025e dmaengine: dw: set LMS field in descriptors
The LMS field indicates from which master the descriptor is to be
read.  This patch assumes this is always the same as the memory
side in a peripheral transfer which is true for all known systems.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-13 21:36:10 +05:30
Mans Rullgard
df1f3a2305 dmaengine: dw: fix byte order of hw descriptor fields
If the DMA controller uses a different byte order than the host CPU,
the hardware linked list descriptor fields need to be byte-swapped.

This patch makes the driver write these fields using the same byte
order it uses for mmio accesses to the DMA engine. I do not know
if this is guaranteed to always be correct.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-13 21:36:10 +05:30
Andy Shevchenko
c422025c18 dmaengine: dw: rename masters to reflect actual topology
The source and destination masters are reflecting buses or their layers to
where the different devices can be connected. The patch changes the master
names to reflect which one is related to which independently on the transfer
direction.

The outcome of the change is that the memory data width is now always limited
by a data width of the master which is dedicated to communicate to memory.

The patch will not break anything since all current users have the same data
width for all masters. Though it would be nice to revisit avr32 platforms to
check what is the actual hardware topology in use there. It seems that it has
one bus and two masters on it as stated by Table 8-2, that's why everything
works independently on the master in use. The purpose of the sequential patch
is to fix the driver for configuration of more than one bus.

The change is done in the assumption that src_master and dst_master are
reflecting a connection to the memory and peripheral correspondently on avr32
and otherwise on the rest.

Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-13 21:36:09 +05:30
Jie Yang
c9784a4673 dmaengine: dw: fix a typo for bitfields of CTL_LO
The offset of SINC should be 9, not 7, here fix this
typo.

Signed-off-by: Jie Yang <yang.jie@intel.com>
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-01-25 09:49:55 +05:30
Andy Shevchenko
d8ded50f8b dmaengine: dw: define DW_DMA_MAX_NR_MASTERS
Instead of using magic number in the code the patch provides
DW_DMA_MAX_NR_MASTERS constant.

While here, restrict the reading of data width array by amount of the actual
number of AHB masters.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-02-04 22:39:44 -08:00
Vinod Koul
295d3e10e6 dmaengine: dw: update the driver comments
driver comment refers to DMA_SLAVE_CONFIG which needs to be updated to
.device_config

Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-12-22 20:26:45 +05:30
Andy Shevchenko
99d9bf4ed2 dmaengine: dw: enable and disable controller when needed
Enable controller automatically whenever first user requires for a channel and
disable it when the last user gone.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-15 20:31:05 +05:30
Andy Shevchenko
46e8c83c83 dmaengine: dw: move private definitions to regs.h
Since we don't allow user to set registers directly through private slave
configuration we may move definitions to the regs.h because they are not used
anywhere except core.c part.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-15 20:31:04 +05:30
Andy Shevchenko
a15636e83e dmaengine: dw: move clock operations to platform.c
On BayTrail platform DMA is not functional in the PCI mode, whereby it always
failed and exit at the point when it tries to get a clock. It causes the PCI
mode probe to exit with the error message:
	dw_dmac_pci: probe of 0000:00:1e.0 failed with error -2

This patch moves clock operations to where it belongs to. Thus, the clock is
provided only in ACPI / non-PCI cases.

Reported-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-09-11 11:48:13 +05:30
Andy Shevchenko
8950052029 dmaengine: dw: apply both HS interfaces and remove slave_id usage
Instead of one request line member let's use both source and destination ones.
Usually we have no such hardware except Atmel MMC controller found on AVR32
platform (see arch/avr32/mach-at32ap/at32ap700x.c and
drivers/mmc/host/atmel-mci.c).

This patch removes slave_id usage since it'll be removed from the generic
structure in later. This breaks the non-ACPI / non-DT cases for the users of
the driver, i.e. SPI and HSUART. However, these cases mean only PCI enumerated
devices for now, which is anyway broken (considering more than one DMA
controller in the system) and this patch series is intended to fix that
eventually.

The ACPI and DT cases shall be aware of the channel direction when setting
request lines, but this is a minor problem that would be addressed in future.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-09-11 11:48:13 +05:30
Andy Shevchenko
3d598f47e8 dmaengine: dw: move dw_dmac.h to where it belongs to
There is a common storage for platform data related structures and definitions
inside kernel source tree. The patch moves file from include/linux to
include/linux/platform_data and renames it acoordingly. The users are also
updated.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
[For the arch/avr32/.* and .*sound/atmel.*]
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-09-11 11:48:12 +05:30
Andy Shevchenko
000871ce03 dma: dw: allocate memory in two stages in probe
This makes the probe() function a little bit clearer.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-03-26 11:44:27 +05:30
Vinod Koul
e368b510c0 dmaengine: dw: select DW_DMAC_BIG_ENDIAN_IO automagically
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-07-05 11:40:46 +05:30
Andy Shevchenko
9cade1a46c dma: dw: split driver to library part and platform code
To simplify the driver development let's split driver to library and platform
code parts. It helps us to add PCI driver in future.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
[Fixed compile error and few checkpatch issues]
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-07-05 11:40:44 +05:30