Commit Graph

427 Commits

Author SHA1 Message Date
Robin Murphy
29e8976e60 arm64: dts: rockchip: Add RK3328 audio pipelines
The audio pipelines for HDMI and the analog codec are internal to the
SoC, so it makes sense to describe them at that level such that boards
need only enable the respective nodes for outputs they implement.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/a09c8d795e7a66fb7bc47af2b6580f6e8dbec91e.1571090991.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-08 23:06:18 +01:00
Andy Yan
4403e1237b arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc
ROC-RK3308-CC is a rk3308 based board designed by Firelfy,
with eMMC and 256MB DDR3 and RTL8188 Wifi on board.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20191030072811.29882-1-andy.yan@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05 20:44:43 +01:00
Markus Reichl
f00736e38e arm64: dts: rockchip: Rework voltage supplies for regulators on rk3399-roc-pc
Correct the voltage supplies according to the board schematics
ROC-3399-PC-V10-A-20180804.

Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Link: https://lore.kernel.org/r/22b56700-3c9e-0f60-cd74-7ff24d4f1a23@fivetechno.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05 20:44:43 +01:00
Markus Reichl
88e0b7822d arm64: dts: rockchip: Add vcc_sys enable pin on rk3399-roc-pc
rk3399-roc-pc has vcc_sys 5V supply for USB and other peripherals.
Add the GPIO pin to enable the regulator.

Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Link: https://lore.kernel.org/r/c72db0ad-c261-af4f-efe6-22bbcf4a0b7b@fivetechno.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05 20:44:43 +01:00
Markus Reichl
389989270e arm64: dts: rockchip: Add nodes for buttons on rk3399-roc-pc
rk3399-roc-pc has a power and a recovery button, enable them.

Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Link: https://lore.kernel.org/r/1ce152cc-bd6b-63af-7892-221e084d087f@fivetechno.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-11-05 20:44:43 +01:00
Heiko Stuebner
0815dc22c2 arm64: dts: rockchip: enable usb2phy on px30-evb
Enable the phy node ion the px30 evb board.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-13-heiko@sntech.de
2019-11-05 20:44:43 +01:00
Heiko Stuebner
f952b45bf3 arm64: dts: rockchip: add usb2phy for px30
Add the usb2phy node on the px30 and hook it up to the usb controllers
it supplies.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-12-heiko@sntech.de
2019-11-05 20:44:43 +01:00
Heiko Stuebner
7272d6e03d arm64: dts: rockchip: remove px30 default optee node
Having a default optee node in a soc devicetree is not really good.
For one there is no guarantee that any tee got loaded and there's even
the possibility that a completely different TEE got loaded.

OP-Tee however will insert relevant nodes to the devicetree (firmware
+reserved memory sections) during its own startup, so there really is
no need to provide a default node.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20191023224409.3550-1-heiko@sntech.de
2019-11-05 20:44:38 +01:00
Heiko Stuebner
2e7f8764dc arm64: dts: rockchip: enable gpu on rk3399-puma
Set the supplying regulator and enable the gpu node on the rk3399-puma som.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20191023223954.3139-1-heiko@sntech.de
2019-11-05 20:44:35 +01:00
Heiko Stuebner
fbb78418c8 arm64: dts: rockchip: add px30 otp controller
The px30 soc contains a controller for one-time-programmable memory,
so add the necessary node for it and the fields defined in it by default.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20191023224113.3268-1-heiko@sntech.de
2019-11-05 20:44:31 +01:00
Markus Reichl
cec0e350ca arm64: dts: rockchip: Add LED nodes on rk3399-roc-pc
rk3399-roc-pc has three gpio LEDs, enable them.

Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Link: https://lore.kernel.org/r/7d8d85c9-5fde-7943-a6b6-639bca38bdc1@fivetechno.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-27 19:08:47 +01:00
Andy Yan
b92880e4d7 arm64: dts: rockchip: Add basic dts for RK3308 EVB
This board use uart4 as debug port and arm core voltage
is modulated by pwm, logic voltage is fixed to 1.05V.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20191021084657.28629-1-andy.yan@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-27 18:54:25 +01:00
Andy Yan
6913c45239 arm64: dts: rockchip: Add core dts for RK3308 SOC
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

This patch add basic core dtsi file for it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20191021084616.28431-1-andy.yan@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-27 18:42:42 +01:00
Johan Jonker
4ff7525371 arm64: dts: rockchip: restyle rockchip,pins on rk3399-rock-pi-4
The define RK_FUNC_1 is no longer used,
so restyle the rockchip,pins definitions.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20191015205852.4200-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-16 21:40:29 +02:00
Robin Murphy
bc43cee88a arm64: dts: rockchip: Update nanopi4 phy reset properties
Use the now-preferred generic phy reset properties instead of the
dwmac-specific ones.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/4d16c24ae3651a2119cf5bb1213f46a9fce4b39a.1570444773.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-10 23:32:35 +02:00
Robin Murphy
f94ffd95cb arm64: dts: rockchip: Enable nanopi4 HDMI audio
All the nanopi4 boards have HDMI, so let them make noise on it.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/7fe6e94e4b9f5986f19f2637b7b716f0cb54de1b.1570444701.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-10 23:32:30 +02:00
Heiko Stuebner
87d8ae980e arm64: dts: rockchip: add cr50 tpm to rk3399-gru scarlet and bob
Scarlet and Bob use the Google-developed cr50 chip to do things
like TPM and closed-case-debugging.

Add the nodes describing the cr50 and its spi-connection.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20180822120925.12388-1-heiko@sntech.de
2019-10-10 23:19:30 +02:00
Katsuhiro Suzuki
6860769ea7 arm64: dts: rockchip: add analog audio nodes on rk3399-rockpro64
This patch adds audio codec (Everest ES8316) and I2S audio nodes for
RK3399 RockPro64.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Link: https://lore.kernel.org/r/20190907174833.19957-1-katsuhiro@katsuster.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-04 21:54:06 +02:00
Heiko Stuebner
85dd763850 arm64: dts: rockchip: add missing #msi-cells to rk3399
The rk3399 gic-its was missing the #msi-cells property as found by
dt-schema checks, so add it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917083625.25818-1-heiko@sntech.de
2019-10-04 21:52:06 +02:00
Jagan Teki
9f7f9b610e arm64: dts: rockchip: Fix roc-rk3399-pc regulator input rails
Few, know rk808 pmic regulators VCC[1-4], VCC[6-7], VCC[9-11],
VDD_LOG, VDD_GPU, VDD_CPU_B, VCC3V3_SYS are inputting with vcc_sys
which is 5V power rail from dc_12v.

So, replace the vin-supply of above mentioned regulators
with vcc_sys as per the PMIC-RK808-D page of roc-rk3399-pc
schematics.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20190919052822.10403-7-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-03 23:34:30 +02:00
Jagan Teki
f1b3b7077b arm64: dts: rockchip: Rename vcc12v_sys into dc_12v for roc-rk3399-pc
It is always better practice to follow regulator naming conventions
as per the schematics for future references.

This would indeed helpful to review and check the naming convention
directly on schematics, both for the code reviewers and the developers.

So, rename vcc12v_sys into dc_12v as per rk3399 power tree as per
roc-rk3399-pc schematics.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20190919052822.10403-6-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-03 23:32:47 +02:00
Heiko Stuebner
52462ac627 arm64: dts: rockchip: add px30-evb i2c1 devices
Enable i2c1 and adds the devices connected to it.
This includes a magnetometer, goodix-touchscreen and accelerometer.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-10-heiko@sntech.de
2019-10-03 23:24:12 +02:00
Heiko Stuebner
45cb61b4f3 arm64: dts: rockchip: document explicit px30 cru dependencies
The px30 contains 2 separate clock controllers the regular cru creating
most clocks as well as the pmucru managing the GPLL and some other clocks.

The gpll of course also is needed by the cru, so while we normally do rely
on clock names to associate clocks getting probed later on (for example
xin32k coming from an i2c device in most cases) it is safer to declare the
explicit dependency between the two crus. This makes sure that for example
the clock-framework probes them in the correct order from the start.

The assigned-clocks properties were simply working by chance in the past
so split them accordingly to the 2 crus to honor the loading direction.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20190917082659.25549-9-heiko@sntech.de
2019-10-03 23:24:06 +02:00
Heiko Stuebner
689c7dc73c arm64: dts: rockchip: remove unused pin settings from px30
These are unused gpio-settings for specific function pins, that
are not used by anything and only clutter up the dtsi.
They can be re-added when a relevant user is added.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-8-heiko@sntech.de
2019-10-03 23:24:02 +02:00
Heiko Stuebner
9003aacb9c arm64: dts: rockchip: move px30-evb console output to uart 5
The px30-evb exposes uart2 through a uart-to-usb converter on the board
but these pins are shared with the sdmmc controller. With both activated
this results in a race condition depending in the probe order.
Whichever of the two probes first will break the other peripheral.

The px30-evb also exposes uart5 through pin its pin headers, so it's way
saner to use these pins for serial output and keep the sdmmc working in
all cases.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-7-heiko@sntech.de
2019-10-03 23:23:59 +02:00
Heiko Stuebner
79fd8ba2fd arm64: dts: rockchip: add emmc-powersequence to px30-evb
Hook the reset line into an emmc-pwrseq for it to get initialized nicely.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-6-heiko@sntech.de
2019-10-03 23:23:54 +02:00
Heiko Stuebner
915b6a8b54 arm64: dts: rockchip: fix the px30-evb power tree
Add the board's pmic (rk809) and hook up the real supplies to their
consumers. This is especially important as cpufreq would otherwise hang
the system when scaling the frequency without adjusting the voltage.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-5-heiko@sntech.de
2019-10-03 23:23:47 +02:00
Heiko Stuebner
cdfebb2789 arm64: dts: rockchip: add default px30 emmc pinctrl
emmc chips are normally hooked up in standard ways using the full 8bit
bus connection, so there should be no need for all future boards to define
this on their own. So add default pin setups for 8bit busses and special
boards really only needing 4 or 1 bit connections can override.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-4-heiko@sntech.de
2019-10-03 23:23:42 +02:00
Heiko Stuebner
f77ccf399e arm64: dts: rockchip: remove px30 emmc_pwren pinctrl
That gpio1-b0 can only be flash_cs apart from a regular gpio,
so there is no power-related pinmux for the emmc for this pin.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-3-heiko@sntech.de
2019-10-03 23:23:38 +02:00
Heiko Stuebner
00519137f7 arm64: dts: rockchip: remove static xin32k from px30
Similar to all other Rockchip SoCs the px30 does not have a static
32kHz clock. Instead it again gets supplied from an external component
like the pmic.

So drop the static clock, so that we can hook up the right one.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-2-heiko@sntech.de
2019-10-03 23:23:34 +02:00
Heiko Stuebner
8e57eed204 arm64: dts: rockchip: fix iface clock-name on px30 iommus
The iommu clock names are aclk+iface not aclk+hclk as in the vendor kernel,
so fix that in the px30.dtsi

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-1-heiko@sntech.de
2019-10-03 23:23:16 +02:00
Shawn Lin
03e61929c0 arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
150MHz is a fundamental limitation of RK3328 Soc, w/o this limitation,
eMMC, for instance, will run into 200MHz clock rate in HS200 mode, which
makes the RK3328 boards not always boot properly. By adding it in
rk3328.dtsi would also obviate the worry of missing it when adding new
boards.

Fixes: 52e02d377a ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs")
Cc: stable@vger.kernel.org
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Liang Chen <cl@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-09-01 03:00:17 +02:00
Jonas Karlman
e8cae2e642 arm64: dts: rockchip: add rk3328 VPU node
This patch add a VPU device node for rk3328.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-08-22 21:30:22 +02:00
Kever Yang
9301d28dcc arm64: dts: rockchip: fix vcc_host_5v regulator for usb3 host
According to rock64 schemetic V2 and V3, the VCC_HOST_5V output is
controlled by USB_20_HOST_DRV, which is the same as VCC_HOST1_5V.

V1 hardware was never sold and only V2/V3 is with customers,
so there is no need to keep a seaprate v1 version around.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-08-19 16:42:01 +02:00
Andy Yan
fc702ed49a arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC
P710 is a RK3399 based SBC, designed by Leez [0].

Specification
- Rockchip RK3399
- 4/2GB LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply

[0]https://leez.lenovo.com

Signed-off-by: Andy Yan <andyshrk@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-08-16 14:39:20 +02:00
Andrius Štikonas
22c65d80af arm64: dts: rockchip: enable internal SPI flash for RockPro64.
The rockpro64 contains a nor-flash chip connected to spi1.

Signed-off-by: Andrius Štikonas <andrius@stikonas.eu>
[a number of cleanups]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-08-16 13:50:08 +02:00
Andrius Štikonas
5882d65c16 arm64: dts: rockchip: Add PWM fan for RockPro64
RockPro64 has a dedicated circuit for driving a 12V fan from PWM1.

At the moment this makes fan spin at full speed. fancontrol can be used
to control fan speed. E.g. the following config file works well:

INTERVAL=10
DEVPATH=hwmon0=devices/platform/pwm-fan
DEVNAME=hwmon0=pwmfan
FCTEMPS=hwmon0/device/pwm1=../thermal/thermal_zone0/temp
MINTEMP=hwmon0/device/pwm1=40
MAXTEMP=hwmon0/device/pwm1=60
MINSTART=hwmon0/device/pwm1=100
MINSTOP=hwmon0/device/pwm1=70

In the future it would be nice to define trip points in dts file,
so that kernel could adjust fan speed itself.

Signed-off-by: Andrius Štikonas <andrius@stikonas.eu>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-25 22:08:51 +02:00
Sean Paul
84ebd2da6d arm64: dts: rockchip: Specify override mode for kevin panel
This patch adds an override mode for kevin devices. The mode increases
both back porches to allow a pixel clock of 26666kHz as opposed to the
'typical' value of 252750kHz. This is needed to avoid interference with
the touch digitizer on these laptops.

Cc: Doug Anderson <dianders@chromium.org>
Cc: Eric Anholt <eric@anholt.net>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stéphane Marchesin <marcheu@chromium.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-22 01:04:36 +02:00
Vicente Bergas
e1d9149e83 arm64: dts: rockchip: Fix USB3 Type-C on rk3399-sapphire
Before this patch, the Type-C port on the Sapphire board is dead.
If setting the 'regulator-always-on' property to 'vcc5v0_typec0'
then the port works for about 4 seconds at start-up. This is a
sample trace with a memory stick plugged in:
1.- The memory stick LED lights on and kernel reports:
[    4.782999] scsi 0:0:0:0: Direct-Access USB DISK PMAP PQ: 0 ANSI: 4
[    5.904580] sd 0:0:0:0: [sdb] 3913344 512-byte logical blocks: (2.00 GB/1.87 GiB)
[    5.906860] sd 0:0:0:0: [sdb] Write Protect is off
[    5.908973] sd 0:0:0:0: [sdb] Mode Sense: 23 00 00 00
[    5.909122] sd 0:0:0:0: [sdb] No Caching mode page found
[    5.911214] sd 0:0:0:0: [sdb] Assuming drive cache: write through
[    5.951585]  sdb: sdb1
[    5.954816] sd 0:0:0:0: [sdb] Attached SCSI removable disk
2.- 4 seconds later the memory stick LED lights off and kernel reports:
[    9.082822] phy phy-ff770000.syscon:usb2-phy@e450.2: charger = USB_DCP_CHARGER
3.- After a minute the kernel reports:
[   71.666761] usb 5-1: USB disconnect, device number 2
It has been checked that, although the LED is off, VBUS is present.

If, instead, the dr_mode is changed to host and the phy-supply changed
accordingly, then it works. It has only been tested in host mode.

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 16:40:02 +02:00
Enric Balletbo i Serra
e6d237fdc1 arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs
As per binding documentation [1], the DWC3 core should have the "ref",
"bus_early" and "suspend" clocks. As explained in the binding, those
clocks are required for new platforms but not for existing platforms
before commit fe8abf332b ("usb: dwc3: support clocks and resets for
DWC3 core").

However, as those clocks are really treated as required, this ends with
having some annoying messages when the "rockchip,rk3399-dwc3" is used:

[    1.724107] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2
[    1.731893] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2
[    2.495937] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2
[    2.647239] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2

In order to remove those annoying messages, update the DWC3 hardware
module node and add all the required clocks. With this change, both, the
glue node and the DWC3 core node, have the clocks defined, but that's
not really a problem and there isn't a side effect on do this. So, we
can get rid of the annoying get clk error messages.

[1] Documentation/devicetree/bindings/usb/dwc3.txt

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 14:41:38 +02:00
Leonidas P. Papadakos
c9a8af804d arm64: dts: rockchip: enable rk3328 watchdog clock
Add the missing clock property for the watchdog on rk3328.

Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
[set wdt node to always enabled, as it is not board-specific]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 12:17:48 +02:00
Vivek Unune
3222bcf5f1 arm64: dts: rockchip: Add support for Hugsun X99 TV Box
Add devicetree support for Hugsun X99 TV Box based on RK3399 SoC

Tested with LibreElec running kernel v5.1.2.
Following peripherals tested and work:

Peripheral works:
- UART2 debug
- eMMC
- USB 3.0 port
- USB 2.0 port
- sdio, sd-card
- HDMI
- Ethernet
- WiFi/BT

Not tested:
- Type-C port
- OPTICAL
- IR

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 00:36:15 +02:00
Daniel Lezcano
cd21c54ad9 arm64: dts: rockchip: Define values for the IPA governor for rock960
Currently the default thermal values for the rk3399-rock960 board is
inherited from the generic definition in rk3399.dtsi.

In order to ensure the rock960 has more room for througput before
being capped by the thermal framework and is correctly supported by
the IPA governor, let's define the power values and the right trip
points for better performances:

 - sustainable power is tested to be 1550mW

 - increase the first mitigation point to 75°C in order to get better
   performances

 - the first trip point is 65°C in order to let the IPA to collect
   enough data for the PID regulation when it reaches 75°C

 - restrict the cooling device to the big CPUs as the little CPUs
   contribution to the heating effect can be considered negligible

The intelligent power allocator PID coefficient to be set in sysfs
are:

    k_d: 0
    k_po: 79
    k_i: 10
    k_pu: 50

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 00:26:04 +02:00
Daniel Lezcano
95f231f801 arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi
Currently the common thermal zones definitions for the rk3399 assumes
multiple thermal zones are supported by the governors. This is not the
case and each thermal zone has its own governor instance acting
individually without collaboration with other governors.

As the cooling device for the CPU and the GPU thermal zones is the
same, each governors take different decisions for the same cooling
device leading to conflicting instructions and an erratic behavior.

As the cooling-maps is about to become an optional property, let's
remove the cpu cooling device map from the GPU thermal zone.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 00:24:29 +02:00
Jianqun Xu
587b4ee24f arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
talk to NPU part inside SoC.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 00:22:45 +02:00
Peter Geis
393f3875c3 arm64: dts: rockchip: improve rk3328-roc-cc rgmii performance.
Currently the rk3328-roc-cc ethernet is enabled using "snps,force_thresh_dma_mode".
While this works, the performance leaves a lot to be desired.
A previous attempt to improve performance used "snps,txpbl = <0x4>".
This also allowed networking to function, but performance varied between boards.

This patch takes that one step further.
Set txpbl and rxpbl to 0x4.
This can also be accomplished with "snps,pbl =<0x4>" which affects both.
Also set "snps,aal" which forces address aligned DMA mode.

Fixes: 4bc4d6013b (arm64: dts: rockchip: fix rk3328-roc-cc gmac2io stability issues)
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Leonidas P. Papadakos <papadakospan@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 00:22:13 +02:00
Nick Xie
c2aacceedc arm64: dts: rockchip: Add support for Khadas Edge/Edge-V/Captain boards
Add devicetree support for Khadas Edge/Edge-V/Captain boards.
Khadas Edge is an expandable Rockchip RK3399 board with goldfinger.
Khadas Captain is the carrier board for Khadas Edge.
Khadas Edge-V is a Khadas VIM form factor Rockchip RK3399 board.

Signed-off-by: Nick Xie <nick@khadas.com>
[edge-captain and edge-v contain different components that are supposed
 to get added in future patches, so should stay separate while looking
 somewhat similar right now]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-14 15:59:35 +02:00
Ezequiel Garcia
549dcdafe7 arm64: dts: rockchip: Enable HDMI audio on Rock Pi
This commit enables the hdmi-sound device needed to have
audio over HDMI on the Rock Pi board.

Fixes: 1b5715c602 ("arm64: dts: rockchip: add ROCK Pi 4 DTS support")
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-14 11:19:32 +02:00
Akash Gajjar
45fa7c3838 arm64: dts: rockchip: add WiFi+BT support on ROCK Pi4 board
Rock Pi 4 has a on board AP6256 WiFi/BT Module. enable wifi and bluetooth
support on Rock Pi 4 board.

Signed-off-by: Akash Gajjar <akash@openedev.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-04 15:38:54 +02:00
Helen Koike
c432a29d3f arm64: dts: rockchip: fix isp iommu clocks and power domain
isp iommu requires wrapper variants of the clocks.
noc variants are always on and using the wrapper variants will activate
{A,H}CLK_ISP{0,1} due to the hierarchy.

Tested using the pending isp patch set (which is not upstream
yet). Without this patch, streaming from the isp stalls.

Also add the respective power domain and remove the "disabled" status.

Refer:
 RK3399 TRM v1.4 Fig. 2-4 RK3399 Clock Architecture Diagram
 RK3399 TRM v1.4 Fig. 8-1 RK3399 Power Domain Partition

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-04 15:35:19 +02:00