Commit Graph

258 Commits

Author SHA1 Message Date
Christian König
2858c00d28 drm/radeon: fix halting UVD
Removing the clock/power or resetting the VCPU can cause
hangs if that happens in the middle of a register write.

Stall the memory and register bus before putting the VCPU
into reset. Keep it in reset when unloading the module or
suspending.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:11 -04:00
Alex Deucher
1294d4a36d drm/radeon: add a module parameter to disable aspm
Can cause hangs when enabled in certain motherboards.
Set radeon.aspm=0 to disable aspm.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-17 14:52:46 -04:00
Alex Deucher
54e2e49ce2 drm/radeon: add fault decode function for cayman/TN (v2)
Helpful for debugging GPUVM errors as we can see what
hw block and page generated the fault in the log.

v2: simplify fault decoding

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2013-07-14 10:11:28 -04:00
Alex Deucher
c6cf7777a3 drm/radeon: set default clocks for SI when DPM is disabled
Fix patching of vddc values for SI and enable manually forcing
clocks to default levels as per NI.

This improves the out of the box performance with SI asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:08:54 -04:00
Alex Deucher
0124853eb1 drm/radeon/aruba: disable additional rlc features
They cause problems with dynamic clocking.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:29 -04:00
Alex Deucher
7178d2a642 drm/radeon/dpm: save some display parameters for DPM
Required for SI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 19:16:36 -04:00
Alex Deucher
8ba104637b drm/radeon: enable additional power gating features on trinity
TN has some additional powergating features beyond what is
supported on ON/LN.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 19:16:28 -04:00
Alex Deucher
f52382d73e drm/radeon: add support for ASPM on evergreen asics
Enables PCIE ASPM (Active State Power Management) on
evergreen-cayman asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 19:16:27 -04:00
Alex Deucher
d70229f704 drm/radeon/kms: add dpm support for trinity asics
This adds dpm support for trinity asics.  This includes:
- clockgating
- powergating
- dynamic engine clock scaling
- dynamic voltage scaling

set radeon.dpm=1 to enable it.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 19:15:45 -04:00
Alex Deucher
dc50ba7f9a drm/radeon/kms: add dpm support for evergreen (v4)
This adds dpm support for evergreen asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching (requires additional acpi support)

Set radeon.dpm=1 to enable.

v2: reduce stack usage, rename ulv struct
v3: fix thermal interrupt check notices by Jerome
v4: fix state enable

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 19:15:22 -04:00
Alex Deucher
cf0cfdd7a7 drm/radeon/kms: fix up dce4/5 display watermark calc for dpm
Calculate the low and high watermarks based on the low and high
clocks for the current power state.  The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:22 -04:00
Alex Deucher
2948f5e6c2 drm/radeon: properly set up the RLC on ON/LN/TN (v3)
This is required for certain advanced functionality.

v2: save/restore list takes dword offsets
v3: rebase on gpu reset changes

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:18 -04:00
Alex Deucher
138e4e16f0 drm/radeon/kms: move ucode defines to a separate header
Avoids confusion and duplication.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:17 -04:00
Alex Deucher
ff82bbc4d5 drm/radeon/kms: add accessors for RCU indirect space
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:14 -04:00
Adis Hamzić
e49f3959a9 radeon: Fix system hang issue when using KMS with older cards
The current radeon driver initialization routines, when using KMS, are written
so that the IRQ installation routine is called before initializing the WB buffer
and the CP rings. With some ASICs, though, the IRQ routine tries to access the
GFX_INDEX ring causing a call to RREG32 with the value of -1 in
radeon_fence_read. This, in turn causes the system to completely hang with some
cards, requiring a hard reset.

A call stack that can cause such a hang looks like this (using rv515 ASIC for the
example here):
 * rv515_init (rv515.c)
 * radeon_irq_kms_init (radeon_irq_kms.c)
 * drm_irq_install (drm_irq.c)
 * radeon_driver_irq_preinstall_kms (radeon_irq_kms.c)
 * rs600_irq_process (rs600.c)
 * radeon_fence_process - due to SW interrupt (radeon_fence.c)
 * radeon_fence_read (radeon_fence.c)
 * hang due to RREG32(-1)

The patch moves the IRQ installation to the card startup routine, after the ring
has been initialized, but before the IRQ has been set. This fixes the issue, but
requires a check to see if the IRQ is already installed, as is the case in the
system resume codepath.
I have tested the patch on three machines using the rv515, the rv770 and the
evergreen ASIC. They worked without issues.

This seems to be a known issue and has been reported on several bug tracking
sites by various distributions (see links below). Most of reports recommend
booting the system with KMS disabled and then enabling KMS by reloading the
radeon module. For some reason, this was indeed a usable workaround, however,
UMS is now deprecated and disabled by default.

Bug reports:
https://bugzilla.redhat.com/show_bug.cgi?id=845745
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/561789
https://bbs.archlinux.org/viewtopic.php?id=156964

Signed-off-by: Adis Hamzić <adis@hamzadis.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-06-03 10:17:54 -04:00
Kleber Sacilotto de Souza
7e0e419637 radeon: use max_bus_speed to activate gen2 speeds
radeon currently uses a drm function to get the speed capabilities for
the bus, drm_pcie_get_speed_cap_mask. However, this is a non-standard
method of performing this detection and this patch changes it to use
the max_bus_speed attribute.

From: Lucas Kannebley Tavares <lucaskt@linux.vnet.ibm.com>
Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-29 12:36:12 -04:00
Alex Deucher
5153550ad7 drm/radeon: don't touch DCE or VGA regs on Hainan (v3)
Hainan has no display hardware:
- no DCE (crtc, uniphy, dac, etc.)
- no VGA

v2: fix bios fetch
v3: fix interrupts

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2013-05-20 12:09:35 -04:00
Niels Ole Salscheider
fc98603454 drm/radeon: Fix VRAM size calculation for VRAM >= 4GB
Add ULL prefix to avoid overflow.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-05-20 10:44:57 -04:00
Christian König
facd112d13 drm/radeon: consolidate UVD clock programming
Instead of duplicating the code over and over again, just use a single
function to handle the clock calculations.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-02 10:09:48 -04:00
Alex Deucher
d4788db30a drm/radeon/evergreen: add support for golden register init
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-23 18:03:56 -04:00
Christian König
4ed108352d drm/radeon: put UVD PLLs in bypass mode
Just power down the PLL when we get a VCLK or DCLK of zero.
Enabling the bypass mode early should also allow us to
switch UVD clocks on the fly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-22 10:39:16 -04:00
Alex Deucher
abf1457bbb drm/radeon: disable the crtcs in mc_stop (evergreen+) (v2)
Just disabling the mem requests should be enough, but
that doesn't seem to work correctly on efi systems.

May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=57567
https://bugs.freedesktop.org/show_bug.cgi?id=43655
https://bugzilla.kernel.org/show_bug.cgi?id=56441

v2: blank displays first, then disable.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-04-22 10:39:10 -04:00
Alex Deucher
968c01664c drm/radeon: properly lock disp in mc_stop/resume for evergreen+
Need to wait for the new addresses to take affect before
re-enabling the MC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-04-22 10:39:08 -04:00
Alex Deucher
10257a6d83 drm/radeon: update wait_for_vblank for evergreen+
Properly wait for the next vblank region.  The previous
code didn't always wait long enough depending on the timing.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-04-22 10:39:07 -04:00
Alex Deucher
2e97be73e5 drm/radeon/evergreen+: don't enable HPD interrupts on eDP/LVDS
Avoids potential interrupt storms when the display is disabled.

May fix:
https://bugzilla.kernel.org/show_bug.cgi?id=56041

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-04-15 10:34:12 -04:00
Alex Deucher
cedb655a3a drm/radeon: handle broken disabled rb mask gracefully
If the disabled rb mask register is not properly initialized
program a sane default based on the number of RBs for the
asic.  This avoids a potential divide by 0 when calculating
the backend mask.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-11 09:22:04 -04:00
Alex Deucher
492d2b61b3 drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT
Avoid confusion with the *REG32_P mask macro.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:40 -04:00
Christian König
9a21059dc4 drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-04-09 10:31:39 -04:00
Alex Deucher
a8b4925c79 drm/radeon: add set_uvd_clocks callback for evergreen
v2: remove unneeded register definitions

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:36 -04:00
Alex Deucher
23d33ba32b drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4)
v2: write clk registers only once!
v3: update cg scratch register properly
v4: add TN support

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:35 -04:00
Christian König
f2ba57b5ea drm/radeon: UVD bringup v8
Just everything needed to decode videos using UVD.

v6: just all the bugfixes and support for R7xx-SI merged in one patch
v7: UVD_CGC_GATE is a write only register, lockup detection fix
v8: split out VRAM fallback changes, remove support for RV770,
    add support for HEMLOCK, add buffer sizes checks

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:33 -04:00
Alex Deucher
d808fc8829 drm/radeon: skip MC reset as it's probably not hung
The MC is mostly likely busy (e.g., display requests), not hung
so no need to reset it.  Doing an MC reset is tricky and not
particularly reliable.  Fixes hangs in certain cases.

Reported-by: Josh Boyer <jwboyer@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-07 12:58:58 -05:00
Alex Deucher
7ae764b11e drm/radeon: fix multi-head power profile stability on BTC+ asics
vddci needs to track mclk for multi-head.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-02-20 08:51:10 -05:00
Alex Deucher
24178ec42b drm/radeon: don't reset the MC on IGPs/APUs
The MC isn't part of the GPU per se.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:58 -05:00
Alex Deucher
123bc1832c drm/radeon: use the reset mask to determine if rings are hung
fetch the reset mask and check if the relevant ring flags
are set to determine whether the ring is hung or not.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:57 -05:00
Alex Deucher
b21b6e7aab drm/radeon: halt engines before disabling MC (evergreen)
It's better to halt the engines before we disable the MC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:55 -05:00
Alex Deucher
168757ea85 drm/radeon: use status regs to determine what to reset (cayman)
When we attempt the reset the GPU, look at the status registers
to determine what blocks need to be reset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:53 -05:00
Alex Deucher
a65a4369f7 drm/radeon: use status regs to determine what to reset (evergreen)
When we attempt the reset the GPU, look at the status registers
to determine what blocks need to be reset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:53 -05:00
Alex Deucher
187e359311 drm/radeon: rework GPU reset on cayman/TN
Update the code to better match the recommended
programming sequence for soft reset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:51 -05:00
Alex Deucher
b7630473de drm/radeon: rework GPU reset on evergreen
Update the code to better match the recommended
programming sequence for soft reset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:50 -05:00
Alex Deucher
410a3418a8 drm/radeon: add a bios scratch asic hung helper
Used by all asic families from r600+.
Flag for the vbios and later instances of the driver
that the GPU is hung.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:49 -05:00
Jerome Glisse
0fcb6155cb radeon/kms: cleanup async dma packet checking
This simplify and cleanup the async dma checking.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:47 -05:00
Alex Deucher
ed39fadd6d drm/radeon/evergreen+: wait for the MC to settle after MC blackout
Some chips seem to need a little delay after blacking out
the MC before the requests actually stop.

May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=56139
https://bugs.freedesktop.org/show_bug.cgi?id=57567

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-01-31 09:03:22 -05:00
Alex Deucher
f7eb973008 drm/radeon: fix backend map setup on 1 RB sumo boards
Need to adjust the backend map depending on which
RB is enabled.

Fixes:
https://bugzilla.redhat.com/show_bug.cgi?id=892233

Reported-by: Mikko Tiihonen <mikko.tiihonen@iki.fi>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-01-30 13:57:40 -05:00
Christopher Staite
bb588820ef drm/radeon: fix MC blackout on evergreen+
Force the crtc mem requests on/off immediately rather
than waiting for the double buffered updates to kick in.
Seems we miss the update in certain conditions.  Also
handle the DCE6 case.

Signed-off-by: Christopher Staite <chris@yourdreamnet.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-01-27 22:38:43 -05:00
Alex Deucher
19fc42ed99 drm/radeon: clear reset flags if engines are idle
Fixes a hard lock in the gpu reset code after the
rework for DMA support (0ecebb9e0d
"drm/radeon: switch to a finer grained reset for evergreen")
due to not bailing before the MC shutdown if the relevant engines
are idle.

Discussion:
http://lists.freedesktop.org/archives/dri-devel/2013-January/032985.html

Reported-by: Eldad Zack <eldad@fogrefinery.com>
Tested-by: Eldad Zack <eldad@fogrefinery.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-15 09:06:38 -05:00
Alex Deucher
0ecebb9e0d drm/radeon: switch to a finer grained reset for evergreen
No change in functionality as we currently set all the reset
flags.

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03 21:28:49 -05:00
Alex Deucher
4b681c2843 drm/radeon: fix typo in evergreen dma fence
SRBM write packet takes DW aligned registers.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03 19:54:34 -05:00
Jerome Glisse
64c56e8ce3 drm/radeon: reset dma engine on gpu reset (v2)
This try to reset the dma engine when performing gpu reset. Hopefully
bringing back the gpu dma engine in sane state.

v2: agd5f: fix dma reset on cayman/TN, add support for SI

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03 13:18:41 -05:00
Jerome Glisse
eaaa6983ab drm/radeon: print dma status reg on lockup (v2)
To help debug dma related lockup.

v2: agd5f: update SI as well

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03 13:18:41 -05:00