SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.
Cc: Chanho Min <chanho.min@lge.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dtc has new checks for SPI buses. Fix the warnings in node names.
arch/arm64/boot/dts/amd/amd-overdrive.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
Cc: Brijesh Singh <brijeshkumar.singh@amd.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Commit a7eb26392b ("arm64: dts: broadcom: Add reference to Compute
Module IO Board V3") adds the bcm2837-rpi-cm3-io3.dts file as a target
in the Makefile, rather than the .dtb name. This will skip the
generation of the .dtb file at compile time and will fail the dtbs_install
target.
Fixes: a7eb26392b ("arm64: dts: broadcom: Add reference to Compute Module IO Board V3")
Signed-off-by: Liviu Dudau <liviu@dudau.co.uk>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This branch adds changes for the Texas Instruments AM654 SoC. Included
changes are:
- Add uart nodes
- Change address cells and size-cells of interconnect tfrom 1 to 2
- Add secure proxy instance for main domain
- Add DMSC support
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Merge tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into next/dt
TI AM654 support for v4.20 merge window.
This branch adds changes for the Texas Instruments AM654 SoC. Included
changes are:
- Add uart nodes
- Change address cells and size-cells of interconnect tfrom 1 to 2
- Add secure proxy instance for main domain
- Add DMSC support
* tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
Signed-off-by: Olof Johansson <olof@lixom.net>
for 4.20, please pull the following:
- Stefan provides a reference to the Compute Module IO Board V3 such
that we can reference the arm counterpart and still build it for arm64
- Rob fixes I2C and SPI bus warnings which are going to show up with his
update to DTC scheduled for 4.20
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Merge tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux into next/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 4.20, please pull the following:
- Stefan provides a reference to the Compute Module IO Board V3 such
that we can reference the arm counterpart and still build it for arm64
- Rob fixes I2C and SPI bus warnings which are going to show up with his
update to DTC scheduled for 4.20
* tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Fix I2C and SPI bus warnings
arm64: dts: broadcom: Add reference to Compute Module IO Board V3
Signed-off-by: Olof Johansson <olof@lixom.net>
New boards are the px30 eval board and roc-rk3399-pc.
The rk3328 got support for the one gpio controlled via the general
register files and the rk3399 finally got its idle-states defined.
And finally fixes and improvements for firefly-rk3399 (wifi),
roc-rk3328-cc (sdmmc-uhs, io-domains), rk3328-rock64 (gpio-regulator
pin fix) and rk3399-sapphire (gpio-regulator pin fix, pmic pin fix
and type-c port supply).
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Merge tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
New soc support for the px30 quad-core Cortex-A35.
New boards are the px30 eval board and roc-rk3399-pc.
The rk3328 got support for the one gpio controlled via the general
register files and the rk3399 finally got its idle-states defined.
And finally fixes and improvements for firefly-rk3399 (wifi),
roc-rk3328-cc (sdmmc-uhs, io-domains), rk3328-rock64 (gpio-regulator
pin fix) and rk3399-sapphire (gpio-regulator pin fix, pmic pin fix
and type-c port supply).
* tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add type-c port supply on rk3399-sapphire board
arm64: dts: rockchip: fix vcc_host1_5v pin assign on rk3328-rock64
arm64: dts: rockchip: add WiFi module support for Firefly-RK3399
arm64: dts: rockchip: remove dvs2 pinctrl from pmic on rk3399-sapphire
arm64: dts: rockchip: Fix VCC5V0_HOST_EN on rk3399-sapphire
arm64: dts: rockchip: re-order vcc_sys on rk3399-sapphire
arm64: dts: rockchip: add missing vop properties for px30
arm64: dts: rockchip: Add idle-states to device tree for rk3399
arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc
arm64: dts: rockchip: add GRF GPIO controller to rk3328
arm64: dts: rockchip: add io-domain to roc-rk3328-cc
arm64: dts: rockchip: add PX30 evaluation board devicetree
arm64: dts: rockchip: add core dtsi file for PX30 SoCs
dt-bindings: rockchip: grf: add grf and pmugrf description for px30
arm64: dts: rockchip: add support for ROC-RK3399-PC board
Signed-off-by: Olof Johansson <olof@lixom.net>
Add devicetree support for HiKey970 development board which
based on Hi3670 SoC and is also one of the 96Boards Consumer
Edition and AI platform.
Only UART6 is enabled which is the default console required
by the 96Boards Consumer Edition Specification.
This patch has been tested on HiKey970 Board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add initial devicetree support for Hisilicon Hi3670 SoC which
is similar to Hi3660 SoC with NPU support.
This SoC has Octal core BigLittle CPUs in two clusters(4 * A53 & 4 * A73).
Only UART6 has been added for console support which is
pre configured by the bootloader. A fixed clock is sourcing
the UART6 which will get replaced by the clock driver when available.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The clocks property should either be present for all the CPUs of a
cluster or none. If these are present only for a subset of CPUs of a
cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add missing clocks property.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add TISCI compatible System controller for AM6 SoCs.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add secure proxy instance for Main domain
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add uart nodes for AM654 device tree components.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
register space. The size of the address space above the 4GB SoC address
space is 4GB. These address ranges will be used by CPU/DMA to access
the PCIe address space. In order to represent the address space above
the 4GB SoC address space and to represent the size of this address
space as 4GB, change address-cells and size-cells of interconnect to 2.
Since OSPI has similar need in MCU Domain Memory Map, change
address-cells and size-cells of cbass_mcu interconnect also to 2.
Fixes: ea47eed33a ("arm64: dts: ti: Add Support for AM654 SoC")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
dtc has new checks for I2C and SPI buses. Fix the warnings in node names
and unit-addresses.
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27"
arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27"
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@180000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@190000: node name for SPI buses should be 'spi'
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The order between "syscon" and "simple-mfd" is important because in these
particular cases, the node needs to be first a "simple-mfd" to expose
it's sub-nodes, and later on a "syscon" to permit other nodes to access
this register space through the "syscon" mechanism.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The r8a77965 has a single FDP1 instance.
Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- Device nodes with unit addresses are sorted by unit address,
- Device nodes without unit addresses and references are sorted
alphabetically.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Successfully tested on H3 ES1.0 and ES2.0, M3-W ES1.0, and M3-N ES1.0.
Even previously stubborn cards work fine. Transfer rates were >60MB/s.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device nodes for all MSIOF SPI controllers, incl. clocks, power
domains, and resets properties.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device node for the external SCIF_CLK, and describe the clock
inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2,
which can increase serial clock accuracy.
The presence of the SCIF_CLK crystal and its clock frequency depend on
the actual board.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Enhance patch description]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use the SoC-specific CPG/MSSR include file to allow future use of
R8A77990_CLK_* symbols.
Replace the hardcoded power domain indices by R8A77990_PD_* symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The comments describing the non-default switch settings to use SATA are
confusing: 'Off' refers to the switch position, not to the MD12 logic
value, while the parentheses suggest otherwise. Rephrase to fix this.
Fixes: bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: updated for a few new cases]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This is based on the existing KF device tree sources:
$ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly
to what was done for the r8a7796 with commit 41dbbf0c5b
("arm64: dts: r8a7796: Add FCPF and FCPV instances"),
commit 69490bc966 ("arm64: dts: renesas: r8a7796: Point
FDP1 via FCPF to IPMMU-VI0"), and commit cef942d0bd ("arm64:
dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0").
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1).
This work is based on similar work done on the R8A7796 SoC
by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1)
device tree.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds definitions for L2 cache for the Cortex-A53 CPU
cores (512 KiB in size, organized as 32 KiB x 16 ways), adds
Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57
+ 4 x Cortex-A53), and finally enables the performance monitor
unit for the Cortex-A53 cores on the R8A774A1 SoC.
Based on work done for r8a7796 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC.
Based on several similar patches of the R8A7796 device tree
by Geert Uytterhoeven <geert+renesas@glider.be>
and Simon Horman <horms+renesas@verge.net.au>.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>