Commit Graph

118 Commits

Author SHA1 Message Date
Rhyland Klein
a26f3963d9 arm64: tegra: Add gpio-keys nodes for Smaug
Add gpio-keys nodes for the volumn controls, lid switch, tablet mode and
power button.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
[treding@nvidia.com: use symbolic names for input types and codes]
[treding@nvidia.com: use wakeup-source instead of gpio-key,wakeup]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:25 +02:00
Laxman Dewangan
0e91ba42be arm64: tegra: Enable power and volume keys on Jetson TX1
Add a gpio-keys device tree node to represent the Power, Volume Up and
Volume Down keys found on Jetson TX1.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:24 +02:00
Jon Hunter
5d17ba6e63 arm64: tegra: Add support for Google Pixel C
Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based
upon Tegra210 SoC with 3 GiB of LPDDR4 RAM.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:19 +02:00
Sudeep Holla
81d22e89b4 arm64: tegra: Replace legacy *,wakeup property with wakeup-source
Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the
wakeup source, "wakeup-source" is the new standard binding.

This patch replaces all the legacy wakeup properties with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:38:15 +02:00
Thierry Reding
68cd8b2e27 arm64: tegra: Fix copy/paste typo in several DTS includes
The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.

Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:38:14 +02:00
Thierry Reding
be70771d4c arm64: tegra: Remove 0, prefix from unit-addresses
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:38:10 +02:00
Adam Buchbinder
ef769e3208 arm64: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-04 18:19:17 +00:00
Jon Hunter
43acf83166 ARM64: tegra: Add chosen node for tegra132 norrin
The NVIDIA bootloader, nvtboot, expects the "chosen" node to be present
in the device-tree blob and if it is not then it fails to boot the kernel.
Add the chosen node so we can boot the kernel on Tegra132 Norrin with the
nvtboot bootloader.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-01 12:20:11 -08:00
Thierry Reding
336f79c7b6 arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit support
The Jetson TX1 Development Kit is the successor of the Jetson TK1. The
Jetson TX1 is composed of the Jetson TX1 module (P2180) that connects to
the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel connected
via the P2597's display connector.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:25 +01:00
Thierry Reding
2e63405776 arm64: tegra: Add NVIDIA P2597 I/O board support
The NVIDIA P2597 I/O board is a carrier board for the Jetson TX1 module
and together they are also known as the Jetson TX1 Developer Kit. The
I/O board provides an RJ45 connector routed to the network adapter that
is part of the Jetson TX1 module. It exposes many other connectors such
as SATA, USB 3.0, HDMI, JTAG and PCIe, among others, as well. Dedicated
connectors allow display and camera modules to be attached. A full-size
SD slot is provided to extend storage beyond the 32 GiB of eMMC found
on the Jetson TX1 module.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:25 +01:00
Thierry Reding
9e71045f1b arm64: tegra: Add NVIDIA Jetson TX1 support
The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC
with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials.

It is typically connected to some I/O board (such as the P2597) that has
the connectors needed to hook it up to the outside world.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:24 +01:00
Thierry Reding
2cc85bd903 arm64: tegra: Add NVIDIA P2571 board support
The NVIDIA P2571 is an internal reference design that's very similar to
the P2371, but targetting different use-cases.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:24 +01:00
Thierry Reding
63023e95be arm64: tegra: Add NVIDIA P2371 board support
The NVIDIA P2371 is an internal reference design that uses a P2530
processor module hooked up to a P2595 I/O board and an optional display
module for a 1200x1920 MIPI DSI panel.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:23 +01:00
Thierry Reding
c24d2e13c6 arm64: tegra: Add NVIDIA P2595 I/O board support
The NVIDIA P2595 I/O board is used in several reference designs and has
the connectors to connect the P2530 compute module to the outside world.
It features a USB 3.0 network adapter, a USB 3.0 port, an HDMI port, a
SATA port, an audio codec, a microSD card slot and a display connector,
among others.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:23 +01:00
Thierry Reding
c552cca31c arm64: tegra: Add NVIDIA P2530 main board support
The NVIDIA P2530 is a processor module used in several reference designs
that features a Tegra210 SoC, 4 GiB of LPDDR4 RAM, 16 GiB eMMC and other
essentials. It is typically connected to some I/O board that provides
the connectors needed to hook it up to the outside world.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:22 +01:00
Thierry Reding
742af7e7a0 arm64: tegra: Add Tegra210 support
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired
with four Cortex-A53 cores in a switched configuration. It features a
GPU using the Maxwell architecture with support for DX11, SM4, OpenGL
4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware
accelerated en- and decoding of various video standards including
H.265, H.264 and VP8 at 4K resolutions and up to 60 fps.

Besides the multimedia features it also comes with a variety of I/O
controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.

Add a SoC-level device tree file that describes most of the hardware
available on the SoC. This includes only hardware for which a device
tree binding already exists or which is trivial to describe.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:21 +01:00
Thierry Reding
0f279ebdf3 arm64: tegra: Add NVIDIA Tegra132 Norrin support
Norrin is a Tegra132-based FFD used as reference platform within NVIDIA.

Based on work by Allen Martin <amartin@nvidia.com>

Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:21 +01:00
Thierry Reding
34b4f6d059 arm64: tegra: Add Tegra132 support
NVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124
but with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI
file for the SoC, which is mostly similar to the one for Tegra124.

Based on work by Allen Martin <amartin@nvidia.com>

Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:20 +01:00