DRA7 family of processors from Texas Instruments, have a hardware module
called IODELAYCONFIG Module which is expected to be configured. This
block allows very specific custom fine tuning for electrical
characteristics of IO pins that are necessary for functionality and
device lifetime requirements. IODelay module has it's own register space
with registers to configure various pins.
According to AM572x TRM SPRUHZ6E October 2014–Revised January 2016[1]
section 18.4.6.1 Pad Configuration, in addition to pinmuxing(MUXMODE),
when operating a pad in certain mode, Virtual/Manual IO Timing Mode must
also be configured to ensure that IO timings are met (DELAYMODE and
MODESELECT fields of pad's IODELAYCONFIG module register). According to
section 18.4.6.1.7 Isolation Requirements of above TRM, when
reprogramming MUXMODE, DELAYMODE, and MODESELECT fields, there is a
potential for a significant glitch on the corresponding IO. It is hence
recommended to do this with I/O isolation (which can only be done in
initial stages of bootloader). QSPI is one such module that requires
IODELAY configuration. So, this patch removes the pinmux for
QSPI for DRA74/DRA72 EVM as it needs to be done in bootloader (U-Boot)
and cannot be done in kernel.
Users should migrate to U-Boot v2016.05-rc1 or higher.
[1] http://www.ti.com/lit/ug/spruhz6e/spruhz6e.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The boards use a TI variant of the PCF8575 so specify that
in the compatible string.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As per the data sheet starting from SPRUHQ0H (Nov 2015 - Latest[1]),
VDD_CORE can vary from 0.85v to 1.15v for AVS class0. VDD GPU/DSP
et.al. can range from 0.85v to 1.25V with AVS class0
Since dynamic voltage scaling is disabled for DRA7/AM57xx SoCs for
all SoC rails other than MPU, the bootloader is responsible for
setting up the AVS class0 voltage, however, with wrong voltage machine
constraints in dtb, regulator framework will lower the voltage below
the required voltage levels for certain samples in production flow.
This can cause catastrophic failures which can be pretty hard to
identify.
Update board files which don't match required specification.
[1] http://www.ti.com/product/AM5728/datasheet/specifications#SPRT637-7340
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Doing so saves quite a bit of code in the driver.
For more information on the 'reserved-memory' bindings see:
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
Suggested-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This patch supplies the Mailbox Controller nodes. In order to
request channels, these nodes will be referenced by Mailbox
Client nodes.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
You'll notice that the voltage cell is populated with 0's. Voltage
information is very platform specific, even depends on 'cut' and
'substrate' versions. Thus it is left blank for a generic (safe)
implementation. If other nodes/properties are provided by the
bootloader, the ST CPUFreq driver will over-ride these generic
values.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
When compiled with "W=1", dtc complains: e.g.
"Warning (unit_address_vs_reg):
Node /soc/ipu@02800000/port@2/endpoint@0
has a unit name, but no reg property"
Endpoint nodes don't have a reg property, and the addresses
in their node names are ordinals without any special meaning
so remove them and swap them for semantic node names.
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Table 8 from MX6DL datasheet (IMX6SDLCEC Rev. 5, 06/2015):
http://cache.nxp.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf
states the following:
"LDO Output Set Point (VDD_ARM_CAP) = 1.125 V minimum for operation
up to 396 MHz."
So fix the entry by adding the 25mV margin value as done in the other
entries of the table, which results in 1.15V for 396MHz operation.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
198MHz is a valid operating point for mx6sx.
Add entries for VDD_ARM_CAP and VDD_SOC_CAP voltages for 198MHz according
to the imx6sx datahseet:
http://cache.nxp.com/files/32bit/doc/data_sheet/IMX6SXIEC.pdf
(a 25mV offset is added to the minimum allowed values for safety).
These values also match the ones from the NXP kernel.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adjust the VDD_ARM_CAP and VDD_SOC_CAP voltages according to
Table-11 from MX6UL datasheet:
http://cache.nxp.com/files/32bit/doc/data_sheet/IMX6ULCEC.pdf
(a 25mV offset is added to the minimum allowed values for safety).
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Application Notes 399 and 400 shares the same memory map and
features. Both are shipped with Cortex-M7 and have the same peripheral
as AN385/AN386, but with different location of PSRAM and Ethernet
controller.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Application Notes 385 and 386 shares the same memory map and features
except the CPU is used. AN385 is supplied with Cortex-M3 CPU and AN386
is supplied with Cortex-M4.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* Correct preset_lpj calculation which may lead to too short delays
* Correct handling of optional clocks on r8a7791 to restore
access to the serial port the porter board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXGEtmAAoJENfPZGlqN0++aYIP/RCANWvI9Z7VH/Y/NQ1f5t4Y
l4Uv1/dSuIHJq44z0sLMD5gmDVKqP1NnCncfkZabDXceGm9Fk3DlFxeLd+ahMN+B
dBtDpf1AA9Mr1AEoBrXjNimWSupvJalatqk3nWfLnjpGHQJOKTZCekikQb9WBA5t
l5r5Pvu/leRfyg/wi10F3hq0a2drKbIbFDOzh37L7al9cvZTnyVZNcchb/vlqZmt
kAi90crLUXvQ9eOw357kFBmigQF5r/fD0X3f5sFYyDlNldZg3chkyghiluiOcXDL
eEc6TdHNT/a9hixqpW/Z1BinpvFF+vIjfUZBW9wXTRz0t9EX5Pxr9wSXWEY4+hmp
DrI9eiEAbX8ltfjOo3Q7LgHstjZ6AJyk3CZJBWk8i2DLK5SEt6eum/BvKRmakTa+
DLe+SES+uUfg1d35WEqhqPeO7JEybPAVyto++NrCRSkPeDeO32+h2O6yEsMBqEKC
HFoV/V86Ufqq8MCiZkQBZJGNYqcTeKMiXzvte23tcAXXYmxMct5Z4HLCiFEM4paw
yyThG9VZofe4pt03u9XqiZjEu23AopMpM9xDpUjK3CKYq6uaJxNoJcgJC6TBbkmT
D7kdmhhlWCLeyr3pqblbqiWdK7Bx9B65aFhm/nilX0y4p3vvT46vMLvG4SgfFojv
Ybr9ICHZMaTxJ1V32fty
=k7qU
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC Fixes for v4.6
* Correct preset_lpj calculation which may lead to too short delays
* Correct handling of optional clocks on r8a7791 to restore
access to the serial port the porter board
This is a backmerge of v4.6 fixes, to avoid a merge conflict between 4.6
and our next/dt branch.
* tag 'renesas-fixes-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: timer: Fix preset_lpj leading to too short delays
Revert "ARM: dts: porter: Enable SCIF_CLK frequency and pins"
ARM: dts: r8a7791: Don't disable referenced optional clocks
Fix a typo on PIN_PD24 for UTXD2 and FLEXCOM4_IO3 which were
wrongly linked to PIN_PD23).
Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Fixes: 7f16cb676c ("ARM: at91/dt: add sama5d2 pinmux")
Cc: stable@vger.kernel.org # v4.4+
[nicolas.ferre@atmel.com: add commit message, changed subject]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add Western Digital My Book World Edition device tree based on
Oxford Semiconductor OX810SE SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Under the OX810SE, this same controller is used as "Reference Peripheral
Specification" Interrupt Controller, so add new compatible string to support
the Oxford Semiconductor OX810SE SoC Interrupt Controller.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The BA16 module has a PMIC that uses the WDOG_B output from iMX6 to
reset the system on a watchdog timeout. Configure the watchdog to assert
the external reset signal (WDOG_B) using fsl,ext-reset-output property.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Previously the LDB_DIx clocks could be specified in the ldb node. With
the ERR009219 errata fix applied, the ldb_di clocks now needs to be
specified in the clks node to ensure the clocks are setup early in the
boot process.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The default monitor that ships with B850v3 requires a 65MHz pixel clock.
65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the
LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx,
set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous
display on both LVDS and HDMI interface.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove ldb panel entry for the following reasons:
- The b850v3 has an onboard LVDS to DisplayPort converter (STDP4028). So
we should not limit the monitors that can be connected by hardcoding the
auo,b133htn01 1080p panel.
- The default resolution on the LVDS interface needs to be WXGA or less.
Otherwise when a 1080p monitor is connected to the HDMI port there is no
output on both the LVDS and HDMI ports since a single IPU on i.MX6 can
not handle two 1080p displays. With the panel entry removed from the
devicetree, drm driver defaults the resolution on LVDS interface to XGA.
Once in userspace, applications can set the desired resolution on LVDS
interface over IPU2 CRTC.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
to the clk-ti branch from the Linux clk tree for the ADPLL clock driver.
Otherwise things won't keep booting properly when we flip over to use
the clock driver instead of fixed clocks set up by the bootloader.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW2MN/AAoJEBvUPslcq6VzVqEP/A2qxFhMYyf/q0Za54RNRHjj
iHbpxmfPUrFIGO/IQqkk7bl5Ufgs+L+uW+mjoe0CvIYGEoVDY/cfe3AZW734cGMO
rLbs3CovoHst2UTZbcKVRs/QjkN+R9nvowvvqK87vSbpAbMX7pRrEcfZSN77T4ej
vRbtRyD0msNCm8s0TgdpQ6ObK0GHmfqtq3GFA/g5Rs5m1X7h9PaD+PWUsVDugKyM
9bEmGZSyOaRN5qGrOX/PTTKK3OiCOSJXB/8tnRgNW7DaISop+KJwxzMhBHyx2iKP
JaD5lDJk/ArE+4Za0FmSpug8muUHLHH+htCu76uU6qi/s7+q8g9UR9ewzfLg7/rG
wYl8IwDBVxWbi5PLnHPRrghGheEkM2ykiqEp5DqlZ1B7vfGv4Wl/3ZxiL1ZO5FZv
jre1yHm5sguLCtA6BErWi69SCI3rpi4GrDQuYnlAbg9ABRH+YBVZ+3lCqtBVyh6J
5yHexIELEEOUHHT2KLPNi7HexzK6xtMpsh4QlP1Yxt2o6dVI2LmTS+oKtU6QAjSn
WE5pbLd9XZUBaDO4jw3T01edhGVpf2OxmtGSOd/ptF5JjZoDA2Kg+NcDE0eTPL72
v7yVlNVU3g8PlD1EfRENi/KL0K4GLNq3eT2WCFQYp/nYuN1dVkk5xraEv3w7N0iZ
vGlh9twbt7VvjiGoImcF
=2Lew
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.6/dt-ti81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Enable dm814x and dra62x clock driver. This branch has a dependency
to the clk-ti branch from the Linux clk tree for the ADPLL clock driver.
Otherwise things won't keep booting properly when we flip over to use
the clock driver instead of fixed clocks set up by the bootloader.
* tag 'omap-for-v4.6/dt-ti81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Add clocks for dm814x ADPLL
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Support for external expansion bus useful for additional hardware
e.g. LogicTile Express daughterboards (Brian Starkey)
2. Fix for device node name unit-address presence/absence warnings
enabled in recently update DTC (Sudeep Holla)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJXHe2CAAoJEABBurwxfuKYi6wP/AwNdbuZV/sOykYUeiyajQNm
mwzggzCTzZPta2vIUoG/9mI0XwfMi6d7oQLKIACb94kZzw9GpXkOxEskLhWYdOA/
9iHv547OKzZrZuduP0TqXhIVff7bKI/8E/vSwwNvYoXjVJ33npyMcb68zzWDTVk5
OmYBQC8klyuDxV/yGj8yWwx0Oica2C/KF1QiO0WkZSpnJu7aGq5ZBIZDz+YFm3CR
IToSe1rQPQurIZ07yE4wBuvD8U0FYA8QSw4TaHSpqNFb3t/68i4jWhcJZoAZSlcm
b+9snmKpuqEPBJfJLVMx2mi7OyqsQdbmW1NLC6VC/Fh57/v0Z+sKskAVjvXa7y8L
iBrG7JT1lL5JBR1/ydIbtlTqheP8SH62Q6fAiUGM1Lhyj2FH8w6Oi6bAwRCyiRQB
3bV+eKAdtLexO9PNAGFZTVC2T49/CNykOsFh3uBZXmNwG2LdBHfocgCTfFxs+Ceb
3BHjxfRDivXq8GnkPk/MPNNvmkJAOJ2FH7x+1Lr9SaiRfePNoCHyrow7IkcNPi0U
wZN8jK0hyahMoF9k4OL+TOM21qNsQvDsOtGpyRkzNMJGWawb59oSpgfPZHFLY9p1
bypdAA6nWVn+yBdB6w7quVq4bBcKY2xbwv3fGasT5zYWUZG30tLjFoZcSCHDJ4IM
xC4rJ+jCPOvXlWDanEQa
=CN/A
-----END PGP SIGNATURE-----
Merge tag 'vexpress-for-v4.7/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
Merge "ARMv7 Vexpress updates/fixes for v4.7" from Sudeep Holla:
1. Support for external expansion bus useful for additional hardware
e.g. LogicTile Express daughterboards (Brian Starkey)
2. Fix for device node name unit-address presence/absence warnings
enabled in recently update DTC (Sudeep Holla)
* tag 'vexpress-for-v4.7/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress: Add external expansion bus to DT
ARM: dts: vexpress: fix node name unit-address presence warnings
* Configure NMI key as wakeup source in DT of kzm9g board
* Add SDHI support to DT of gose board
* Add support of UHS-I SDR-50 for SDHI to DT of r8a7790 SoC
* Correct interrupt type for ARM TWD in DT of r8a7779 and sh73a0 SoCs
* Add IIC support to DT of r8a7794 SoC
* Add CAN support to DT of r8a7793 and r8a7794 SoCs
* Add SCIF2 support to r8a7790 device tree
* Use CAN, JPU and USB3.0 fallback compatibility string
in DT of r8a7791 and r8a7790 SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXHZwbAAoJENfPZGlqN0++3nUP/3sPtsfjE9v40DBnhiuO6nDA
W3IW1mwlisw+R/HN8mkFun7OYDWjiY9dAjR7tHhKCxapztIxbWMG2pWgKmTKevIR
m7RY8VCOWQIKDhpBEAalqxhpu5WAq5/Dfeyf2CF+CnPCnZA+CUsVS+gLdJRz5R0e
yP5c9n9EaLMs/1IODQlgySQcdYrfal/SaRcsNDwnZZIH4L98DewhYAcXb7wYVL3Y
n1bd4CAcHmKXk+rjauFnynXSCU/BIOEf+FiUlyHPgDAk3VrIAB9aos7C0S+lSCtr
4v7q0G0fizaeImtiDW2XrNIvBinbVb8vRWN4Q7hgPqDqJAxaPIa9Uy8QFf8Y2vZ7
Ki0VAtq0JFoH78CdzNMD7tHzOUMOgTio7mnvK66JAG/KtWVthBdGDMRd3sCl5wnQ
Eepe8hEWBPMZF8XibIJ7HUpVFGDmBwrQ5hawsO3vYG6qiR/Cakc+8NLjMbx+y3AN
j1LZL3uHWfNC/798MovmpMswhVFuP6MTdF2HTICwlC8rHCPW2J20w4F0HBiMZcSE
KUsid/YhFMuILkMEDBLfnqtmrGgF4ugrVusxFqzl6nn7F3eiguYv4cq3CmBosK5d
Lp2frlfUjSWjGcpr4J0+qXOwjZljCu+1tDeTlRAEHSuPyQXm3vNUYzuxGGgQKWOg
Fs29CVOaPN5+QoFRv+O9
=vStA
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC DT Updates for v4.7" from Simon Horman:
* Configure NMI key as wakeup source in DT of kzm9g board
* Add SDHI support to DT of gose board
* Add support of UHS-I SDR-50 for SDHI to DT of r8a7790 SoC
* Correct interrupt type for ARM TWD in DT of r8a7779 and sh73a0 SoCs
* Add IIC support to DT of r8a7794 SoC
* Add CAN support to DT of r8a7793 and r8a7794 SoCs
* Add SCIF2 support to r8a7790 device tree
* Use CAN, JPU and USB3.0 fallback compatibility string
in DT of r8a7791 and r8a7790 SoCs
* tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
ARM: dts: gose: Enable SDHI controllers
ARM: dts: r8a7793: Add SDHI controllers
ARM: dts: r8a7790: fix max-frequency for SDHI
ARM: dts: kzm9g: Configure NMI key as wake-up source
ARM: dts: r8a7790: lager: Enable UHS-I SDR-50
ARM: dts: r8a7790: Set maximum frequencies for SDHI clocks
ARM: dts: r8a7791: Use USB3.0 fallback compatibility string
ARM: dts: r8a7790: Use USB3.0 fallback compatibility string
ARM: dts: r8a7779: Correct interrupt type for ARM TWD
ARM: dts: sh73a0: Correct interrupt type for ARM TWD
ARM: dts: r8a7794: Add IIC nodes
ARM: dts: r8a7794: add IIC clocks
ARM: dts: r8a7793: add CAN nodes to device tree
ARM: dts: r8a7793: add CAN clocks to device tree
ARM: dts: r8a7794: add CAN nodes to device tree
ARM: dts: r8a7794: add CAN clocks to device tree
ARM: dts: r8a7790: use fallback can compatibility string
ARM: dts: r8a7791: use fallback can compatibility string
ARM: dts: r8a7790: Add SCIF2 device node
ARM: dts: r8a7790: Add SCIF2 clock
...
Fix off by one error in da850 device tree in
the number of INTC interrupts.
Signed-off-by: David Lechner <david@lechnology.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[nsekhar@ti.com: commit message update]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Disable mdio and eth0 in da850.dtsi file. All other
devices are disabled by default and not all boards
will use these devices, so these should be disabled too.
da850-evm.dtb already had status = "okay" for these devices.
da850-enbw-cmc.dts did not, so they were added.
Signed-off-by: David Lechner <david@lechnology.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[nsekhar@ti.com: commit description updates]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add AUXDATA needed to match the device-tree node for spi0 to the
non-device-tree clock.
Signed-off-by: David Lechner <david@lechnology.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[nsekhar@ti.com: commit description updates]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The VExpress development platform has an external expansion bus which
can be used for additional hardware (e.g. LogicTile Express daughter
boards).
Add this bus to the VExpress CoreTile device-trees.The bus is described
for a CoreTile occupying site 1.
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Commit b993734718 ("scripts/dtc: Update to upstream version 53bf130b1cdd")
added warnings on node name unit-address presence/absence mismatch in
the device trees.
This patch fixes those warning on all the vexpress platforms where
unit-address is present in node name while the reg/ranges property is
not present.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Enable the S/PDIF transmitter present on the Cubietruck.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
In order to be standard to manage for rockchip SoCs, move the thermal
data into rk3288 dtsi, we needn't to add a new file for thermal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Includes regulator and pin assignments.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The wrong values come from an old datasheet (H2 v0.6). Anything later
has the fixed value of 195MHz (H2 v0.7 up to Gen2-common V2.0).
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
