2 Commits

Author	SHA1	Message	Date
Krzysztof Adamski	111f2b8732	pinctrl: sunxi: H3 requires irq_read_needs_mux ... It seems that on H3, just like on A10, when GPIOs are configured as external interrupt data registers does not contain their value. When value is read, GPIO function must be temporary switched to input for reads. Signed-off-by: Krzysztof Adamski <k@japko.eu> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>	2016-02-11 14:29:13 +01:00
Jens Kuske	e87623cb3b	pinctrl: sunxi: Add H3 PIO controller support ... The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>	2015-12-11 10:15:33 +01:00