267 Commits

Author	SHA1	Message	Date
Linus Torvalds	20f9449656	A few clk driver fixes ... - Don't expose the SiFive clk driver on non-RISCV architectures - Fix some bits describing clks in the imx8mm driver - Always call clk domain code in the TI driver so non-legacy platforms work -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlzvBroRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSXt1hAAjab8EFP2qRzqoZKEns5Zu4H9htPbLvco oWJAcaLgmeF8MV/pK+HmGkqFJnAOBkTf+2NoAkz5qcRghGBacbxfmJAm0zLNoMQ4 JBGowtpQhio5u52UMNIyVND7TeNdRaNihe1osPpSoFj0zFzwUFIv2aK8Im6gRmWY uDNkJdib5DsVURiPa2kqglLLWOpJl5X4tXYpu0i88pToWhiOK9b3ngh1R/VTVYic H4vvo6XGClF1CSqpKpwCeUCxyuAWHT+qCbE3SHbEJJcon0QzEFTW635NMLbmCNMa oNpqLnPtx+IELvLeTeLyeKKsb9HedgllmqiGp2szC5jj8y+T4T1O45WhCl0mj2TV bS0ANcrpxy+edhH0qGEOAp4pK41WO5vEWiQbJBLm6ge9jtLuir/GP91tAcAdBDRT DOCGGhmYythMo0OETQ5ZlpP/TvgM9uCPRmg0OTVzZHgosG7u2TZgH5/TzoIlnNRE bowpTfKYPTTZ8ZhNqhqmNll8CV/xdmbdTW8QAgnOuj9Kv76IyMGZfxQIbUDbdUox cgVFWa+S6HxBUddX5GPsDqm0voE4bhYxBqb6B0NuopjMHYRqphyY5Icp4qQMhbyC MzcEEbfGj0GDtDLXEpDFOASWHPpBV/6g6xA1hJyhXPWBl3oEWPM1nL4hIADMx41O Wzg6MPVeqWU= =gbSJ -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk driver fixes from Stephen Boyd: - Don't expose the SiFive clk driver on non-RISCV architectures - Fix some bits describing clks in the imx8mm driver - Always call clk domain code in the TI driver so non-legacy platforms work * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: ti: clkctrl: Fix clkdm_clk handling clk: imx: imx8mm: fix int pll clk gate clk: sifive: restrict Kconfig scope for the FU540 PRCI driver	2019-05-30 16:33:37 -07:00
Peng Fan	b3fddd5b10	clk: imx: imx8mm: fix int pll clk gate ... To Frac pll, the gate shift is 13, however to Int PLL the gate shift is 11. Cc: <stable@vger.kernel.org> Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-21 11:42:44 -07:00
Thomas Gleixner	8b9844d7e8	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 21 ... Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 2 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154042.615184352@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>	2019-05-21 11:28:47 +02:00
Thomas Gleixner	1621633323	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1 ... Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option [no]_[pad]_[ctrl] any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 176 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154040.652910950@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>	2019-05-21 11:28:39 +02:00
Stephen Boyd	62e59c4e69	clk: Remove io.h from clk-provider.h ... Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-15 13:21:37 -07:00
Stephen Boyd	f6111b9d79	Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next ... - Remove clk_readl() and introduce BE versions of basic clk types * clk-doc: clk: Drop duplicate clk_register() documentation clk: Document and simplify clk_core_get_rate_nolock() clk: Remove 'flags' member of struct clk_fixed_rate clk: nxp: Drop 'flags' on fixed_rate clk macro clk: Document __clk_mux_determine_rate() clk: Document CLK_MUX_READ_ONLY mux flag clk: Document deprecated things clk: Collapse gpio clk kerneldoc * clk-more-critical: clk: highbank: Convert to CLK_IS_CRITICAL * clk-meson: (21 commits) clk: meson: axg-audio: add g12a support clk: meson: axg-audio: don't register inputs in the onecell data clk: meson: axg_audio: replace prefix axg by aud dt-bindings: clk: axg-audio: add g12a support clk: meson: meson8b: add the video decoder clock trees clk: meson: meson8b: add the VPU clock trees clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2 clk: meson: meson8b: use a separate clock table for Meson8m2 dt-bindings: clock: meson8b: export the video decoder clocks clk: meson-g12a: add video decoder clocks dt-bindings: clock: meson8b: export the VPU clock clk: meson-g12a: add PCIE PLL clocks dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL dt-bindings: clock: meson8b: drop the "ABP" clock definition clk: meson: g12a: add cpu clocks dt-bindings: clk: g12a-clkc: add VDEC clock IDs dt-bindings: clock: axg-audio: unexpose controller inputs dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id ... * clk-basic-be: clk: core: replace clk_{readl,writel} with {readl,writel} clk: core: remove powerpc special handling powerpc/512x: mark clocks as big endian clk: mux: add explicit big endian support clk: multiplier: add explicit big endian support clk: gate: add explicit big endian support clk: fractional-divider: add explicit big endian support clk: divider: add explicit big endian support	2019-05-07 11:44:42 -07:00
Stephen Boyd	2ed3b9103a	Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next ... - Qualcomm QCS404 CDSP clk support - Qualcomm QCS404 Turing clk support - Mediatek MT8183 clock support - Mediatek MT8516 clock support - Milbeaut M10V clk controller support * clk-renesas: clk: renesas: rcar-gen3: Remove unused variable clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value clk: renesas: r8a77980: Fix RPC-IF module clock's parent clk: renesas: rcar-gen3: Rename DRIF clocks clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC clk: renesas: rcar-gen3: Correct parent clock of HS-USB clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI clk: renesas: r8a774c0: Add Z2 clock clk: renesas: r8a77990: Add Z2 clock clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents math64: New DIV64_U64_ROUND_CLOSEST helper clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r9a06g032: Add missing PCI USB clock clk: renesas: r7s9210: Always use readl() clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() * clk-qcom: clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998 clk: qcom: Add QCS404 TuringCC clk: qcom: branch: Add AON clock ops dt-bindings: clock: Introduce Qualcomm Turing Clock controller clk: qcom: gcc-qcs404: Add CDSP related clocks and resets * clk-mtk: clk: mediatek: add clock driver for MT8516 dt-bindings: mediatek: apmixedsys: add support for MT8516 dt-bindings: mediatek: infracfg: add support for MT8516 dt-bindings: mediatek: topckgen: add support for MT8516 clk: mediatek: Allow changing PLL rate when it is off clk: mediatek: Add MT8183 clock support clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add dt-bindings for MT8183 clocks dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data clk: mediatek: Add new clkmux register API clk: mediatek: Disable tuner_en before change PLL rate * clk-milbeaut: clock: milbeaut: Add Milbeaut M10V clock controller dt-bindings: clock: milbeaut: add Milbeaut clock description * clk-imx: clk: imx: correct pfdv2 gate_bit/vld_bit operations clk: imx: clk-pllv3: mark expected switch fall-throughs clk: imx8mq: Add dsi_ipg_div clk: imx: pllv4: add fractional-N pll support clk: imx: keep uart clock on during system boot clk: imx: correct i.MX7D AV PLL num/denom offset clk: imx6sll: Fix mispelling uart4_serial as serail clk: imx: pll14xx: drop unused variable clk: imx: rename clk-imx51-imx53.c to clk-imx5.c clk: imx5: Fix i.MX50 ESDHC clock registers clk: imx5: Fix i.MX50 mainbus clock registers clk: imx: Remove unused imx_get_clk_hw_fixed dt-bindings: clock: imx7ulp: remove SNVS clock clk: imx7ulp: remove snvs clock	2019-05-07 11:44:21 -07:00
Anson Huang	a5a627c676	clk: imx: correct pfdv2 gate_bit/vld_bit operations ... The operations of pfdv2 gate_bit/valid_bit are incorrect, they are defined as u8 for bit offset, but gate_bit is actually assigned as mask which could be 32 bit long and it causes overflow, and vld_bit is assigned as bit offset based on incorrect gate_bit value, it causes incorrect pfd clock gate status in clock tree, this patch fixes the issue by assigning them as correct bit offset. Fixes: 9fcb6be3b6 ("clk: imx: add pfdv2 support") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-03 09:31:54 -07:00
Gustavo A. R. Silva	53dd5c709b	clk: imx: clk-pllv3: mark expected switch fall-throughs ... In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/clk/imx/clk-pllv3.c: In function ‘imx_clk_pllv3’: drivers/clk/imx/clk-pllv3.c:446:18: warning: this statement may fall through [-Wimplicit-fallthrough=] pll->div_shift = 1; ~~~~~~~~~~~~~~~^~~ drivers/clk/imx/clk-pllv3.c:447:2: note: here case IMX_PLLV3_USB: ^~~~ drivers/clk/imx/clk-pllv3.c:453:21: warning: this statement may fall through [-Wimplicit-fallthrough=] pll->denom_offset = PLL_IMX7_DENOM_OFFSET; ^ drivers/clk/imx/clk-pllv3.c:454:2: note: here case IMX_PLLV3_AV: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enable -Wimplicit-fallthrough. Fixes: b4a4cb5a04 ("clk: imx: correct i.MX7D AV PLL num/denom offset") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-03 09:02:13 -07:00
Guido Günther	4d13c67adf	clk: imx8mq: Add dsi_ipg_div ... It's defined in imx8mq-clock.h but wasn't assigned yet. It's used as clk_tx_esc in the nwl dsi host controller (i.MX8MQ RM, Rev. 0, 01/2018 Sect. 13.5.3.7.4). Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-02 13:26:38 -07:00
Anson Huang	a048fe996b	clk: imx: pllv4: add fractional-N pll support ... The pllv4 supports fractional-N function, the formula is: PLL output freq = input * (mult + num/denom), This patch adds fractional-N function support, including clock round rate, calculate rate and set rate, with this patch, the clock rate of APLL in clock tree is more accurate than before: Without fraction: apll_pre_sel 1 1 1 24000000 0 0 50000 apll_pre_div 1 1 2 24000000 0 0 50000 apll 1 1 2 528000000 0 0 50000 apll_pfd3 0 0 0 792000000 0 0 50000 apll_pfd2 0 0 0 339428571 0 0 50000 apll_pfd1 0 0 0 352000000 0 0 50000 usdhc0 0 0 0 352000000 0 0 50000 apll_pfd0 1 1 1 352000000 0 0 50000 With fraction: apll_pre_sel 1 1 1 24000000 0 0 50000 apll_pre_div 1 1 2 24000000 0 0 50000 apll 1 1 2 529200000 0 0 50000 apll_pfd3 0 0 0 793800000 0 0 50000 apll_pfd2 0 0 0 340200000 0 0 50000 apll_pfd1 0 0 0 352800000 0 0 50000 usdhc0 0 0 0 352800000 0 0 50000 apll_pfd0 1 1 1 352800000 0 0 50000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>	2019-05-01 14:01:45 -07:00
Jacky Bai	8cd117e712	clk: imx: keep uart clock on during system boot ... Keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-29 16:02:01 -07:00
Anson Huang	b4a4cb5a04	clk: imx: correct i.MX7D AV PLL num/denom offset ... According reference manual, i.MX7D's audio/video PLL's num/denom register offset are 0x20/0x30, they are different from i.MX6's audio/video PLL, correct it by introducing new offset variables for audio/video PLL and using runtime assignment based on PLL type. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-29 16:01:50 -07:00
Leonard Crestez	6ff46d77ca	clk: imx6sll: Fix mispelling uart4_serial as serail ... This looks like a copy-paste error. This string is not referenced anywhere so it's safe to rename it. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 14:46:01 -07:00
Peng Fan	a3c9e13ff0	clk: imx: pll14xx: drop unused variable ... It does not make sense to only get value from pll->base and assign to a local variable when recalc_rate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 14:42:02 -07:00
Stephen Boyd	d635c3512d	i.MX7UPL clock changes for 5.2: ... - Remove SNVS clock from i.MX7UPL clock driver and bindings, as the clock will be visible on M4 core only, and never be accessed by Cortex-A cores. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJcvThaAAoJEFBXWFqHsHzOoR0H/0AjB+fmbMoeGEpo0pZjPFyw RbQ/+UavX0Yy4z4LJmYw3y3n7/cLvyv8Edg/BRXCvgX6dmjHa6sOSW3rZSD7BWUp Jg6m/NCkaq4GRFOfXrs+vzmjtEECyq5j6EV9QG8w3ZBEU733FkcQgMTsOmK9u7kF fxUfz7PReS6ZPk276gTMwWaNOl1R6W8eaHjiK0F1LQIcZfPRcsPtFRFkriQ27m/7 MOJ5Wjpf5804qis3p8gDIc/Z+wPaf5QF0exNKL/55INjVeSwCw81TAqTpFWrkrgj lF2DTXgBHVO9S03I5/d5CNFCYdlP7EbgRD5CoH7mWrqEiBnvUUAxhe5zlm4etno= =4yV1 -----END PGP SIGNATURE----- Merge tag 'clk-imx7ulp-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX7UPL clk changes from Shawn Guo: - Remove SNVS clock from i.MX7UPL clock driver and bindings, as the clock will be visible on M4 core only, and never be accessed by Cortex-A cores * tag 'clk-imx7ulp-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: clock: imx7ulp: remove SNVS clock clk: imx7ulp: remove snvs clock	2019-04-25 08:31:32 -07:00
Stephen Boyd	363de1d63e	i.MX5 clock changes for 5.2: ... - A couple of patches from Jonathan Neuschäfer to improve i.MX5 clock driver for i.MX50 support. - Rename file clk-imx51-imx53.c to clk-imx5.c, as it covers support for all i.MX5 series SoCs including i.MX50. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJcvTXlAAoJEFBXWFqHsHzO9oAH+wQtUGOJw7Yiu/UcjGQmoWRJ 0MRLknDBlVBTKSqZLVoFsm2xRyCkdHA7QB3OaCui4I40pdwoCOxDFHUOc2PTwBk2 kr0tHiiYoYXF6oZioD5tCh2zLHNuCIYy+TLzwG4jVavUCQAnQE8jzE59kiEvxBVg 9dvVxRjiIcHg0azm/oRsD+HQYwZ0ALMkLcAtbP1GGgsHeoSbaPJsYQCmj+9jDP8t OKwgtum7DeYFlelCMF70BubA3NmAFz3uKrgh1lXRGSM5nm2aMmuNyypFIN6c7E53 ELWfXvRLfncl5uipeIc5Km5r0L+AwBQmH9aOyzd3i4Ys2z3Kp5atSEhuqbDWnDI= =udGf -----END PGP SIGNATURE----- Merge tag 'clk-imx5-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX5 clk changes from Shawn Guo: - A couple of patches from Jonathan Neuschäfer to improve i.MX5 clock driver for i.MX50 support - Rename file clk-imx51-imx53.c to clk-imx5.c, as it covers support for all i.MX5 series SoCs including i.MX50 * tag 'clk-imx5-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: rename clk-imx51-imx53.c to clk-imx5.c clk: imx5: Fix i.MX50 ESDHC clock registers clk: imx5: Fix i.MX50 mainbus clock registers	2019-04-25 08:30:39 -07:00
Jonas Gorski	5834fd75e6	clk: core: replace clk_{readl,writel} with {readl,writel} ... Now that clk_{readl,writel} is just an alias for {readl,writel}, we can switch all users of clk_* to use the accessors directly and remove the helpers. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> [sboyd@kernel.org: Also convert renesas file so that this can be compile independently] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-23 10:57:49 -07:00
Shawn Guo	de348df5b3	clk: imx: rename clk-imx51-imx53.c to clk-imx5.c ... As the driver is handling all i.MX5 series SoCs inlcuding i.MX50, rather than just i.MX51 and i.MX53, let's rename it to clk-imx5.c. Signed-off-by: Shawn Guo <shawnguo@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org>	2019-04-15 17:09:23 +08:00
Leonard Crestez	f89b9e1be7	clk: imx: Fix PLL_1416X not rounding rates ... Code which initializes the "clk_init_data.ops" checks pll->rate_table before that field is ever assigned to so it always picks "clk_pll1416x_min_ops". This breaks dynamic rate rounding for features such as cpufreq. Fix by checking pll_clk->rate_table instead, here pll_clk refers to the constant initialization data coming from per-soc clk driver. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Fixes: 8646d4dcc7 ("clk: imx: Add PLLs driver for imx8mm soc") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-12 14:21:43 -07:00
Jonathan Neuschäfer	1e06250983	clk: imx5: Fix i.MX50 ESDHC clock registers ... The MUX bits for esdhc_{a,c,d}_sel are shifted by one bit within CSCMR1, because esdhc_b_sel (ESDHC3_CLK_SEL in the Reference Manual) is extended by one bit. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Shawn Guo <shawnguo@kernel.org>	2019-04-03 16:10:06 +07:00
Jonathan Neuschäfer	639eb92531	clk: imx5: Fix i.MX50 mainbus clock registers ... i.MX50 does not have a periph_apm clock. Instead, the main bus clock (a.k.a. periph_clk) comes directly from a MUX between pll1_sw, pll2_sw, pll3_sw, and lp_apm. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Shawn Guo <shawnguo@kernel.org>	2019-04-03 16:09:50 +07:00
Abel Vesa	48a15bb42d	clk: imx: Remove unused imx_get_clk_hw_fixed ... This is never used and the imx_clk_hw_fixed does the same thing. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>	2019-03-26 16:49:49 +08:00
Anson Huang	03fc565c2a	clk: imx7ulp: remove snvs clock ... Since i.MX7ULP B0 chip, the SNVS module is moved into M4 domain and its clock is also moved into PCC0 which is contorlled by M4, Linux kernel should NOT add it into clock tree. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>	2019-03-20 15:59:52 +08:00
Stephen Boyd	e7faa095cb	Merge branches 'clk-imx', 'clk-samsung', 'clk-ti', 'clk-uniphier-gear' and 'clk-mmp2-lcdc' into clk-next ... - Split LCDC into two clks on the Marvell MMP2 SoC * clk-imx: clk: imx8mq: add GPIO clocks to clock tree clk: imx: Refactor entire sccg pll clk clk: imx: scu: add cpu frequency scaling support clk: imx: imx8mm: Mark init function __init clk: imx8mq: Add the missing ARM clock dt-bindings: imx8mq-clock: Add the missing ARM clock clk: imx: imx8mq: Fix the rate propagation for arm pll clk: imx8mq: Add support for the CLKO1 clock clk: imx8mq: Fix the CLKO2 source select list clk: imx8mq: Add missing M4 clocks clk: imx: Add clock driver support for imx8mm dt-bindings: imx: Add clock binding doc for imx8mm clk: imx: Add PLLs driver for imx8mm soc clk: imx5: add imx5_SCC2_IPG_GATE clk: imx: scu: add set parent support clk: imx: scu: add fallback compatible string support clk: imx8mq: Make parent names arrays const pointers clk: imx: Make parents const pointer in mux wrappers clk: imx: Make parent_names const pointer in composite-8m * clk-samsung: clk: samsung: s3c2443: Mark expected switch fall-through clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure clk: samsung: exynos5433: Add selected IMEM clocks clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU clk: samsung: exynos5433: Fix name typo in sssx clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs * clk-ti: clk: clk-twl6040: Fix imprecise external abort for pdmclk ARM: OMAP2+: hwmod: disable ick autoidling when a hwmod requires that clk: ti: check clock type before doing autoidle ops clk: ti: add a usecount for autoidle clk: ti: generalize the init sequence of clk_hw_omap clocks clk: ti: remove usage of CLK_IS_BASIC clk: ti: add new API for checking if a provided clock is an OMAP clock clk: ti: move clk_hw_omap list handling under generic part of the driver * clk-uniphier-gear: clk: uniphier: Fix update register for CPU-gear * clk-mmp2-lcdc: clk: mmp2: separate LCDC peripheral clk form the display clock dt-bindings: marvell,mmp2: Add clock id for the LCDC clock	2019-03-08 10:27:40 -08:00
Stephen Boyd	7e2570031a	Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', 'clk-socfpga-parent' and 'clk-struct-size' into clk-next ... - Various DT of_node refcount fixes - Support for fixed rate clks populated from an MMIO register - Remove clps711x driver as the board support is gone * clk-of-refcount: clk: dove: fix refcount leak in dove_clk_init() clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init() clk: armada-xp: fix refcount leak in axp_clk_init() clk: kirkwood: fix refcount leak in kirkwood_clk_init() clk: armada-370: fix refcount leak in a370_clk_init() clk: vf610: fix refcount leak in vf610_clocks_init() clk: imx7d: fix refcount leak in imx7d_clocks_init() clk: imx6sx: fix refcount leak in imx6sx_clocks_init() clk: imx6q: fix refcount leak in imx6q_clocks_init() clk: samsung: exynos4: fix refcount leak in exynos4_get_xom() clk: socfpga: fix refcount leak clk: ti: fix refcount leak in ti_dt_clocks_register() clk: qoriq: fix refcount leak in clockgen_init() clk: highbank: fix refcount leak in hb_clk_init() * clk-mmio-fixed-clock: clk: Add Fixed MMIO clock driver dt-bindings: clk: Add bindings for Fixed MMIO clock * clk-remove-clps: clk: clps711x: Remove board support * clk-socfpga-parent: clk: socfpga: Don't have get_parent for single parent ops * clk-struct-size: clk: imx: imx7ulp: use struct_size() in kzalloc()	2019-03-08 10:26:59 -08:00
Anson Huang	0c91c11c7d	clk: imx8mq: add GPIO clocks to clock tree ... i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-28 10:28:28 -08:00
Abel Vesa	e9dda4af68	clk: imx: Refactor entire sccg pll clk ... Make the entire combination of plls to be one single clock. The parents used for bypasses are specified each as an index in the parents list. The determine_rate does a lookup throughout all the possible combinations for all the divs and returns the best possible 'setup' which in turn is used by set_rate later to set up all the divs and bypasses. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-26 10:09:31 -08:00
Anson Huang	3b9ea606cd	clk: imx: scu: add cpu frequency scaling support ... On NXP's i.MX SoCs with system controller inside, CPU frequency scaling can ONLY be done by system controller firmware, and it can ONLY be requested from secure mode, so Linux kernel has to call ARM SMC to trap to ARM-Trusted-Firmware to request system controller firmware to do CPU frequency scaling. This patch adds i.MX system controller CPU frequency scaling support, it reuses cpufreq-dt driver and implement the CPU frequency scaling inside SCU clock driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-26 10:03:38 -08:00
Stephen Boyd	341fdf2602	clk: imx: imx8mm: Mark init function __init ... It calls another __init marked function and thus causes a section mismatch if we don't mark it this way. Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 15:29:10 -08:00
Abel Vesa	db27e40b27	clk: imx8mq: Add the missing ARM clock ... Add the ARM clock as imx_clk_cpu type. Will be used by cpufreq. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:56:52 -08:00
Abel Vesa	ad18bbf369	clk: imx: imx8mq: Fix the rate propagation for arm pll ... The arm pll bypass needs to propagate the rate upwards in order for the cpufreq to work. Fixes: b80522040c ("clk: imx: Add clock driver for i.MX8MQ CCM") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:56:52 -08:00
Fabio Estevam	202ce5afe5	clk: imx8mq: Add support for the CLKO1 clock ... Add the entry for the CLKO1 clock. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:56:52 -08:00
Fabio Estevam	0bfed63baf	clk: imx8mq: Fix the CLKO2 source select list ... The CLKO2 clock source select list is the following as per the i.MX8M Reference Manual: 000 - 25M_REF_CLK 001 - SYSTEM_PLL2_DIV5 010 - SYSTEM_PLL1_DIV2 011 - SYSTEM_PLL2_DIV6 100 - SYSTEM_PLL3_CLK 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL1_CLK 111 - 32K_REF_CLK However, in imx8mq_clko2_sels[] only the first four entries are correct. Fix it by adding the missing "sys3_pll2_out" entry in order to match the description from the manual. Fixes: b80522040c ("clk: imx: Add clock driver for i.MX8MQ CCM") Reported-by: Rogerio Pimentel <rogerio.silva@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:17 -08:00
Carlo Caione	81bf81e7d3	clk: imx8mq: Add missing M4 clocks ... The clocks list is missing the clocks for the M4 core. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Bai Ping	ba5625c3e2	clk: imx: Add clock driver support for imx8mm ... Add clock driver support for i.MX8MM SOC. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Bai Ping	8646d4dcc7	clk: imx: Add PLLs driver for imx8mm soc ... New PLLs are introduced on i.MX8M Mini SOC. PLL1416X is Integer PLL, PLL1443X is a Frac PLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Michael Grzeschik	9b15cffbf2	clk: imx5: add imx5_SCC2_IPG_GATE ... This adds the missing clock for the SCC2 peripheral unit. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Aisheng Dong	666aed2d13	clk: imx: scu: add set parent support ... Add clk scu set parents support. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Remove le32_to_cpu() on get_parent op] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Aisheng Dong	cd67d32727	clk: imx: scu: add fallback compatible string support ... SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Make the driver support "fsl,scu-clk" fallback compatible string to allow other SoCs to reuse the common part. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Abel Vesa	402564aee0	clk: imx8mq: Make parent names arrays const pointers ... The arrays containing the mux selectors need to be of const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Abel Vesa	470663e078	clk: imx: Make parents const pointer in mux wrappers ... The parents needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Abel Vesa	65a6b7c5f3	clk: imx: Make parent_names const pointer in composite-8m ... The parent_names needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-02-21 12:41:16 -08:00
Gustavo A. R. Silva	921e88a4f9	clk: imx: imx7ulp: use struct_size() in kzalloc() ... One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct foo { int stuff; void *entry[]; }; instance = kzalloc(sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL); Instead of leaving these open-coded and prone to type mistakes, we can now use the new struct_size() helper: instance = kzalloc(struct_size(instance, entry, count), GFP_KERNEL); This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-01-24 11:37:46 -08:00
Abel Vesa	a64a9c088b	clk: imx: Fix fractional clock set rate computation ... Before multiplying by PLL_FRAC_DENOM, the temp64 needs to be temp64 = rate * 2 - divfi * parent_rate * 8, instead of: temp64 = (rate * 2 - divfi) * parent_rate Fixes: 6209624b9a ("clk: imx: Add fractional PLL output clock") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-01-24 11:17:28 -08:00
Wei Yongjun	48504619a6	clk: imx: fix potential NULL dereference in imx8qxp_lpcg_clk_probe() ... platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Fixes: 1e3121bfe5 ("clk: imx: add imx8qxp lpcg driver") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-01-09 10:34:54 -08:00
Yangtao Li	567177024e	clk: vf610: fix refcount leak in vf610_clocks_init() ... The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 1f2c5fd5f0 ("ARM: imx: add VF610 clock support") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-12-28 11:40:59 -08:00
Yangtao Li	5f8c183a99	clk: imx7d: fix refcount leak in imx7d_clocks_init() ... The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 8f6d8094b2 ("ARM: imx: add imx7d clk tree support") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-12-28 11:40:44 -08:00
Yangtao Li	1731e14fb3	clk: imx6sx: fix refcount leak in imx6sx_clocks_init() ... The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: d551356890 ("ARM: imx: add clock driver for imx6sx") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-12-28 11:40:25 -08:00
Yangtao Li	c9ec1d8fef	clk: imx6q: fix refcount leak in imx6q_clocks_init() ... The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 2acd1b6f88 ("ARM: i.MX6: implement clocks using common clock framework") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-12-28 11:40:04 -08:00