All chips on OpenPOWER platforms support the fastread SPI command.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Let's define the SPI controllers in the Aspeed SoCs AST2500 and
AST2400 and also enable these, as well as the chips, on the associated
platforms.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Palmettos have 512MB of memory as opposed to the previously thought
256MB. Update the device trees accordingly.
We run the uart at 115200.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
When used as a BMC, the host expects to be able to use 16MB of
framebuffer memory at the top of RAM.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
A common device tree for all forth gen/ast2400 systems and a board
specific dts for the Palmetto OpenPower developemnt machine which was
used for testing.
Signed-off-by: Joel Stanley <joel@jms.id.au>
