When the bus is configured to have more BCLK then the data type demands we
need to use the rotation to move the data to correct place.
Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
In IIS mode the tx and rx configuration is symmetric, the BCLK and FSYNC is
shared.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
If probe fails then we need to call pm_runtime_disable() to balance
out the previous pm_runtime_enable() call.
Signed-off-by: Anil Kumar <anilk4.v@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
In this way the start code for tx/rx going to be located at the same place.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The AFIFO should not be stopped (or started for that matter) when McASP is
running since it can cause unpredictable issues because we are switching off
AFIFO for the direction which was handling the requests from McASP and was
generating DMA request toward the system DMA.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Follow the sequence described in the TRMs when starting RX.
Write to RXBUF register was not correct and there is no need to release the
RX state machine/Receive frame sync generator twice.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Follow the sequence described in the TRMs when starting TX. This sequence
will make sure that we are not facing with initial channel swap caused by
no data available in McASP for transmit.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
If the board is sent to suspend (deep sleep) the McASP context will be lost.
In case when suspend happens during active audio we need to save and restore
more registers, which was configured during hw_param times as well.
We need to add more config registers, AFIFO control registers and we also
need to save and restore the serializer configuration as well.
Since the number of serializers depends on the SoC we need to allocate the
memory for it based on the num_serializer for the given McASP instance.
With this patch the ongoing stream will resume after resuming from deep
sleep.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Instead of individual values use an array to store the registers need to be
saved on suspend and restored on resume.
It is going to be easier to add more registers to save and restore.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
In case of capture we should not use rotation. The reverse and mask is
enough to get the data align correctly from the bus to MCU:
Format data from bus after reverse (XRBUF)
S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
With this patch all supported formats will work for playback and capture.
Reported-by: Jyri Sarha <jsarha@ti.com> (broken S24_3LE capture)
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
The implicit BLCK divider setting was broken by "ASoC: mcasp: don't
override bclk divider if it was provided by the machine"-patch. After
the BCLK divider is implicitly set for the first time the
mcasp->bclk_div gets a non zero value and the implicit setting is
"turned off".
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
If a machine driver provides an BCLK divider to the McASP driver, skip the
automatic calculation.
This fixes machines on which the physical sample transport always works
in 32 bits, even though not all of them are actually used.
snd_soc_params_to_bclk() will fail to address such cases properly.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Use the edma-pcm with AM335x and AM437x SoCs.
Keep using the davinci-pcm for daVinci devices, they can be switched to use
the dmaengine based driver later when they are verified to work correctly.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
In case of S24_LE/U24_LE modes we expect 24bits on the bus while the samples
are stored and transferred in memory on 32bits (lower 3 bytes of the 4
bytes).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Do not fail if the exact BLCK rate can not be produced, just print a
warning. Check that sysclk frequency is set before implicitly setting
the BCLK divider.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Fixes build with SND_DAVINCI_SOC or SND_OMAP_SOC alone and adds build
dependecy to SND_DAVINCI_SOC or SND_OMAP_SOC.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
In DIT (S/PDIF) mode, program the transmitted user bits to reflect the
configured sample rate, along with some other details.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Make including the omap-pcm.h outside sound/soc/omap more convenient.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Remove the cleanup code related to the platform from the DAI drivers at the
same time to avoid breakage.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Version 4 of McASP is using omap-pcm as platform driver and the omap-pcm
platform need to be registered using the cpu dai's device.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This register is not defined in TI81xx and on AM335x/AM437x it is the
SYSCONFIG register which should not be touched by drivers since it is
related to PM and handled by the generic PM code.
This register write was there since the first time the davinci-mcasp driver
was appeared in the kernel.
The reason why it did not caused any issues on AM335x/AM437x is that it sets
bit 1 in SYSCONFIG register which in turn will enable the smart-idle mode.
This is the default mode and this is the mode McASP should be in also when
in use.
On TI81xx the register is not defined.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The FS needs to be inverted in McASP compared to other supported formats.
Use a flag to indicate if the FS needs to be inverted.
At the same time fail when non supported format is asked since the default
case was anyways configuring McASP to a not valid format.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
FS polarity can be either rising or falling edge in McASP. Instead of
accessing the registers in every switch/case set a flag and write the
registers after the switch for the invert configuration.
This change will help when adding support for more formats also.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
DSP_A is like DSP_B mode but with one bit delay after the FS.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Use intermediate variable for the data delay needed for the specific format
and write the register after the format configuration at once.
This will help to control the number of lines as support for more formats
going to be added.
Also fixes a case when we switch between two formats with different delay
requirements.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
When the AFIFO is not enabled but more than one serializers are used the DMA
need to transfer number of words equal to active serializers when a DMA
request is generated.
When configuring the burst for the DMA avoid using value '1' for the burst
since it is going to enable additional logic in the DMA drivers. Burst '1'
means that the DMA should send/receive one word per DMA requests.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Configure the AFIFO numevt parameter based on the requested tx/rx_numevt,
active serializers and period size in words.
In this way McASP can adopt it's (and the DMA) configuration runtime and
can pick the most optimal setup which satisfy the parameters.
This way we do not need to place any constraint on the stream itself,
allowing application greater freedom on how they want to set up ALSA.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Move the dma_params->fifo_level and dma_data->maxburst configuration to the
mcasp_common_hw_param() function where we configure the AFIFO registers.
It makes the code regarding to AFIFO and DMA configuration more easy to
follow since it is now clear how the AFIFO and how the DMA is going to be
configured.
Previously this has been done in two functions using a bit different
calculation form - which ended up with the same result in both case at the
end, but it was confusing.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
We can have more linear code flow by using variables in
mcasp_common_hw_param() related to the AFIFO configuration.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Set up the playback_dma_data/capture_dma_data for the dai at probe
time since the generic dmaengine PCM stack needs to have access to
this information early.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
IB_NF, NB_IF and IB_IF configured the bc polarity incorrectly. The receive
polarity was set to the same edge as the TX in these cases.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
When we boot with non-DT mode the damengine will need the channel number and
a filter function in order to get the channel.
The filter_data is filled in the DAI driver while the filter_function will
be provided by the edma-pcm driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
It is quite confusing to name the pointer to davinci_pcm_dma_params as
dma_data. Rename the pointer to avoid confusion.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Move the context register storage behind of a struct and use a pointer to
it in the suspend/resume callbacks to remove the long lines.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Rename the struct for the platform data:
snd_platform_data -> davinci_mcasp_pdata
Since we have users under arch/arm/mach-davinci/ for this struct add
temporary define to avoid breakage. The arch code can be updated later to
use the new struct name.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Rearrange the code in the function for readability.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Handle the PM callbacks via the ASoC core instead of device core.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Take the return value from mcasp_common_hw_param() and use that in case of
error.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The use of pm_runtime in trigger() callback is not correct and it will lead
to unbalanced power.usage_count.
The only place which might need to call pm_runtime is the set_fmt callback.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
These registers can be configured synchronously for playback and capture.
Furthermore when McASP is in master and sync mode the capture operation
needs the TX path to be configured in order to be able to provide the needed
clocks for the bus.
xxFMT and xxFMCT registers has been already configured for both TX and RX
other places in the driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Instead of
davinci_hw_common_param - for common, I2S/DIT mode settings
davinci_hw_dit_param - for DIT protocol configuration
davinci_hw_param - for I2S (and compatible protocols)
Use the following names:
mcasp_common_hw_param, mcasp_dit_hw_param and mcasp_i2s_hw_param.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Make BCLK divider setting implicite in hw_params call if McASP device
is the bit clock master on the audio serial bus.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Optional DT property to specify the desired parent clock for the McASP fck
clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
An earlier patch overlooked this when the compatible has been changed from
omap2 -> am33x.
Rename omap2_mcasp_pdata to am33xx_mcasp_pdata.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Instead of passing __iomem address (mcasp->base + register_offset) pass
the main mcasp structure and only access the mcasp->base in the low level
IO functions.
In most cases this helps with code readability and it will make it easier
to switch over to regmap in the future.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The IP in DRA7xx is similar to the IP found in TI81xxAM3xxx/AM4xxx type of
SoCs but it is is integrated with sDMA instead of eDMA. The suitable pcm
driver for DRA7xx is the omap-pcm driver which is using dmaengine.
In the driver we can configure both dma related structures used for eDMA and
sDMA. The only thing we need to make sure that we set the correct dma_data
at startup with snd_soc_dai_set_dma_data()
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
In synchronous mode both transmit and receive sections are using the TX
clocks. In setup like this the TX clocks need to be enabled when capture
is running.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The audio data to/from McASP can be sent/received via two method:
Via the data port (preferred) or via the configuration bus.
Currently the driver assumes that all data communication will be done via
the data port.
This patch adds support for selecting the configuration port as data
interface.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The FIFO registers base address is different in dm646x compared to newer
SoCs with McASP IP. Instead of using two paths (switch/case) to handle the
difference we can simply pick the correct base address beforehand and use
offsets to address the register we need to configure.
With this change the indentation depth can be reduced as well.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Replace mcasp->base use with plain base in the davinci_mcasp_set_dai_fmt()
function since it has been already used by the remaining part of the function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Rename the private struct from davinci_audio_dev to davinci_mcasp.
Change the local use of the pointer to this struct from *dev to *mcasp.
The aim is to have better readable code for the first look since having
dev->xxxx in the code when using the local private struct is a bit
surprising.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
It brings no benefit to inline this function due to it's size and function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Since it is a private struct strictly used by the davinci-mcasp driver it
can be moved from header file to the source file.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
It is better for readability to have the register definitions out from the
source file.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The serial-dir array gives this information so there is no need to have the
num-serializer property in DT description.
Just ignore the property in the driver the DTS files can be updated
separately without regression.
Update the documentation at the same time for davinci-mcasp
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Change the model omap2-mcasp-audio in compatible property to
am33xx-mcasp-audio as omap2 does not have mcasp.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Extract DMA channels directly from DT as they can not be found from
platform resources anymore. This is a work-around until davinci audio
driver is updated to use dmaengine.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This patch adds a separate register location for data port registers to
mcasp DT bindings. On am33xx SoCs the McASP registers are mapped
trough L4 interconnect, but data port registers are also mapped trough
L3 bus to a different memory location.
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Darren Etheridge <detheridge@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
When the system returns from suspend, it looses its configuration. Most
of it is restored by running a normal audio stream startup, but the DAI
format is left unset as that's configured on the audio device creation.
Hence, it suffices here to care for the registers which are touched by
davinci_mcasp_set_dai_fmt() and restore them when the system is resumed.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
'mcasp_dt_ids' is always compiled in. Hence of_match_ptr is not
necessary.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
McASP serial audio engine needs different rotation values on TX and RX
channels. Commit dde109fb46 ("ASoC: McASP: Fix data rotation for
playback. Enables 24bit audio playback") changed the calculation to fix
the playback format, but broke the capture stream by doing it for both
TXFMT and RXFMT.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@vger.kernel.org [3.9 only]
A few more bug fixes, the DAPM clock fix is actually a driver specific
one since currently there's only one user of the clock support due to
the problems relying on the clock API.
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Merge tag 'asoc-v3.10-4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
ASoC: Updates for v3.10
A few more bug fixes, the DAPM clock fix is actually a driver specific
one since currently there's only one user of the clock support due to
the problems relying on the clock API.
According documentation bit ACLKRPOL is set to 0 (receiver samples data
on falling edge) and when set to 1 (receiver samples data on rising edge).
I2S data are always sampled on falling edge and valid during rising edge
of bit clock. So in case of capture data transmitter sample data on falling
edge and macsp must read then on rising edge.
Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
When McASP is bit clock and frame clock master enable pin output for rx clocks.
Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
For TDM mode, BCLK-to-LCLK ratio is computed as (tdm_slots) x (word_length).
I2S mode is only subset of TDM mode with specific tdm_slots = 2 channels.
Also bclk_lrclk_ratio can be greater than 255, therefore u16 need to be used.
Signed-off-by: Michal Bachraty <michal.bachraty@streamunlimited.com>
Acked-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
As pointed of by Vaibhav, commit message: "ASoC: davinci-mcasp: Add support for multichannel playback"
number of active serializers can be hidden into fifo_level variable, which is set in davimci-mcasp.
Signed-off-by: Michal Bachraty <michal.bachraty@streamunlimited.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Channel size settings will be made at the end of
davinci_mcasp_hw_params() routine and thus overwrite frame
format settings made for DIT mode. This patch fixes this issue
by taking op_mode into account. Tested with official PSP 3.2
kernel and sii9022a HDMI transmitter.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
AFSX won't be used in DIT mode. The related pins are AHCLKX and
the data pins.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
As pointed of by Vaibhav, commit 2952b27e2 ("ASoC: davinci-mcasp:
Add support for multichannel playback") duplicated the logic of
counting the active serializers. That can be avoided by shifting
the code around a bit.
Also, drop two unused defines introduced by the same commit.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Davinci McASP has support for I2S multichannel playback.
For I2S playback/receive, each serializer is capable to play 2 channels
(L/R) audio data.Serializer function (Playback-receive-none) is configured
in DT, depending on hardware specification. It is possible to play less
channels than configured in DT. For that purpose,only specific number of
active serializers are enabled. McASP FIFO need to have DMA transfer Bcnt
set to number of enabled serializers, otherwise no data are transfered to
McASP and Alsa generates "DMA/IRQ playback write error (DMA or IRQ trouble?)"
error. For TDM mode, McASP is capable to play or receive 32 channels for one
serializer. McAsp has support for max 16 serializer, therefore max channels
is 32 * 8.
Signed-off-by: Michal Bachraty <michal.bachraty@streamunlimited.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
u32 rotate = (32 - word_length) / 4;
This implementation is wrong, but it works only for 16, or 32 bit audio data.
(rotation for 16 or 32 bit is same as in code I present) Mcasp rotated data in
4 bits (max value 0x7)and then masks them . That data are sended to i2s bus.
For 24 bit or 20 bit or other data formats, this code rotates data badly and
you hear somethink like noise. You need to use
u32 rotate = (word_length / 4) & 0x7;
to proper data rotation.
Signed-off-by: Michal Bachraty <michal.bachraty@streamunlimited.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Depending on the Codec, the the BCLK/LRCLK ratio might not be freely
chosen by the CPU DAI.
For example, some Codec might want to be supplied with 32-bit samples
for both its channels regardless of the actual audio word size the CPU
sends. In such cases, the rest of the bits on the data lines must be
padded with zeros:
_______________________________
LRCLK / \
--' `---------- .....
BCLK ||||||||||||||||||||||||||||||||||||||||||||||| .....
DATA ____||||||||||||||||_________________|||||||||| .....
|<-- data -->|<-- pads --> |
This patch adds a new clock divider to configure the BCLK/LRCLK ratio.
If the machine code uses that divider, the driver uses the specified
value, instead of deriving that information from the audio word size.
Otherwise, the original behaviour is retained.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Change davinci_config_channel_size() to derive the values for XSSZ and
XROT in DAVINCI_MCASP_[RT]XFMT_REG from the configured word length
rather than hard-coding them in a switch/case block.
Also, by directly passing the word length to
davinci_config_channel_size(), we can get rid of the
DAVINCI_AUDIO_WORD_* enum.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
codec_fmt and sample_rate variables are unused in both snd_platform_data
and davinci_audio_dev, so drop them.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Removes the DaVinci private SRAM API and replaces it with
the genalloc API. The SRAM gen_pool is passed in pdata since
DaVinci is in the early stages of DT conversion.
[zonque@gmail.com: stub out gen_pool functions for
!CONFIG_GENERIC_ALLOCATOR]
Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Daniel Mack <zonque@gmail.com>
Reported-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The FSDUR flag configures whether the frame clock uses a high phase of
only one bit or a full word. This has to be set depending on the DAI
format.
For other modes than DSP_B, the FSXDLY/FSRDLY fields have to be set to
1.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add a .set_sysclk function to pass the direction of the clock down to
the driver. Only enable AHCLKX in the PDIR register when the CPU is
driving the clock.
This also removes the modification of the AHCLKXE/AHCLKRE bits in the
hw_params callback, and users must set the desired configuration using
snd_soc_dai_set_sysclk(), which this patch also does for the only user
in mainline (davinci-evm).
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add support for the internal clock dividers of the McASP driver.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The OMAP2+ variant of McASP is different from Davinci variant w.r.to
some register offset.
Changes
- Add new MCASP_VERSION_3 to identify new variant. New DT compatible
"ti,omap2-mcasp-audio" to identify version 3 controller.
- The register offsets are handled depending on the version.
Note:
DMA parameters (dma fifo offset) are not updated and will be done later.
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add device tree probe for McASP driver.
Note:
DMA parameters are not populated from DT and will be done later.
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Same as the commit 518de86 (ASoC: tegra: register 'platform' from DAIs,
get rid of pdev). It makes davinci-pcm not a platform_driver but helper
to register "platform", so that the platform_device for davinci-pcm can
be saved completely.
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* Add Runtime PM support to McASP host controller.
* Use Runtime PM API to enable/disable McASP clock.
This was tested on AM18x Board using suspend/resume
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
