Pull the clockevents/clocksource tree from Daniel Lezcano:
- Convert the clocksource-probe init functions to return a value in order to
prepare the consolidation of the drivers using the DT. It is a big patchset
but went through 01.org (kbuild bot), linux next and kernel-ci (continuous
integration) (Daniel Lezcano)
- Fix a bad error handling by returning the right value for cadence_ttc
(Christophe Jaillet)
- Fix typo in the Kconfig for the Samsung pwm (Alexandre Belloni)
- Change functions to static for armada-370-xp and digicolor (Ben Dooks)
- Add support for the rk3399 SoC timer by adding bindings and a slight
change in the base address. Take the opportunity to add the DYNIRQ flag
(Huang Tao)
- Fix endian accessors for the Samsung pwm timer (Matthew Leach)
- Add Oxford Semiconductor RPS Dual Timer driver (Neil Armstrong)
- Add a kernel parameter to swich on/off the event stream feature of the arch
arm timer (Will Deacon)
Add a 'rktimer' node in the device treee for the ARM64 rk3399 SoC.
Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.
These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.
Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The 2nd additional region is the GIC virtual cpu interface register
base and size.
As the gic400 of rk3368 says, the cpu interface register map as below
:
-0x0000 GICC_CTRL
.
.
.
-0x00fc GICC_IIDR
-0x1000 GICC_IDR
Obviously, the region size should be greater than 0x1000.
So we should make sure to include the GICC_IDR since the kernel will access
it in some cases.
Fixes: b790c2cab5 ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: stable@vger.kernel.org
[added Fixes and stable-cc]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals. Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.
Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates. 200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
their i2c bus was slow anyway. Since we gate the functional clock
when the i2c bus is not active, power savings would only be while i2c
transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
clock to make divisions work out perfectly, accounting for the rise /
fall time measured on an actual board.
Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal
data is including the cpu and gpu sensor zone node.
The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings.
The thermal zone node must contain, apart from its own properties, one
sub-node containing trip nodes and one sub-node containing all the zone
cooling maps.
The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls
* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.
* trips:
A sub-node which is a container of only trip point nodes required to
describe the thermal zone.
* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.
* cooling-device:
A phandle of a cooling device with its specifier, referring to which
cooling device is used in this cooling specifier binding. In the cooling
specifier, the first cell is the minimum cooling state and the second cell
is the maximum cooling state used in this map.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tree-wide replacement was done by commit 2ef7d5f342 (ARM, ARM64:
dts: drop "arm,amba-bus" in favor of "simple-bus"), but we have some
new users of "arm,amba-bus" at Linux 4.7-rc1. Eliminate them now.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The general register files do contain a lot of separate functions and
while some really are only registers with a lot of different 1-bit
settings, there are also a lot of them containing some bigger function
blocks. To be able to define these as sub-devices, make them simple-mfds.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: David Wu <david.wu@rock-chips.com>
Rockchip's rk3399 evaluation board has eMMC. Let's enable the
newly-added nodes.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to
200 MHz, to support all supported timing modes.
Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably
have a compliant Arasan controller, but let's have a rockchip property
as the canonical backup/precautionary measure. Per Heiko's previous
suggestion, let's not clutter the arasan doc with it.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Per the examples in
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt, we need the
grf node to be a simple-mfd in order to properly enumerate child devices
like our eMMC PHY.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
[directly mimic for the pmugrf, which will need the same change later
and there is no need to pollute commit history with another patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
These clocks are all core clocks used by many blocks/peripherals, many
of whose drivers don't set their clock rates at all. Let's assign
reasonable default clock rates for these core clocks, so that these
peripherals get something reasonable by default, and also so that if
child devices want to select a clock rate themselves, their muxes have
some reasonable parent clock rates to branch off of (rather than just
the boot-time defaults).
This helps the eMMC PHY, for one, to get a reasonable ACLK rate.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds core dtsi file for Rockchip RK3399 SoCs.
The RK3399 has big/little architecture, which needs a separate
node for the PMU of each microarchitecture, for now it missing
the pmu node since the old one could not work well.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In order to be standard to manage for rockchip SoCs, move the thermal
data into rk3368 dtsi, we needn't to add a new file for thermal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The GeekBox contains an MXM3 module with a Rockchip RK3368 SoC.
Some connectors are available directly on the module.
This adds initial support, namely serial, USB, GMAC, eMMC, IR and TSADC.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Drop superfluous #address-cells and #size-cells.
Use KEY_POWER define for 116.
Rename sub-nodes to avoid new dtc warnings.
Reported-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds mailbox device nodes in dts.
Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Only one of "broken-cd" and "non-removable" should be supplied
according to Documentation/devicetree/bindings/mmc/mmc.txt.
Obviously emmc and sdio-wifi are non-removable devices, while
broken-cd is for removable device whose card detect pin is broken.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch fixes the incorrect Over-temperature protection pin.
since the rk3368 io list said the otp pin is gpio0a3.
Anyway, that should be fixed in here.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy
"gpio-key,wakeup" boolean property to enable gpio buttons as wakeup
source.
Few dts files assign value "1" to gpio-key,wakeup and in one instance a
value "0" is assigned probably assuming it won't be enabled as a wakeup
source. Since the presence of the boolean property indicates it is
enabled, value of "0" have no value.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property which inturn fixes the above mentioned issue.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add tuning clk for emmc and sdmmc, otherwise I get
the following failure while enabling mmc-hs200-1_8v.
dwmmc_rockchip ff0f0000.dwmmc: Tuning clock (sample_clk) not defined.
mmc0: tuning execution failed
mmc0: error -5 whilst initialising MMC card
With it
dwmmc_rockchip ff0f0000.dwmmc: Successfully tuned phase to 170
mmc0: new HS200 MMC card at address 0001
mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There is a need of a broadcast timer in this case to ensure proper
wakeup when the cpus are in sleep mode and a timer expires.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The card detect pin is currently called sdmcc-cd.
This patch fixes the typo and renames the pin to sdmmc-cd.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In general, the logic voltage is affected by ddr frequency factors.
We should fix the correct voltage range since assuemd that we have the
ddr frequency driver in mainline.
AFAIK, the 1.8v voltage is used by the SD3.0 card.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This board is similar with the rk3288 evb board but the rk3368 top
board. There exist the act8846 as the pmic.
Moment, add the balight/thermal/emmc/usb.. stuff,
Let the board can happy work.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The pulse-width modulator (PWM) feature is very common in
embedded systems. On the rk3368 there exist 4 built-in PWM channels.
In general, the pwm pins can via the pinctrl to
configure iomux mode except the pwm2 since the pwm2 iomux mode from
the SoC control register.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch enable the TS-ADC.
When a thermal temperature is invoked use the CRU to reset the chip
on R88 board. TSHUT is low active on this board.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch add the thermal needed info on RK3368.
Meanwhile, support the trips to throttle for thermal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patchset add the thermal for RK3368 dts,
Since the two CPU clusters, with four CPU core for each cluster,
one cluster is optimized for high-performance(big cluster) and the othe
is optimized for low power(little cluster).
This patch adds the second order for thermal throttle, and the critical
temperature for thermal over-tempeature protection on Software.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add an ethernet0 alias for the RK3368 mac interface so
that u-boot can find the device-node and fill in the mac address on
boards that support a wired network interface.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The idle-states bindings mandate that the entry-method string
in the idle-states node must be "psci" for ARM v8 64-bit systems,
but the examples in the bindings report a wrong entry-method string.
Owing to this typo, some dts in the kernel wrongly defined the
entry-method property, since they likely cut and pasted the example
definition without paying attention to the bindings definitions.
This patch fixes the typo in the DT idle states bindings examples and
respective dts in the kernel so that the bindings and related dts
files are made compliant.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Howard Chen <howard.chen@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Rob Herring <robh@kernel.org>
In terms of peripherals the rk3368 is quite similar to the rk3288, which
makes it possible to have a lot basic components working in the first go.
More to follow once I tracked down all the tiny differences that still
exist in some parts.
With these dts files, the R88 board is able to boot from an attached
usb device and most likely from its emmc too, if the emmc uses a standard
partition table instead of Rockchip's own one - the emmc itself is
detected correctly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
