Commit Graph

347 Commits

Author SHA1 Message Date
Alexandre Courbot
aff51175cd drm/nouveau/bus: remove cpu_coherent flag
This flag's only remaining function is to ignore the uncached flag for
BOs on coherent architectures.

However the reason for allocating an object uncache on a non-coherent
architecture (namely because the cost of doing explicit flushes/
invalidations is higher than the benefit of caching the data because
accesses are few and far between) should also apply on architectures for
which coherency is maintained implicitly. Thus allocate coherent objects
as uncached on all architectures.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:55:18 +10:00
Ben Skeggs
146cfe2476 drm/nouveau/ce/gp104: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
fd47877f77 drm/nouveau/disp/gp104: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
6258cd43cf drm/nouveau/fb/gp104: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
52fa0866ca drm/nouveau/gr/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
8e7e1586c5 drm/nouveau/ce/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
e8ff979492 drm/nouveau/fifo/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
f9d5cbb388 drm/nouveau/disp/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
a96def399b drm/nouveau/ltc/gp100: initial support
Due to the GPU preventing us from touching NV_PLTCG_LTCS_LTSS_CBC_BASE,
we cannot provide CBC/ZBC support without signed PMU firmware to handle
the task for us...

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
7ff51f8200 drm/nouveau/fb/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
45aa4d0774 drm/nouveau/pci/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
be61c54cbe drm/nouveau/mc/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
7f53abdb95 drm/nouveau/core: recognise GP100 chipset
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
cb7b5ea9be drm/nouveau/core: increase maximum nvenc instances to 3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
34bf50cd20 drm/nouveau/core: increase maximum ce instances to 6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
c73baa831f drm/nouveau/fb/gf100-: allow selection of an alternate big page size
GFxxx/GM1xx support the selection of 64/128KiB big pages globally.

GM2xx supports the same, as well as another mode where the page size
can be selected per-instance.

We default to 128KiB pages (With per-instance for GM200, but the current
code selects 128KiB there already) as the MMU code isn't currently able
to handle otherwise.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
2f96e8e3e0 drm/nouveau/bios: pointers beyond end of first image need special handling
Makes common the code that was previously used by the PMU table parsing,
as it appears other tables need this too.

Not much of an idea what this is all about...

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
4d4e9907ff drm/nouveau/bios: guard against out-of-bounds accesses to image
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Karol Herbst
437bb44d38 drm/nouveau/volt: save the voltage range we are able to set
We shouldn't set voltages below the min or above the max voltage the gpu is
able to set, so save the range for future lookups.

Signed-off-by: Karol Herbst <karolherbst@gmail.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
d2680907c2 drm/nouveau/tegra: fetch gpu_speedo_id
The GPU speedo ID is required to select the right clk/volt parameters on
GM20B.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
5dfc5dbf65 drm/nouveau/secboot: use nvkm_mc_enable/disable()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
2b80bb74fb drm/nouveau/secboot: use nvkm_mc_intr_mask/unmask()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
66adbfb00d drm/nouveau/mc: support for temporarily masking interrupts from a specific device
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
3c2a536b0c drm/nouveau/mc: expose device enable/disable separately, as well as reset
There are cases where subdevs need to perform additonal actions around
the master reset, so we want to expost the operations separately.

This commit also adds a flag to the NV_PMC_ENABLE bitfield definitions
which allow skipping the automatic reset() called from core/subdev.c.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
d398119034 drm/nouveau/mc: take nvkm_device as argument to public functions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
3560e1703f drm/nouveau/top: add function to lookup interrupt mask for a given device
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
952eb819e3 drm/nouveau/top: take nvkm_device as argument to public functions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
77154fd969 drm/nouveau/core: swap the order of imem/fb
Fixes a use-after-free reported by valgrind and KASAN.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-06-02 13:54:07 +10:00
Ben Skeggs
bc9139d23f drm/nouveau/bios/disp: fix handling of "match any protocol" entries
As it turns out, a value of 0xff means "any protocol" and not "VGA".

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2016-06-02 13:53:30 +10:00
Ben Skeggs
e976278ad2 drm/nouveau/fb/gm200: setup mmu debug buffer registers at init()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
99c5917253 drm/nouveau/fb/gf100-: allocate mmu debug buffers
Later chipsets require setting this up both in FB and GR, so let's just
move the allocation to FB.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
56d06fa29e drm/nouveau/core: remove pmc_enable argument from subdev ctor
These are now specified directly in the MC subdev.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
667e99ab23 drm/nouveau/mc/nv11: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
79360b7d5f drm/nouveau/mc/nv17: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
7354902001 drm/nouveau/mc/g84: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
88c0de2cdb drm/nouveau/mc/gt215: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
33537d6fdc drm/nouveau/mc/gk104: define reset masks + intr cleanup
Engine fields have been removed, as they're specified by PTOP.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
6defde5ab3 drm/nouveau/mc: add helper function to handle device reset
This will be later extended to handle PTOP-specified reset masks as well
as the hardcoded ones.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
fb3e9c61ca drm/nouveau/top/gk104: initial implementation
Ported from the code currently in engine/fifo/gk104.c.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
5f76f294d1 drm/nouveau/top: initial implementation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
eaebfcc34e drm/nouveau/core: add top plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
5f1f07de41 drm/nouveau/iccsense: split sensor into own struct
v2: add list_del call, reword error message

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
92224e751f drm/nouveau/iccsense: convert to linked list
v2: add list_del calls

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
d03e0f2748 drm/nouveau/iccsense: remove read function
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Alexandre Courbot
c6007dc4e5 drm/nouveau/devinit/gf100: make devinit on resume safer
In case of successful suspend, devinit will have to be run and this is
the behavior currently hardcoded. However, as FD bug 94725 suggests,
there might be cases where runtime suspend leaves the GPU powered, and
in such cases devinit should not be run on resume.

On GF100+ we have a reliable way to know whether we need to run devinit.
Use it instead of blindly trusting the flag set by nvkm_devinit_fini().

The code around the NvForcePost also needs to be slightly reworked in
order to keep working.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Suggested-by: Dave Airlie <airlied@redhat.com>
Suggested-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Alexandre Courbot
34440ed697 drm/nouveau/tegra: acquire and enable reference clock if needed
GM20B requires an extra clock compared to GK20A. Add that information
into the platform data and acquire and enable this clock if necessary.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-04-06 16:06:51 +10:00
Alexandre Courbot
52829d4fab drm/nouveau/clk/gm20b: add basic driver
Add a basic clock driver that reuses the GK20A logic.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:56 +10:00
Alexandre Courbot
71757abf2e drm/nouveau/volt: add GM20B driver
Add basic GM20B volt driver that reuses the GK20A logic.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:50 +10:00
Ben Skeggs
253a03f03f drm/nouveau/ce/gm107: expose MaxwellDmaCopyA
The HW accepts KeplerDmaCopyA and MaxwellDmaCopyA classes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:49 +10:00
Ben Skeggs
7c4f87c9e5 drm/nouveau/fifo/gm107: KeplerChannelGpfifoB, and 2048 channels
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:48 +10:00