Commit Graph

7896 Commits

Author SHA1 Message Date
Harry Wentland
1619677618 drm/amd/display: Only require EDID read for HDMI and DVI
[Why]
VGA sometimes has trouble retrieving the EDID on very long cables, KVM
switches, or old displays.

[How]
Only require EDID read for HDMI and DVI and exempt other types (DP,
VGA). We currently don't support VGA but if anyone adds support in the
future this might get overlooked.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Suggested-by: Michel Dänzer <michel@daenzer.net>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-03 10:14:10 -05:00
Harry Wentland
01dc285d5c drm/amd/display: Report non-DP display as disconnected without EDID
[Why]
Some boards seem to have a problem where HPD is high on HDMI even though
no display is connected. We don't want to report these as connected. DP
spec still requires us to report DP displays as connected when HPD is
high but we can't read the EDID in order to go to fail-safe mode.

[How]
If connector_signal is not DP abort detection if we can't retrieve the
EDID.

v2: Add Bugzilla and stable

Bugzilla: https://bugs.freedesktop.org/107390
Bugzilla: https://bugs.freedesktop.org/106846
Cc: stable@vger.kernel.org
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-03 10:14:09 -05:00
Gustavo A. R. Silva
ddf74e79a5 drm/amdgpu/pm: Fix potential Spectre v1
idx can be indirectly controlled by user-space, hence leading to a
potential exploitation of the Spectre variant 1 vulnerability.

This issue was detected with the help of Smatch:

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:408 amdgpu_set_pp_force_state()
warn: potential spectre issue 'data.states'

Fix this by sanitizing idx before using it to index data.states

Notice that given that speculation windows are large, the policy is
to kill the speculation on the first load and not worry if it can be
completed with a dependent load/store [1].

[1] https://marc.info/?l=linux-kernel&m=152449131114778&w=2

Cc: stable@vger.kernel.org
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:23 -05:00
Colin Ian King
7ac7aebe85 drm/amd/display: add missing void parameter to dc_create_transfer_func
Add a missing void parameter to function dc_create_transfer_func, fixes
sparse warning:

warning: non-ANSI function declaration of function 'dc_create_transfer_func'

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:22 -05:00
Thomas Zimmermann
fea872b279 drm/amdgpu: Replace ttm_bo_unref with ttm_bo_put
The function ttm_bo_put releases a reference to a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.

A call to ttm_bo_unref takes the address of the TTM BO object's pointer and
clears the pointer's value to NULL. This is not necessary in most cases and
sometimes even worked around by the calling code. A call to ttm_bo_put only
releases the reference without clearing the pointer.

The current behaviour of cleaning the pointer is kept in the calling code,
but should be removed if not required in a later patch.

v2:
 * set prefix to drm/amdgpu

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:21 -05:00
Thomas Zimmermann
71d5ef1127 drm/amdgpu: Replace ttm_bo_reference with ttm_bo_get
The function ttm_bo_get acquires a reference on a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.

v2:
 * changed prefix to drm/amdgpu

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:21 -05:00
Christian König
4a102ad4ba drm/amdgpu: create an empty bo_list if no handle is provided
Instead of having extra handling just create an empty bo_list when no
handle is provided.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:19 -05:00
Christian König
920990cb08 drm/amdgpu: allocate the bo_list array after the list
This avoids multiple allocations for the head and the array.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:19 -05:00
Christian König
39f7f69a60 drm/amdgpu: add bo_list iterators
Add helpers to iterate over all entries in a bo_list.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:19 -05:00
Christian König
a0f208453b drm/amdgpu: nuke amdgpu_bo_list_free
The RCU grace period is harmless and avoiding it is not worth the effort
of doubling the implementation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:18 -05:00
Christian König
81c6dabcc9 drm/amdgpu: always recreate bo_list
The bo_list handle is allocated by OP_CREATE, so in OP_UPDATE here we just
re-create the bo_list object and replace the handle. This way we don't
need locking to protect the bo_list because it's always re-created when
changed.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:18 -05:00
Christian König
4a8c21a1e9 drm/amdgpu: move bo_list defines to amdgpu_bo_list.h
Further demangle amdgpu.h

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:18 -05:00
Christian König
8ab19ea619 drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function v2
This allows us to trace all VM ranges which should be valid inside a CS.

v2: dump mappings without BO as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Reviewed-and-tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> (v1)
Reviewed-by: Huang Rui <ray.huang@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:17 -05:00
Christian König
0cb7c1f03b drm/amdgpu: return error if both BOs and bo_list handle is given
Return -EINVAL when both the BOs as well as a list handle is provided in
the IOCTL.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:17 -05:00
Christian König
275105ce7b drm/amdgpu: fix total size calculation
long might only be 32bit in size and we can easily use more than 4GB
here.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:16 -05:00
Christian König
52c054caf8 drm/amdgpu: add proper error handling to amdgpu_bo_list_get
Otherwise we silently don't use a BO list when the handle is invalid.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:16 -05:00
Rex Zhu
ccf9ef0b0d drm/amdgpu: fix a reversed condition
This test was reversed so it would end up leading to vddnb value
can't be read via hwmon on APU.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-07-31 16:58:12 -05:00
Rex Zhu
8a50bb47a8 drm/amd/pp: Convert voltage unit in mV*4 to mV on CZ/ST
the voltage showed in debugfs and hwmon should be in mV

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-07-31 16:58:06 -05:00
Rex Zhu
90983631a6 drm/amd/pp: Delete unused temp variables
Only delete the dead temp variables in Polaris.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:06 -05:00
Rex Zhu
2d227ec2c1 drm/amd/pp/Polaris12: Fix a chunk of registers missed to program
DIDTConfig_Polaris12[] table missed a big chunk of data.

Pointed by aidan.fabius <aidan.fabius@coreavi.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-07-31 16:58:02 -05:00
Huang Rui
2e603d0429 drm/amdgpu: clean up the superfluous space and align the comment text for amdgpu_ttm
This patch cleans up spaces and align the text to refine the comment for
amdgpu_ttm.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 15:00:38 -05:00
Junwei Zhang
204029e197 drm/amdgpu: correct evict flag for bo move
pass the evict flag instead of hard code

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 15:00:29 -05:00
Alex Deucher
f1e582ebfd drm/amdgpu: implement harvesting support for UVD 7.2 (v3)
Properly handle cases where one or more instance of the IP
block may be harvested.

v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c
v3: rebase on Christian's UVD changes, drop unused var

Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:44 -05:00
Harry Wentland
d04cc604a6 drm/amd: Add missing fields in atom_integrated_system_info_v1_11
This structure needs to align with structure in atomfirmware table.
Update it.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:43 -05:00
Harry Wentland
116f451c90 drm/amd/display: DC 3.1.59
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:43 -05:00
Anthony Koo
9907704174 drm/amd/display: Prevent PSR from being enabled if initialization fails
[Why]
PSR_SET command is sent to the microcontroller in order to initialize
parameters needed for PSR feature, such as telling the microcontroller
which pipe is driving the PSR supported panel. When this command is
skipped or fails, the microcontroller may program the wrong thing if
driver tries to enable PSR.

[How]
If PSR_SET fails, do not set psr_enable flag to indicate the feature is
not yet initialized.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:43 -05:00
Jerry (Fangzhi) Zuo
f358b39d18 drm/amd/display: Fix Vega10 black screen after mode change
[Why]
The sequence is slightly changed when bring .set_bandwidth out
from the end of programming backend to the end of programming
surface. Vega10 doesn't like to get clocks updated if
stream_count is zero in the current context (Atomic Reset).

[How]
Do not update clocks if no stream is showing up in the context.

Fixes 1b2b130192 "dc: Remove 300Mhz minimum disp clk limit."

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:42 -05:00
Bhawanpreet Lakha
65c78961b3 drm/amd/display: flatten aux_engine and engine
[Why]
engine and aux_engine are unnecessary layers we want to remove this
layer.

[How]
flatten engine and aux engine structs into one struct called
aux_engine and remove all references to the engine struct.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:42 -05:00
Bhawanpreet Lakha
824474ba38 drm/amd/display: Retry link training again
[Why]
Some receivers seem to fail the first link training but are good on
subsequent tries. We want to retry link training again. This fixes
HTC vive pro not lighting up after being disabled.

[How]
Check if the link training passed without fall back if this is not
the case then we retry link training.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:42 -05:00
Christian König
66c28d6df2 drm/amdgpu: patch the IBs for the second UVD instance v2
Patch the IBs for the second UVD instance so that userspace don't need
to care about the instance they submit to.

v2: use direct IB patching

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-and-tested-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:41 -05:00
Christian König
9d248517d4 drm/amdgpu: add support for inplace IB patching for MM engines v2
We are going to need that for the second UVD instance on Vega20.

v2: rename to patch_cs_in_place

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-and-tested-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:41 -05:00
Jia-Ju Bai
586092ab4b gpu: drm: amdgpu: Replace mdelay with msleep in cik_pcie_gen3_enable()
cik_pcie_gen3_enable() is only called by cik_common_hw_init(), which is
never called in atomic context.
cik_pcie_gen3_enable() calls mdelay() to busily wait, which is not
necessary.
mdelay() can be replaced with msleep().

This is found by a static analysis tool named DCNS written by myself.

Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:40 -05:00
Alex Deucher
6cdf4e87b4 drm/amdgpu/gmc9: clarify GPUVM fault error message
The address printed is the actual address, not the page.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:40 -05:00
Nayan Deshmukh
068c330419 drm/scheduler: remove sched field from the entity
The scheduler of the entity is decided by the run queue on which
it is queued. This patch avoids us the effort required to maintain
a sync between rq and sched field when we start shifting entites
among different rqs.

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:26 -05:00
Nayan Deshmukh
cdc5017659 drm/scheduler: modify API to avoid redundancy
entity has a scheduler field and we don't need the sched argument
in any of the functions where entity is provided.

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:19 -05:00
Christian König
bf314ca3f1 drm/amdgpu: reduce the number of placements for a BO
Make struct amdgpu_bo a bit smaller.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:13 -05:00
Christian König
c704ab18e0 drm/amdgpu: consistenly name amdgpu_bo_ functions
Just rename functions, no functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:06 -05:00
Christian König
4d4831a3da drm/amdgpu: expose only the first UVD instance for now
Going to completely rework the context to ring mapping with Nayan's GSoC
work, but for now just stopping to expose the second UVD instance should
do it.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:05:32 -05:00
Christian König
f8a91d4555 drm/amdgpu: clean up coding style a bit
No need to bitcast a boolean and even if we should use "!!" instead.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:05:08 -05:00
Harry Wentland
bb805f2b20 drm/amd/display: DC 3.1.58
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:16:07 -05:00
Jun Lei
cfd84fd365 drm/amd/display: separate dc_debug into dc_debug_options and dc_debug data
[why]
confusing as to which part of debug is informational, and which part causes behavioral change

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:59 -05:00
Bhawanpreet Lakha
5c6ac7112f drm/amd/display: Decouple aux from i2c
[Why]
Aux engine is created from i2caux layer. We want to remove this layer
and use the engine directly.

[How]
Decouple aux engine from i2caux. Move aux engine related code to dce folder and use
dc resource pool to manage the engine. And use the engine functions directly

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:50 -05:00
vikrant mhaske
3fc9fc4cf5 drm/amd/display: DPP CM ICSC AYCRCB8888 format support
[why]
Diags has POR to run the video workload using AYCRCB8888 through DCN;
capture it through DWB and send it to VCN hardware to encode

[how]
added the code to support this format so that DPP ICSC will be able to
convert it from YUV444 to internal RGB and DWB OCSC will be able to
convert from internal RGB to YUV420

Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:41 -05:00
David Francis
278ca8d677 drm/amd/display: On dce100, set clocks to 0 on suspend
[Why]
When a dce100 asic was suspended, the clocks were not set to 0.
Upon resume, the new clock was compared to the existing clock,
they were found to be the same, and so the clock was not set.
This resulted in a pernicious blackscreen.

[How]
In atomic commit, check to see if there are any active pipes.
If no, set clocks to 0

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:30 -05:00
Tony Cheng
aafded8885 drm/amd/display: allow diags to skip initial link training
[why]
diag specify what the full config and is only concerned about pass/fail at the end

having inter-op code like verifiying we can actually train at reported link rate
slows down diag test and add complexity we don't need

[how]
add dc_debug option to skip capability link trianing

also  remove hbr in function name as verify is not specific to hbr

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Ken Chalmers <ken.chalmers@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:14 -05:00
Mikita Lipski
85344e75d0 drm/amd/display: Remove unnecessary warning
[why]
The warning message floods the dmesg log on Tonga even
though it is expected to have a pix_clk set to zero,
when the pipe is not active.
[how]
remove the assert

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:02 -05:00
Shirish S
5f8181733f drm/amdgpu: move the amdgpu_fbdev_set_suspend() further up
This patch moves amdgpu_fbdev_set_suspend() to the beginning
of suspend sequence.

This is to ensure fbcon does not to write to the VRAM
after GPU is powerd down.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:54 -05:00
Michel Dänzer
456607d816 drm/amdgpu: Don't warn on destroying a pinned BO
The warning turned out to be not so useful, as BO destruction tends to
be deferred to a workqueue.

Also, we should be preventing any damage from this now, so not really
important anymore to fix code doing this.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:45 -05:00
Evan Quan
92859e0d5c drm/amd/powerplay: allow slow switch only if NBPState enabled v2
Otherwise there may be potential SMU performance issues.

v2: fix commit description and coding style

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rex.zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:35 -05:00
Evan Quan
f132d56162 drm/amd/powerplay: correct the argument for PPSMC_MSG_SetUclkFastSwitch
The argument was set wrongly. Fast/slow switch was asked when there is
actually a slow/fast switch needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rex.zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:25 -05:00